JPH01305535A - Lsi wiring film - Google Patents
Lsi wiring filmInfo
- Publication number
- JPH01305535A JPH01305535A JP13696588A JP13696588A JPH01305535A JP H01305535 A JPH01305535 A JP H01305535A JP 13696588 A JP13696588 A JP 13696588A JP 13696588 A JP13696588 A JP 13696588A JP H01305535 A JPH01305535 A JP H01305535A
- Authority
- JP
- Japan
- Prior art keywords
- film
- aluminum
- wiring
- wiring film
- stress
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims abstract description 18
- 229910052782 aluminium Inorganic materials 0.000 claims abstract description 17
- 238000002161 passivation Methods 0.000 claims abstract description 14
- 229910000838 Al alloy Inorganic materials 0.000 claims abstract description 8
- 230000000630 rising effect Effects 0.000 claims description 3
- 239000011800 void material Substances 0.000 claims description 2
- 238000000034 method Methods 0.000 abstract description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 3
- 238000005530 etching Methods 0.000 abstract description 3
- 229910052710 silicon Inorganic materials 0.000 abstract description 3
- 239000010703 silicon Substances 0.000 abstract description 3
- 150000004767 nitrides Chemical class 0.000 abstract description 2
- 238000004544 sputter deposition Methods 0.000 abstract description 2
- 230000002035 prolonged effect Effects 0.000 abstract 1
- 230000000694 effects Effects 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 238000000386 microscopy Methods 0.000 description 1
- 238000013508 migration Methods 0.000 description 1
- 230000005012 migration Effects 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明はアルミニュウムあるいはアルミニュウム合金膜
からなるＬ Ｓ Ｉ ｉ！ｉｃ！線膜に関するものであ
る。[Detailed Description of the Invention] [Industrial Field of Application] The present invention provides an LSI i! film made of aluminum or an aluminum alloy film. ic! It concerns the membrane.
ＬＳＩの配線材料として、現在アルミニュウムあるいは
アルミニュウム合金膜が用いられている。Aluminum or aluminum alloy films are currently used as wiring materials for LSIs.
従来この様な配線膜においては、エレクトロマイクレー
ジョンによる配線の断線発生がよく知られており、その
研究かされていたが、最近、エレクトロマイグレーショ
ンではなくとも、別の原因により配線に断線か生じるこ
とかあり、これかＬ ＳＩの信頼性に関わる問題として
注目されている。Conventionally, in such wiring films, it is well known that wire breakage occurs due to electromigration, and this has been studied, but recently it has been reported that wire breakage may occur due to other causes, even if it is not electromigration. For this reason, this is attracting attention as an issue related to the reliability of LSI.
このような断線の原因としては配線に働く応力に起因し
ているとしてストレスマイクレージョンと呼ばれ、例え
は、ＳＥＭＩテクノロジーシンポジウム°８７講演予稿
集（Ｐ、３１３ ）にその手崎衆氏により報告がなされ
ている。The cause of such wire breakage is called stress microreaction, as it is caused by stress acting on the wiring. being done.
このストレスマイクレージョンによる断線に関しては種
々のパッシベーション膜についてその原因が調へられて
いるが、前記報告例にもある様に、配線にストレスかか
かっていることが主なる原因と考えられ、パッシベーシ
ョン膜の種類あるいは形成方法を単に変えるたけでは、
これらのス１〜レスを緩和することは困難であった。The causes of wire breakage due to stress microscopy have been investigated in various passivation films, but as mentioned in the above report, stress on the wiring is thought to be the main cause, and passivation film Simply changing the type of film or the method of forming it will not work.
It has been difficult to alleviate these stresses.
本発明の目的はこの様な従来の問題点を解決し、配線の
ストレスを低減すると共に、たとえ、ストレスかかかっ
てもス１〜レズを緩和できる様な構造にし、配線膜の断
線をなくすることにある。The purpose of the present invention is to solve these conventional problems, to reduce the stress on the wiring, and to create a structure that can alleviate the stress even if stress is applied, thereby eliminating disconnection of the wiring film. There is a particular thing.
上記目的を達成するため、本発明のＬＳＩ配線膜におい
ては、絶縁膜」−に、パッシベーション膜で上面及び側
方覆われた断面構造が逆デーパ状のアルミニュウムある
いはアルミニュウム合金配線膜を有し、前記配線膜の逆
テーパ状立上り部とその側方のパッシベーション膜との
間に空隙を設すなものである。In order to achieve the above object, the LSI wiring film of the present invention has an aluminum or aluminum alloy wiring film whose top surface and sides are covered with a passivation film and whose cross-sectional structure is inversely tapered, in the insulating film. A gap is provided between the inverted tapered rising portion of the wiring film and the passivation film on the side thereof.
配線膜の断線の原因としては配線膜にパッシベーション
膜から印加される応力によると考えられている。従って
配線膜に印加される応力を低減するかあるいは、たとえ
応力が印加されたとしても緩和できる構造になっていれ
ば断線の原因が除かれる。従って、配線膜の断面構造を
逆テーパ状に加工し、その面と下地絶縁膜あるいは、パ
ッシベーションｊ摸とに囲まれる部分に空隙を設けるこ
とにより、パッシベーション膜から印加される応力を低
減すると共に、たとえ応力がかかったとじても、配線膜
の変位を許容する空隙が存在しているため、この部分で
応力緩和がなされ、断線を防ぐことが可能となる。It is believed that the cause of disconnection in the wiring film is stress applied to the wiring film from the passivation film. Therefore, if the stress applied to the wiring film is reduced, or if the structure is such that even if stress is applied, it can be relaxed, the cause of wire breakage can be eliminated. Therefore, by processing the cross-sectional structure of the wiring film into a reverse tapered shape and providing a gap between the surface and the underlying insulating film or passivation pattern, the stress applied from the passivation film can be reduced, and Even if stress is applied, there is a gap that allows the wiring film to be displaced, so stress is relaxed in this area, making it possible to prevent wire breakage.
以下、本発明をその実施例にもとづいて詳細に説明する
。Hereinafter, the present invention will be explained in detail based on examples thereof.
第１図は本発明の実施例に用いた試料の断面構造を示ず
。図において、シリコン基板１上に、酸化膜からなる絶
縁膜２を形成する。次に、スパッタ法を用いてアルミニ
ュウム１１０（またはアルミニュウム合金膜）を全面に
イ」着さぜな後、通常のレジスト工程を用いてアルミニ
ュウム膜をバターニングする。アルミニュウム膜はＲＩ
Ｅを用いてエツチングを行ってアルミニュウム配線膜３
を形成するが、そのエツヂンク時間を多少長くしてアル
ミニュウム配線膜３の幅方向の断面構造を逆デーパ状に
加工する。次に、ＣＶ Ｉ）法により酸化膜を付着させ
る。このとき、配線３の逆テーパ状立上り部の両側には
空隙５が生じる。さらに、窒化膜を付着し、パッシベー
ション膜４を形成する。以上の方法でアルミニュウム又
はアルミニュウム合金配線膜３を形成することにより、
配線膜にかがる応力特に、配線膜３の側方のパッシベー
ション膜４より加えられる応力を極めて低減することが
でき、さらに１、空隙５がわずかに存在するためにたと
え、応力がかかったとしてもアルミニュウム配線膜３の
応力が緩和され、スＩ・レスマイグレーションによる断
線を防止される。 ・〔発明の効果〕
以上のように本発明の構造によるときには配線膜にかか
る応力を低減し、さらに、応力かかかってもその応力を
緩和して断線を防止できる。なお、本発明においては、
空隙は配線膜の側面にわずかに存在しているたけである
ため、配線膜の信頼性を極端に悪化させず、実用上問題
が生ずることかない。FIG. 1 does not show the cross-sectional structure of a sample used in an example of the present invention. In the figure, an insulating film 2 made of an oxide film is formed on a silicon substrate 1. Next, aluminum 110 (or an aluminum alloy film) is deposited on the entire surface using a sputtering method, and then the aluminum film is patterned using a normal resist process. Aluminum film is RI
The aluminum wiring film 3 is etched using E.
However, the etching time is increased somewhat to process the cross-sectional structure of the aluminum wiring film 3 in the width direction into a reverse taper shape. Next, an oxide film is deposited by CV I) method. At this time, a gap 5 is created on both sides of the reversely tapered rising portion of the wiring 3. Furthermore, a nitride film is deposited to form a passivation film 4. By forming the aluminum or aluminum alloy wiring film 3 by the above method,
The stress applied to the wiring film, especially the stress applied from the passivation film 4 on the sides of the wiring film 3, can be extremely reduced.1. Even if stress is applied due to the presence of a slight void 5, Also, stress in the aluminum wiring film 3 is relaxed, and disconnection due to I/less migration is prevented. - [Effects of the Invention] As described above, according to the structure of the present invention, the stress applied to the wiring film can be reduced, and even if stress is applied, the stress can be alleviated and disconnection can be prevented. In addition, in the present invention,
Since the voids are only slightly present on the side surfaces of the wiring film, the reliability of the wiring film is not extremely deteriorated, and no practical problems arise.
第１図は本発明の実施例を示す試料の断面構造を示ず図
である。
１・・・シリコン基板 ２・・・絶縁膜３・・・
アルミニュウム配線膜
４２．・パッシベーション１摸
５・・・空隙
特許出願人 日本電気株式会社FIG. 1 is a diagram without showing the cross-sectional structure of a sample showing an example of the present invention. 1... Silicon substrate 2... Insulating film 3...
Aluminum wiring film 42.・Passivation 1 5...Gap patent applicant NEC Corporation
Claims (1)
覆われた断面構造が逆テーパ状のアルミニュウムあるい
はアルミニュウム合金配線膜を有し、前記配線膜の逆テ
ーパ状立上り部とその側方のパッシベーション膜との間
に空隙を設けたことを特徴とするＬＳＩ配線膜。(1) An aluminum or aluminum alloy wiring film having an inverted tapered cross-sectional structure covered with a passivation film on the upper surface and the sides is formed on the insulating film, and the inverted tapered rising portion of the wiring film and the passivation film on its sides are formed on the insulating film. An LSI wiring film characterized in that a void is provided between the film and the film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13696588A JPH01305535A (en) | 1988-06-02 | 1988-06-02 | Lsi wiring film |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13696588A JPH01305535A (en) | 1988-06-02 | 1988-06-02 | Lsi wiring film |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01305535A true JPH01305535A (en) | 1989-12-08 |
Family
ID=15187625
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13696588A Pending JPH01305535A (en) | 1988-06-02 | 1988-06-02 | Lsi wiring film |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01305535A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0536681A (en) * | 1991-07-29 | 1993-02-12 | Nec Corp | Semiconductor device |
| EP1109219A2 (en) * | 1999-12-15 | 2001-06-20 | Shinko Electric Industries Co. Ltd. | Semiconductor device having a wiring layer |
-
1988
- 1988-06-02 JP JP13696588A patent/JPH01305535A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0536681A (en) * | 1991-07-29 | 1993-02-12 | Nec Corp | Semiconductor device |
| EP1109219A2 (en) * | 1999-12-15 | 2001-06-20 | Shinko Electric Industries Co. Ltd. | Semiconductor device having a wiring layer |
| EP1109219A3 (en) * | 1999-12-15 | 2003-11-12 | Shinko Electric Industries Co. Ltd. | Semiconductor device having a wiring layer |
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