JPH01303883A - Video data processing circuit - Google Patents

Abstract

PURPOSE:To attain easy to see pattern and to simplify the circuit constitution in case of applying the circuit for a channel search function or the like by controlling an inverted write enable (inverse of WE) signal so as to compress only a video part and to write the result into a picture memory. CONSTITUTION:A signal synchronously with a horizontal synchronizing signal is shaped into a reset pulse with one clock width by a waveform shaping circuit 41 to reset a horizontal counter 42, a bit shift circuit 43 applies bit shift to an output of the horizontal counter 42 and to output a compressed data. The output is added to a constant representing a display location outputted from a selector 45 at an adder circuit 44 and the result is outputted as a horizontal address. On the other hand, an inverse of WE signal generating circuit 47 generates an inverse of WE signal so as to write only a required part from an output of the bit shift circuit 43 into a memory. Since the inverse of WE signal is controlled so as to compress only the video part and to write it into a memory in this way, the address control to disappear the blanking part from the screen is attained. Thus, the screen is devised to be observed easily in case of applying the title circuit to a channel search or the like and the circuit constitution is simplified.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a video data processing circuit used for realizing a channel search function in a television receiver, for example.

(Prior Art) In recent years, large-capacity memory for images (field memory) has been applied to provide television receivers with various special functions.

For example, there is a function called channel search.

As shown in FIG. 4, this reduces all the programs currently being broadcast and displays them simultaneously. This function allows viewers to compare programs being broadcast in the same time slot and select their favorite program.

FIG. 5 is a diagram illustrating a conventional video data processing circuit used to realize the channel search function.

First, an RF multiplied signal input from an input terminal 1 is detected by a tuner 2, and a baseband composite signal is sent to a decoder 3. The decoder 3 decodes the composite signal to obtain signals having components of, for example, Y, BY, and RY, and sends them to AD converters 5 to 7, respectively.

AD converters 5-7 digitize these signals and send them to field memories (FM) 9-11. Each field memory receives an address value and a control signal from an address generation circuit 8, and receives an address value and a control signal from an AD converter 5 to 7.
Store the signal from.

The address generation circuit 8 generates a write address value and a control signal based on the signal from the synchronization circuit 4, and generates a read address value and control signal based on the signal received from the read synchronization generation circuit 12, respectively. I am sending it to 9-11.

When video data corresponding to one channel is written, the channel switching signal generation circuit 13 generates a channel switching signal and sends it to the tuner 3, and the tuner 2 detects the next channel.

On the other hand, the channel switching signal is also sent to the address generation circuit 8. Address generation circuit 8 outputs a control signal to field memories 9 to 11 so as to write again in response to this channel switching signal.

The outputs of the field memories 9-11 are then sent to DA converters 14-16 and converted into analog signals.

In the example of FIG. 4, the 1B screen is displayed on the same screen. The memory areas of field memories 9 to 11 are allocated to 16 blocks corresponding to the screens as shown in FIG. 6, and information for one screen is written in each block.

By the way, in the field memories 9 to 11, addresses are specified separately in the horizontal direction and the vertical direction.

For example, 1024 samples horizontally and 25 samples vertically.
For sample B, one screen is stored at addresses 0 to 255 horizontally and 0 to 63 vertically, and another screen is stored at addresses 256 to 511 horizontally and 0 to 63 vertically. Control addresses such as storing the screen. Address generation circuit 8 performs this address control.

FIG. 7 is a diagram showing an example of the configuration of the write address generation section in the address generation circuit 8, and FIG. 8 is a diagram showing the timing of each signal.

First, a signal b (FIG. 8b) synchronized with the horizontal synchronization signal is applied to the input terminal 20 from the synchronization circuit 4 (FIG. 5).

This signal S is a signal that rises in the middle of the horizontal synchronizing signal H5 of the composite signal a. This signal is shaped into a one-clock width in the waveform shaping circuit 21 and becomes a signal C (C in FIG. 8), which resets the horizontal counter 22. The horizontal counter 22 starts counting from the time of reset, and counts from 0 to 023.
024 types of data are output.

This output is then sent to the bit shift circuit 23. In the bit shift circuit 23, in order to display four screens in the horizontal direction of the screen, the address is shifted by 2 bits and the data is
It is compressed to /4. Therefore, the counter is 0 to 102
While counting up to 3, data from 0 to 255 is output.

This data is sent to the addition circuit 24 and added to the horizontal bias output from the horizontal bias generation circuit 25.

On the other hand, the vertical synchronization signal from the synchronization generation circuit 4 is applied to the terminal 26, is shaped by the waveform shaping circuit 27, and resets the vertical counter 28. and bit shift circuit 29
The output of the vertical counter 28 is bit-shifted, and the vertical bias is added in the adder circuit 30.

Note that each bias value is fixed depending on the display position. For example, in the case of displaying in the part marked ■ in FIG. 4, the output of the horizontal bias generation circuit 25 is 256, and the output of the vertical bias generation circuit 31 is
The output of is 0.

(Problem to be Solved by the Invention) By the way, according to the address generated by the address generation circuit as described above, writing to the field memory is performed during the period S in FIG. 8, but the video portion in this period S is There is only a period of X, and a period of y%2 is a blanking or sync tip portion.

In other words, when writing to the field memory is performed in the process described above, blanking portions are also displayed, but according to this, the blanking portions appear black at the edges of each screen, as shown in Figure 9. The screen becomes very unsightly.

In order to prevent this blanking part from appearing on the screen, only the data of the video part must be condensed and written.

If the address counter is stopped for the period y5z in Fig. 8, only the period X in Fig. 8 will be written to the memory, so only the video can be condensed and written to the memory, but in order to do this, y, z Since a counter is required to count the period of , the entire circuit configuration becomes extremely complicated.

The present invention has been made under these circumstances, and aims to provide a video data processing circuit that makes the screen easier to see when used to implement functions such as channel search, and has a simple circuit configuration.

[Configuration of the Invention (Means for Solving the Problems)] In order to achieve this object, the video data processing circuit of the present invention includes an image memory into which video data consisting of bit components in the horizontal and vertical directions is to be written; a first counter that counts horizontal bit components of the video data, a second counter that counts vertical bit components of the video data, bit shifting means that shifts the output of each counter, and the image data. address generation means for outputting a plurality of write address values for the memory; address selection means for selecting one of the address values; and address generation means for outputting a plurality of write address values for the memory; and write enable signal control means for controlling a write enable signal of the memory.

(Function) In the video data processing circuit of the present invention, the write enable signal is controlled so that unnecessary data accompanying video data is not written to the image memory. , the blanking part can be erased without incrementing an extra counter.

(Example) Hereinafter, details of an example of the present invention will be described based on the drawings.

This embodiment differs from the conventional video data processing circuit shown in FIG. 5 only in the address generation circuit, so only the address generation circuit will be described below.

Further, in this embodiment, since the same processing is performed on both the horizontal bit component and the vertical bit component of video data, only the horizontal bit component will be described below.

In FIG. 1, 40 is an input terminal to which a video signal from a synchronization circuit is applied, 41 is a waveform shaping circuit that shapes the video signal, 42 is a horizontal counter that counts horizontal bit components of the video signal, and 43 is a horizontal counter that counts horizontal bit components of the video signal. A bit shift circuit 44 shifts the output of the I counter, and an addition circuit 44 adds the signal output from the bit shift circuit 43 and the signal from the selector 45.The selector 45 selects an address as described later. 46 is a channel switching signal generation circuit that generates a channel switching signal;
Reference numeral 47 represents a W child signal generation circuit for generating a write enable signal (hereinafter referred to as WE multiplied signal), and 48 to 51 are constant generation circuits to be described later.

First, a signal synchronized with a horizontal synchronization signal from a synchronization circuit (not shown) is applied to the input terminal 40.

This signal is shaped into a one clock width reset pulse by the waveform shaping circuit 41, and becomes a signal for resetting the horizontal counter 42. This horizontal counter 42 is, for example, 0 to 10.
Outputs 1024 data up to 23.

The bit shift circuit 43 bit-shifts the output of the horizontal counter 42.

For example, when displaying 16 screens, each screen's water 1
Since it is necessary to compress the data to 1/4 in the direction B and to 1/4 in the vertical direction, the bit shift circuit 43 outputs data from 0 to 255. This output is added in an adder circuit 44 to a constant indicating the display position output from the selector 45, and output as a horizontal address.

On the other hand, in the WE signal generation circuit 47, the bit shift circuit 4
W to write only the necessary part from the output of step 3 into memory.
E-fold signal is generated.

FIG. 2 is a diagram showing the timing of each signal in this embodiment.

In FIG. 2, β is the write inhibit period including the back porch side y of the horizontal blanking period, γ is the write inhibit period including the front porch side 2 of the horizontal blanking period, and δ is the period for writing to the memory.

When writing a sample of video data for a period of δ to the memory as a horizontal component of one screen in channel search, a period of β or The period γ is a write-protected portion.

By writing each channel search screen by δ in the horizontal direction, it is possible to prevent the blanking portion from being displayed on the screen.

The above process is exactly the same for the vertical bit components.

FIG. 3 shows a memory map of the field memory in this embodiment, which corresponds to the display screen. In this field memory, horizontal addresses are 0 to 102.
3, and the addresses of the first column from the left are α1 from the end, the second column is α2 from the end, the third column is α3, and the address of the fourth column is α4. These values of α1 to α4 are determined by constant generators 48 to
51 and sent to the selector 45.

The output value SC of the bit shift circuit 43 is 0 to 255.
86 samples of the child screen are sampled during the write permission period δ shown in FIG. 4) Written to address.

For example, in the case of the screen displayed at the position (■) in FIG. 3, 86 samples during the write period δ are written to addresses α1 to αl+sδ. If the address value is A, then A
varies from 0 to 1023.

If Sβ is the number of samples in the write-protection period β on the back porch side in FIG. 2, and Sγ is the number of samples in the write-protection period γ on the front porch side in FIG. 2, then Sβ+Sγ+S
It is δ-256. That is, the output α1 (i-1 to 4) of the A near address SC two-bit shift circuit 43: the value of the address from the end of the memory area (constant) α2-αl+sδ α3 α2+sδ-α1+2Sδ α4-α3+Sδ α1+3Sδ Sβ; left side When the number of samples in the deleted part (constant) Sγ: the number of samples in the deleted part on the right side (constant) Sδ: the number of samples written to the memory area (constant), the address is represented by the formula: A-5C+(αi- Sβ) The case of writing in the upper left part (■) of FIG. 3 will be specifically explained.

First, when the output value SC of the bit shift circuit 43 is between 0 and Sβ, the field memory is set in a state in which WE multiplied signal writing is prohibited, that is, it is set at It I gh level. At this time, address A changes from α1-5β to α1.

When SC is between Sβ and Sβ+Sδ, the WE double signal write is enabled, that is, the Loν level is set.

At this time, address A changes from α1 to αl+sδ.

When SC is between Sβ+Sδ and Sβ+Sδ+Sγ, the WE double signal is prohibited. At this time, address A is αl+sδ
~αl+sδ+Sγ.

Next, the case of writing in the second column of FIG. 2, for example, the part marked ■, will be specifically explained.

When SC is between 0 and Sβ, WE multiplication signal write is prohibited. At this time, address A changes from α2-sβ to α2, and the address value overlaps with the right end of the part marked ■, but W
Since writing of the E times signal is prohibited, the contents of the part marked ■ do not change.

Next, when SC is between Sβ and Sβ+Sδ, the WE double signal write permission is deaf. At this time, address A is α2 to α2
The value changes to +sδ, and data is written in the portion marked ■.

Furthermore, if SC is between Sβ+Sδ and Sβ+Sδ+Sγ, W
E times signal writing ■ is stopped. At this time, address A changes from α2+sδ to α2+sδ+Sγ.

The above relationships are summarized in the table below.

Thus, in this embodiment, the horizontal counter 42 only needs to keep counting, and the value of the address A is set in advance by the constant α1(
i-1 to 4), Sβ, Sγ, and Sδ are automatically set simply by storing them in the constant generation circuit. Then, the W1 signal of the memory is controlled so that only the video part is condensed and written to the memory so that the blanking part is not displayed on the screen, so address control is performed so that the blanking part is not displayed on the screen. I can do it.

Although this embodiment describes the case where the present invention is used to realize a channel search function, the present invention is not limited to this, and the present invention is not limited to this. This method can be widely applied to cases in which multiple images are simultaneously displayed on one screen.

[Effects of the Invention] As explained above, the video data processing circuit of the present invention has the following effects:
Since the WE multiplication signal of the memory is controlled so that only the video portion is condensed and written to the image memory, the blanking portion will not be displayed on the screen even if it is used to realize a channel search function, for example. And since we don't use any extra counters to stop or move the address counter,
The circuit configuration is simple.

[Brief explanation of the drawing]

FIG. 1 is a diagram illustrating the circuit configuration of an embodiment of the present invention, FIG. 2 is a diagram illustrating the timing of each signal in the embodiment, and FIG. 3 is a diagram illustrating a memory map of the field memory in the embodiment. , FIG. 4 is a diagram illustrating a display example in channel search, FIG. 5 is a diagram illustrating the circuit configuration of a conventional video data processing circuit, FIG. 6 is a diagram illustrating a memory map of the field memory in the conventional example, FIG. 7 is a diagram showing an example of the configuration of the write address generation section of the address generation circuit in the same embodiment, FIG. 8 is a diagram showing the timing of each signal in the conventional video data processing circuit, and FIG. 9 is a diagram showing the timing of each signal in the conventional video data processing circuit. FIG. 2 is a diagram illustrating a problem with a processing circuit. 40... Input terminal, 41 Waveform shaping circuit, 42... Horizontal counter, 43... Bit shift circuit, 44...
Adder circuit, 45...Selector, 46...Channel switching signal generation circuit, 47...WE generation circuit, 48~
51...Constant generation circuit. Applicant Toshiba Corporation Patent Attorney Satoshi Suyama - Horizontal Address → Figure 3 Figure 4 1] 1 [' 1 Horizontal Address Figure 6 Figure 7 25″ Figure 9

Claims (1)

[Claims] (1) An image memory into which video data consisting of horizontal and vertical bit components is to be written, a first counter that counts the horizontal bit components of the video data, and a first counter that counts the horizontal bit components of the video data; a second counter for counting, a bit shifting means for shifting the output of each counter, an address generating means for outputting a plurality of write address values for the image memory, and an address selecting means for selecting one of the address values. and write enable signal control means for controlling a write enable signal of the image memory so that unnecessary data accompanying the video data is not written into the image memory.