JPH01292425A - Elastic store memory extending circuit - Google Patents

Abstract

PURPOSE:To omit a read/write (W/R) enable reset signal to be a chip selecting signal by writing data only into one LSI at the time of writing, and at the time of reading, reading out data from all LSIs but outputting data only from one LSI. CONSTITUTION:The title circuit is provided with a write address generating part (WAG) for generating a write address (WA) after resetting a write address counter (WAC) by a write reset signal (WR) and stopping the write address count-up of the WAC when the value of the WAC is maximized and a read address generating part (RAG) for generating a read address (RA) after resetting a read address counter (RAC) by a read reset signal (RR) and when the value of the RAC is maximized, generating a read counter reset signal (RCR) and allowing an output control part (OC) to control an output buffer (OB) by the RCR and the RR to control the output of data read out from a built-in memory.

Description

[Detailed Description of the Invention] [Summary] Each input data line and each output data line are commonly connected, each has a built-in memory, and the built-in memory is written and read by a write address counter and a read address counter, respectively. Regarding elastic store memory expansion circuits that expand memory capacity using multiple LSI circuits, the purpose of this is to eliminate the need to externally supply chip selection signals and reset signals for address counters from the second stage chip onwards. LSI circuits are connected in cascade, and each LSI circuit resets its address counter using a write/read reset signal, then starts a write/read operation, and generates a counter reset signal when the address counter value reaches the maximum. By stopping the write/read operation and using the counter reset signal as the write/read reset signal for the next stage, only one LS is used when writing.
The configuration is such that only the I circuit is written, and when reading, data is read from all LSI circuits, but data is output from only one LSI circuit.

[Industrial application field]

The present invention relates to an elastic store memory expansion circuit, in particular, each input data line and each output data line are commonly connected, each has a built-in memory, and the built-in memory is written and read by a write address counter and a read address counter, respectively. The present invention relates to an elastic store memory expansion circuit that expands memory capacity using a plurality of LSI circuits.

Elastic store memory circuits are used to absorb input signal phase fluctuations due to delay fluctuations and variations in the transmission path, and to adjust the frame phase of the input signal to a specific time position. An LSI circuit well known as a stick store memory circuit is shown in FIG. 6, in which a write reset signal WR is latched (
After the write address counter 20 is reset by being given as a reset signal to the write address counter 20, the counter 20 starts counting in response to the write clock signal WCK and generates a write address WA. The input data passes through the data register 40 and is stored at the address in the memory 10 specified by the write address counter 20.

In this case, in order to shift the timing, data register 4
The write clock WCR of 0 and the write clock WCR of memory 10 are different, and this write clock WCR is different from the write clock WCR of memory 10.
CR'' is obtained by ANDing the write enable WE and the write clock, and writes to the memory 10 are not performed unless the write enable WE is generated.

In addition, the flip-flop 50 and the write address counter 2
0 constitutes a write address generation unit WAG.

On the other hand, the data stored in the memory 10 is read (one after another) after the read address counter 30 is reset by the read reset signal RR via the flip-flop 70.
This is done by specifying an address by the read address counter 30 which starts counting in response to the read clock signal RCK. The read data is then output at the timing of the read clock signal RCK input to the data register 60. Incidentally, the flip-flop 70 and the read address counter 30 constitute a read address generation section RAG.

In such an elastic store memory circuit, it is necessary to expand the memory capacity as the amount of frame data to be processed increases.

[Conventional technology]

FIG. 7 shows a conventional example of an elastic store memory expansion circuit configured to expand the capacity of the elastic store memory circuit.
Prepare multiple circuits (two in this case), and each LSI circuit 1
Write enable signals WE1, WB2 and read enable signals RE1, RE2 as chip select signals corresponding to 3.14 are applied to LSI times N! They are provided from the outside of the i13 and i14 by the WE light generator 11 and the RE generator 12, respectively. A write clock signal WCK and a write clock signal RCK are applied to these enable signal generating sections 11 and 12, respectively. Further, the write reset signal WR and read reset signal RR of each LSI circuit are separate signals, and are also given from the outside.

The operation of such a circuit configuration will be explained with reference to the time chart of FIG.

First, in a write operation, as shown in FIG. 8(a), the WE light generator 11 generates a write enable signal WEI to enable the LSI circuit 13 and transfer input data to the built-in memory 10 (FIG. 6). Store in. At this time,
Since the write clock signal WCK is synchronized with the input data (because the data register 40 is used), the LSI
When the write clock signal WCK is counted up to the maximum count value of the write address counter 20 in the circuit 13, the write enable signal WEI is disabled and the write enable signal WE2 is enabled and turned low.
SI circuit 14 is selected as the data input chip. In this way, data is sequentially stored in the LSI circuits, but the write address counter 20 in each LSI circuit
is reset by receiving a write reset signal WR externally applied to each LSI circuit.

In the read operation, as shown in Figure 8 (b), R
E light generation 12 and read reset signals RRI and RR2 are applied to LSI circuits 13 and 14 in the same manner as in the write operation, and data is output in order for each chip.

In this way, memory capacity is expanded.

[Problem to be solved by the invention]

When using such a conventional elastic store memory expansion circuit, in addition to the need for a write enable generation section and a write enable generation section, the write reset signal and read reset signal are generated as individual elastic store memory expansion circuits. This is necessary for LSI circuits, which poses the problem of increasing the size of the device.

Therefore, the present invention provides a plurality of LSI circuits in which each input data line and each output data line are commonly connected, each has a built-in memory, and the built-in memory is written and read by a write address counter and a read address counter, respectively. In the elastic store memory expansion circuit that expands the memory capacity using chip selection signals and
The purpose of this invention is to eliminate the need to externally supply a reset signal for address counters on and after the stage chip.

[Means to solve the problem]

In order to achieve the above object, the present invention connects LSI circuits 1, 2, . . . in cascade as shown in principle in FIG. Then, each LSI circuit 1.2 resets the write address counter WAC by the write reset signal WR, and then generates the write address WA of the built-in memory, and when the write address counter WACO value reaches the maximum, a write counter reset signal is generated. A write address generation unit WAC generates WCR to stop the write address increment of the write address counter WAC, and a read address generator WAC generates a read address RA of the built-in memory after resetting the read address counter RAC with a read reset signal RR. and the read address counter R
When the value of AC reaches the maximum, a read counter reset signal RCR is generated and the read counter reset signal RCR is generated.
and the read reset signal RR, the output control section OC controls the output buffer OB to output the data read from the built-in memory.
It is equipped with In this case, since each LSI circuit is connected in cascade, the write counter reset signal WCR and read counter reset signal RCR are sent to the LS of the next stage.
These are the write reset signal WR and read reset signal RR of the I circuit. Although not shown in Figure 1,
Obviously, each address counter is supplied with a clock signal.

[For production]

In FIG. 1, a write reset signal WR and a read reset signal RR are applied from the outside only to the first stage LSI circuit 1.

First, in the write operation, the write reset signal WR
is input to the write address generator WAG, the write address counter WAC is reset and starts counting, generates the write address WA of the built-in memory M1 and stores the input data, but after that, the count of the write address counter WAC is When the value reaches the maximum, the write address generator WAG outputs the write counter reset signal WCR.
is generated to stop incrementing the write address of the write address counter WAC and stop storing the input data in the memory M1.

In the second and subsequent stages of LSI circuits 2, the write counter reset signal WCR and read counter reset signal RCR of the previous stage LSI circuit become the write reset signal WR and read reset signal RR of the next stage LSI circuit, respectively. Therefore, the built-in memory Ml of the first stage LSI circuit 1
After writing data to the second stage LSI circuit 2,
The input data is written into the built-in memory M2. In this way, input data is sequentially stored in the built-in memory of the next-stage LSI circuit.

In a read operation, the read address generator RAG receives the read reset signal RR, resets the read address counter RAC, and then starts the read address counter R.
Counting of AC is started, a read address RA of the built-in memory is generated, and data stored in the memory is read.

Then, when the count value of the read address counter RAC reaches the maximum, the read address generation unit RAG generates a read counter reset signal RCR, and outputs the read address generation unit RAG from the read counter reset signal RCR and the read reset signal RR. Control part O
C controls the output buffer OB and outputs the data read from the built-in memory. That is, data is output in response to a read reset signal RR, and data output is inhibited in response to a read counter reset signal RCR.

Therefore, after reading the data stored in the built-in memory M1 of the first-stage LSI circuit 1, the data stored in the built-in memory M2 of the second-stage LSI circuit 2 will be read. Become.

In this way, write/read operations are performed separately and sequentially on the cascaded LSI circuits without using unnecessary external circuits or signals.

〔Example〕

FIG. 2 shows a write address generation unit WAG used in the elastic store memory expansion circuit of the present invention shown in FIG.
FIG. 3 shows an example of the read address generation section RA.
An example of G is shown.

Note that the conventional LSI circuit configuration shown in FIG. 6 can be used for the other configurations.

The difference between the write address generation unit WAG in FIG. 2 and the write address generation unit WAG in FIG. 6 is that a counter control unit 3 is provided. Write reset signal WR
(only the first stage LSI circuit 1 is required), a write clock signal WCK, and a write counter reset signal WCR which is a carry signal of the write address counter WAC are input, and a write clock signal WCK' is output.

This write clock signal WCK' serves as a clock for advancing the count of the write address counter WAC, and is also provided to the built-in memory 10 (also corresponding to the memories M1 and M2 in FIG. 1).

The difference between the read address generation section RAG in FIG. 3 and the write address generation section WAG in FIG. 6 is that an output control section 4 is provided. Read reset signal RR (necessary only for 1st stage LSI circuit 1), read clock signal RCK
, and a read counter reset signal RCR, which is a carry signal of the read address counter RAC, are input, and an output control signal CNT is output. This output control signal CN
T becomes the gate signal of output buffer ○B.

Next, FIG. 2 shows the write operation in the embodiment of the present invention.
The write address generation section WAG and read address generation section RAG shown in FIG. 3, the time charts of FIGS. 4 and 5, and the configuration of FIG.
(excluding).

First, to explain the write operation, the write reset signal WR latched by the flip-flop 50 of the LSI circuit 1 resets the write address counter (WAC) 20 and is sent to the counter control unit 3 to generate the write clock signal WCK'. do. This write clock signal WCK' is sent to memory 10 to enable writing to memory 10. After being reset, the write address counter 20 counts up every time the write clock signal WCK' is input, and counts up from the 0th to the Mth of the input data Di.
-1st (M-2": M and N are integers) are written to memory 1. In FIG. 4, when counting up to address M-2, a write counter reset WCR is generated as a carry signal. This is as follows. Write reset signal WR
Since the counter 20 starts counting with a delay of two clocks from the input of
The write counter reset signal WCR generated as a carry signal by the write address count 20 counted up to 0M-1 is input to the counter control unit 3, and the write counter reset signal WCR is input to the counter control unit 3, The generation of WCK' is stopped. As a result, the write address counter 20 stops counting up, and the data write operation of the memory 10 stops.

The write counter reset signal WCR generated from the write address counter 20 is applied to the next stage LSI connected in cascade.
By inputting the write reset signal WR to the circuit 2 and resetting the write address counter 20 and performing the same operation as above, 2M from the Mth of the input data DI
-Start the operation of writing to the memory 10 up to the first.

In this way, input data is sequentially stored in the built-in memories of the cascaded LSI circuits.

Next, in a read operation, the read address counter (RAC) 30 is reset via the flip-flop 70 by the read reset signal RR, and the read clock RC
Each time K manually inputs a count, the data from address 0 to address M-1 of the memory 10 is read out.

After receiving the read reset signal RR, the output control unit (QC) 4 sends an "H" level control signal CNT to the output buffer OB until the read address counter 30 reads the data at address M-1, and the output buffer OB is is opened and data Do is output to the outside of the LSI circuit. In addition, in FIG. 5, the output signal of the output control section 4 is
The reason why the count value is delayed by one clock is to match the delay in the data register 60.

When the read address counter 30 counts up to address M-2, it generates the read counter reset signal RCR as a carry signal (as explained in the case of FIG. 4, this reset is delayed by two clocks from the reset signal RR). This is because the counting operation of the address counter 30 is started by the read counter reset signal RCR.
When this is generated, the output control section 4 that receives this sets the output signal CNT to the "Lw" level, closes the output buffer OB, and stops outputting the data Do.
Now, after receiving the read counter reset signal RCR signal, as described above, the output signal C is delayed by two clocks.
Set NT to "L" level.

The read counter reset signal RCR is given as the read reset signal RR to the cascade-connected next-stage LSI circuit 2.
0 is reset and the data Do is reset by the same operation as above.
is read from address 0. At this time, the output control signal CNT of LSI circuit 1 is at the 1L" level, and the output control signal CNT of LSI circuit 2 is at the "H" level.
Only the data of I circuit 2 will be output to the outside.

〔Effect of the invention〕

As described above, according to the elastic store memory expansion circuit of the present invention, a plurality of LSI circuits are connected in cascade, and each LSI circuit is
The SI circuit resets the address counter using the write/read reset signal, then starts the write/read operation, and when the value of the address counter reaches the maximum, generates a counter reset signal and stops the write/read operation. At the same time, by using the counter reset signal as a write/read reset signal for the next stage, when writing, only one LSI circuit is written, and when reading, data is read from all LSI circuits, but data is output from only one LSI circuit. Since each LSI
A circuit that generates a write/read enable signal and a write/read reset signal as a chip select signal for the circuit becomes unnecessary, and the device can be made smaller and lower in cost.

[Brief explanation of the drawing]

FIG. 1 is a principle diagram showing an elastic store memory expansion circuit according to the present invention, and FIG. 2 is a block diagram showing an embodiment of a write address generation section used in each LSI circuit of the elastic store memory expansion circuit according to the present invention. 3 is a block diagram showing an embodiment of the read address generator used in each LSI circuit of the elastic store memory expansion circuit according to the present invention, and FIG. 4 is a time diagram showing the write operation of the embodiment of the present invention. Chart diagram, FIG. 5 is a time chart diagram showing the read operation of the embodiment of the present invention, FIG. 6 is a block diagram showing a general elastic store memory circuit, and FIG. 7 is a conventional elastic store memory expansion circuit. Figure 8 is a time chart of external signals used in the conventional example.
It is. In Figure 1, 1.2...LSI circuit, M1, M2...memory, WAG...write address generation section, RAG...read address generation section, WAC...write address counter, RAC...read address counter, OB...output buffer, OC ...Output control unit, WR...Write reset signal, RR...Read reset signal, WCR...Write counter reset signal, RCR...Read counter reset signal, WA...Write address, RA...Read address. In the figures, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Claims] Each input data line and each output data line are commonly connected, each has a built-in memory (M1, M2...), and the built-in memory (M1, M2...) is connected to a write address counter (W
A plurality of LSI circuits (1, 1,
In an elastic store memory expansion circuit that expands memory capacity using 2...), each LSI circuit resets its write address counter (WAC) using a write reset signal (WR) and then resets the write address (WAC) of the built-in memory. ) and generates a write counter reset signal (WCR) when the value of the write address counter (WAC) reaches a maximum, thereby stopping the write address increment of the write address counter (WAC). (WAG) and a read reset signal (RR) to reset the read address counter (RAC), and then reset the read address (RAC) of the built-in memory.
) and the read address counter (RA
When the value of C) reaches the maximum, a read counter reset signal (RCR) is generated and the read counter reset signal (
RCR) and the read reset signal (RR), the output control unit (OC) controls the output buffer (OB) to control the output of data read from the built-in memory. The write counter reset signal (WCR) and the read counter reset signal (RCR) are transmitted to the next stage LSI.
An elastic store memory expansion circuit characterized in that each LSI circuit is connected in cascade so as to provide a write reset signal (WR) and a read reset signal (RR) of the circuit.