JPH0129071B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a protection circuit against pulsed high voltage applied to external connection terminals of a semiconductor circuit such as a semiconductor integrated circuit.

FIG. 1 is a circuit diagram showing a conventional input protection circuit and its test circuit, in which A shows the semiconductor circuit to be protected, B the input protection circuit, and C its test circuit. 1 is input
MOS transistor (MOST), 2 is the input terminal connected to its gate, 3 is input terminal 2 and input
A series resistor connected between the gate of MOST1,
4 is a high threshold MOST whose gate is connected to input terminal 1, and whose source and drain are connected between the gate of input MOST 1 and the ground point; 5 is a high voltage power supply; 6 is a capacitor for generating high static voltage; 7 is a changeover switch.

In the test circuit C, the capacitor 6 is charged to a high voltage by closing the changeover switch 7 to the a side, and then when the changeover switch 7 is turned to the b side, a high static voltage is applied to the input terminal 2. In input protection circuit B, when the input voltage exceeds the threshold of MOST4, MOST4 becomes conductive, the charge stored in capacitor 6 is discharged through resistor 3 and MOST4, and the voltage at input terminal 2 decays over time. . On the other hand, the gate voltage of input MOST1 is
Even when MOST4 becomes conductive, it is not equal to the voltage at input terminal 2, and increases due to the time constant of the gate capacitance of input MOST1 and resistor 3, and the input voltage is divided by the ratio of MOST4's off resistance and resistor 3. When MOST4 begins to conduct as it approaches this value, it will attenuate accordingly. Therefore, if the circuit constants are appropriately selected, damage to the input MOST can be prevented. Figure 2 is a waveform diagram showing the time change of the voltage at each part of this circuit, where A is the voltage waveform at input terminal 2, and B is the input terminal.
This is the gate voltage waveform of MOST1.

In this conventional input protection circuit, a series resistor 3 is provided so that the high threshold MOST 4 becomes conductive before the voltage applied to the input terminal 2 is sufficiently transmitted to the input MOST 1 of the protected semiconductor circuit due to a time delay; The key point is that after MOST4 becomes conductive, the voltage applied to input MOST1 becomes a value obtained by dividing the voltage at input terminal 2 by the series resistor 3 and the conductance of MOST4. Therefore,
Series resistor 3 is essential. Therefore, as shown in FIG. 3, when the circuit to be protected is a circuit that emphasizes the analog value of the input voltage, the above-mentioned input protection circuit B is inappropriate. In the figure, 8, 9, and 10 are input voltage dividing resistors, and 11 is an analog summing amplifier. In this circuit, in order to make the voltage drop across resistor 3 negligible during normal operation, the value of resistor 3 must be extremely small, and on top of that, a high threshold must be set to achieve the function of the input protection circuit. It was necessary to use an extremely large capacitance for the field transistor 4.

The present invention has been made in view of the above points, and an object of the present invention is to provide a protection circuit that does not use a series resistor.

FIG. 4 is a circuit diagram showing an embodiment of this invention.
Portions equivalent to those of the conventional example are indicated by the same reference numerals. In the figure, 13 is a capacitor 12 whose one end is connected to the input terminal 2 and the other end is grounded via a high resistance 14.
The drain is input terminal 2 and the gate is capacitor 1
3 and high resistance 14, and the source is grounded, which is a normal threshold voltage MOST. FIG. 5 is a cross-sectional view showing the structure of a MOST suitable for use in this embodiment circuit, in which 21 is a silicon substrate, 22 is a source diffusion region, 23 is a drain diffusion region, 24 is a gate oxide film, and 25 is a field oxide film. The membrane 26 is a gate electrode, as shown in the figure.
The overlap between the gate electrode 26 and the drain diffusion region 23 is increased, and the capacitance of this portion is integrated into the capacitor 13 shown in FIG. 4.

In this embodiment circuit, when a high voltage is applied to the input terminal 2, the gate voltage of the MOST 12 instantly increases via the capacitor 13. Since the MOST 12 does not have a high threshold as in conventional circuits, its conductance is large and a sufficient current flows, and the voltage at the input terminal 2 is rapidly attenuated to protect the protected semiconductor circuit A. If the input surge voltage is too high, the gate voltage of MOST12 will change to capacitor 1.
3. Return to zero voltage with the time constant of resistor 14, MOST
12 is cut off, and the protected semiconductor circuit A operates normally. FIG. 6 is a waveform diagram showing the time change of the operating voltage of this embodiment circuit, where A is the voltage at the input terminal 2, and B is the gate voltage waveform of the MOST 12.

The main points of this embodiment are the capacitor 13 and the resistor 14.
It is necessary to select an appropriate time constant for this. If this time constant is too large, the time when high voltage is applied to the gate of MOST12 will be longer, and MOST12 will be destroyed.
Loss of input protection function. Conversely, if the time constant is too small, the conduction period of the MOST 12 will be short and the voltage at the input terminal 2 will not be sufficiently attenuated, resulting in destruction of the protected semiconductor circuit.

In the above embodiments, the case where it is used as an input protection circuit has been shown, but if it is used in an output circuit, a protection function against surge voltage entering from the output terminal can be achieved. Moreover, since there is no series resistance, the output characteristics will not be deteriorated.

As explained above, the protection circuit according to the present invention does not use a series resistor, so even if it is used as an external connection terminal for sending and receiving analog signal values, signal attenuation does not occur, and the chip size can be significantly increased. The protection function can be achieved without any damage.

[Brief explanation of drawings]

Figure 1 is a circuit diagram showing a conventional input protection circuit and its test circuit, Figure 2 is a waveform diagram showing time changes in voltage at each part of this circuit, and Figure 3 explains the shortcomings of the conventional input protection circuit. 4 is a circuit diagram showing one embodiment of the present invention, FIG. 5 is a sectional view showing the structure of a MOST suitable for use in the protection circuit of this invention, and FIG. 6 is a circuit diagram showing the above embodiment. FIG. 3 is a waveform diagram showing temporal changes in the operating voltage of the circuit. In the figure, A is the protected semiconductor circuit, B is the input protection circuit, 2 is the input terminal, 12 is MOST, 13
14 is a capacitor, 14 is a resistor, 23 is a drain diffusion region, 24 is a gate oxide film, and 26 is a gate electrode. Note that the same reference numerals in the figures indicate the same or corresponding parts.

Claims (1)

[Claims] 1. A gate-insulated transistor with a large current capacity is connected in parallel between an external connection terminal of a semiconductor circuit to be protected and a ground point, and the gate electrode of the transistor is connected to the external connection terminal and the By connecting a capacitor and a resistor to the ground point, and setting the time constant of the capacitor and the resistor to a desired value, the semiconductor A protection circuit for a semiconductor circuit, characterized in that the circuit is protected. 2. Claims characterized in that the drain diffusion region of a gate insulated transistor faces the gate electrode over a wide area via a gate oxide film, and the capacitance formed in this facing part is used as a capacitor. A protection circuit for a semiconductor circuit according to item 1.