JPH01289919A - Manufacture of display device - Google Patents

Manufacture of display device

Info

Publication number
JPH01289919A
JPH01289919A JP63120932A JP12093288A JPH01289919A JP H01289919 A JPH01289919 A JP H01289919A JP 63120932 A JP63120932 A JP 63120932A JP 12093288 A JP12093288 A JP 12093288A JP H01289919 A JPH01289919 A JP H01289919A
Authority
JP
Japan
Prior art keywords
gate
wiring
electrode
terminals
electrodes
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP63120932A
Other languages
Japanese (ja)
Other versions
JP2605346B2 (en
Inventor
Hirokazu Sakamoto
阪本 弘和
Yasuo Kawashima
康夫 河嶋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP12093288A priority Critical patent/JP2605346B2/en
Publication of JPH01289919A publication Critical patent/JPH01289919A/en
Application granted granted Critical
Publication of JP2605346B2 publication Critical patent/JP2605346B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Abstract

PURPOSE:To decrease working stages by forming picture electrodes, electrodes, and a short ring which connects source terminals, and gate terminals and the source terminals, and feeding electricity to the short ring and plating the gate electrodes, gate terminals, and source terminals. CONSTITUTION:The picture element electrodes 2, linear gate electrodes and their wiring 3, gate elements 8, and short ring 10 which short-circuits the source terminals 9, and gate terminals 8 and source terminals 9 outside them are formed. Then plating films 11 of metal such as Ni and Cr are deposited by electroplating on the gate electrodes and their wiring 3, gate terminals 8, source terminals 9, and short ring 10. At this time, the picture element electrodes 2 are not electrically conductive, so no plating film is deposited. Consequently, pattern working stages are less in frequency than those of a conventional method by one and cost reduction and high yield are realized.

Description

【発明の詳細な説明】 〔産業上の利用分舒〕 この発明は、液晶等のマトリクス形表示装置の製造方法
に関するものである。
DETAILED DESCRIPTION OF THE INVENTION [Industrial Application] The present invention relates to a method of manufacturing a matrix type display device such as a liquid crystal display device.

〔従来の技術〕[Conventional technology]

この種のマトリクス形表示装置は、通常2枚の対向基板
の間に液晶等の表示材料が挾持され、この表示材料に電
圧を印加する方法で構成される。
This type of matrix type display device is usually constructed by a method in which a display material such as a liquid crystal is sandwiched between two opposing substrates, and a voltage is applied to the display material.

この際少くとも一方の基板にマトリクス状に配列した画
素電極を設け、これらの画素を選択的に動作するために
、各画素毎にTPT等の非線形特性を有する能動素子を
設けている。
At this time, pixel electrodes arranged in a matrix are provided on at least one of the substrates, and in order to selectively operate these pixels, an active element having nonlinear characteristics such as TPT is provided for each pixel.

従来、この種の表示装置としては例えば特開昭61−2
48564号公報に開示されているものがあり、第4図
〜第6図にその構造を示す。第4図は従来のマトリクス
形表示装置の製造方法により形成したTFTアレイ基板
の全体を示す平面図、第5図はその一画素の平面図、そ
して第6図は第5図のII−II線断面図である。各図
において、1は透明絶縁基板、2はこの基板1上の画素
電極、3ば同じく基板1上に設けたゲート電極とその配
線、4はゲート電極3上のゲート絶縁膜、5はこの絶縁
膜4上に形成した半導体膜、6および7は半導体膜5に
接続したソース電極とその配線およびドレイン電極であ
る。8はゲート端子、9はソース端子である。
Conventionally, as this type of display device, for example, Japanese Patent Application Laid-Open No. 61-2
There is one disclosed in Japanese Patent No. 48564, and its structure is shown in FIGS. 4 to 6. FIG. 4 is a plan view showing the entire TFT array substrate formed by the conventional manufacturing method of a matrix type display device, FIG. 5 is a plan view of one pixel, and FIG. 6 is a line II-II line in FIG. 5. FIG. In each figure, 1 is a transparent insulating substrate, 2 is a pixel electrode on this substrate 1, 3 is a gate electrode and its wiring provided on the substrate 1, 4 is a gate insulating film on the gate electrode 3, and 5 is this insulating film. The semiconductor films 6 and 7 formed on the film 4 are a source electrode connected to the semiconductor film 5, its wiring, and a drain electrode. 8 is a gate terminal, and 9 is a source terminal.

上記のように構成した表示装置は全体として複数のゲー
ト配線3が並設されており、このゲート配#I3に交叉
して複数のソース配@6が並設され、そしてゲートおよ
びソース配線3,6の交叉部に設けられたドレイン電極
7、ゲート絶縁膜4、半導体膜5およびゲート電極3と
ソース電極6とで非線形特性を有するTPTを構成し、
この能動素子と画素電極2とでTFTアレイ基板を構成
している。このTFTアレイ基板に対向して、かつ表面
に透明電極等を有する対向電極基板(図示せず)が設け
られ、TPTプレイ基板と対向電極基板の間に液晶等の
表示材料が挾持されてマトリクス形表示装置を構成する
In the display device configured as described above, a plurality of gate wirings 3 are arranged in parallel as a whole, and a plurality of source wirings @6 are arranged in parallel across the gate wiring #I3, and the gate and source wirings 3, The drain electrode 7, the gate insulating film 4, the semiconductor film 5, and the gate electrode 3 and the source electrode 6 provided at the intersection of the gate electrodes 6 constitute a TPT having nonlinear characteristics,
This active element and the pixel electrode 2 constitute a TFT array substrate. A counter electrode substrate (not shown) having a transparent electrode etc. on the surface is provided opposite to this TFT array substrate, and a display material such as liquid crystal is sandwiched between the TPT play substrate and the counter electrode substrate to form a matrix shape. Configure the display device.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

しかしながら、TFTアレイ基板を製造する場合、少な
くとも5回のパターン加工工程が必要であり、その都度
パターニング不良による欠陥あるいは工程を経るごとに
基板に付着する異物による欠陥が発生し、これによって
製品歩留りの低下を招き、また工程数が多いことによる
高コスト化がまぬがれない。さらに、ゲート端子8、ソ
ース端子9はそれぞれゲート電極とその配線3およびソ
ース電極とその配#!6と同時にAIやCrの材料で形
成されているため、端子と外部回路を接続する際、信頼
性の高い半田を使用できないといった問題があった。
However, when manufacturing a TFT array substrate, at least five pattern processing steps are required, and each time defects occur due to poor patterning or defects due to foreign matter adhering to the substrate after each step, which reduces product yield. In addition, high costs due to the large number of steps are unavoidable. Further, the gate terminal 8 and the source terminal 9 are respectively connected to a gate electrode and its wiring 3 and a source electrode and its wiring! At the same time as No. 6, since the terminals are made of materials such as AI and Cr, there is a problem in that highly reliable solder cannot be used when connecting the terminals to external circuits.

この発明は上記の様な従来の課題を解消するためになさ
れたもので、少くともパターン加工工程を1つ少くして
製造できるマトリクス形の表示装置の製造方法を得るこ
とを目的とする。
The present invention has been made to solve the above-mentioned conventional problems, and an object of the present invention is to provide a method for manufacturing a matrix type display device that can be manufactured by reducing at least one pattern processing step.

〔課題を解決するための手段〕[Means to solve the problem]

この発明に係る表示装置の製造方法は、マトリクス形の
表示装置において、画素電極、ゲート電極とその、ソー
ス端子およびゲート端子とソース=3− 端子を接続するショートリングを形成し、ショートリン
グに通電してゲート電極やゲート端子およびソース端子
に金属メッキを施こすものである。
A method for manufacturing a display device according to the present invention includes forming a short ring connecting a pixel electrode, a gate electrode, a source terminal, and a source=3− terminal to each other in a matrix display device, and energizing the short ring. Then, metal plating is applied to the gate electrode, gate terminal, and source terminal.

〔作 用〕[For production]

この発明においては、ゲート電極とその配線、ゲート端
子およびソース端子はITOとその上にメッキ析出され
た金属とからなるので、従来の製造方法よりパターン加
工工程が1回生なくできる。
In the present invention, since the gate electrode, its wiring, gate terminal, and source terminal are made of ITO and metal plated thereon, the patterning process can be repeated less than once compared to conventional manufacturing methods.

〔実施例〕〔Example〕

以下、この発明の一実施例を図について説明する。第1
図はこの発明の製造方法によって製作したマトリクス形
表示装置のTFTアレイ基板の全体の平面図、第2図は
その一画素の拡大平面図、第3図は第2図のI−N線断
面図であって、11はゲート電極およびその配線3の表
面を被覆した金属のメッキ膜で、その他の符号は従来例
の場合と全て同一であるので同一符号を付して説明は省
略する。
An embodiment of the present invention will be described below with reference to the drawings. 1st
The figure is a plan view of the entire TFT array substrate of a matrix display device manufactured by the manufacturing method of the present invention, FIG. 2 is an enlarged plan view of one pixel, and FIG. 3 is a sectional view taken along the line I-N in FIG. Reference numeral 11 denotes a metal plating film that coats the surface of the gate electrode and its wiring 3, and all other symbols are the same as in the conventional example, so the same symbols will be given and explanations will be omitted.

次に上記したTFTアレイ基板の製造方法について説明
する。
Next, a method for manufacturing the above-described TFT array substrate will be explained.

まずガラス等の透明絶縁基板l上に、ITO(Incl
ium Tin 0xide)等の透明導電膜を、EB
魚着法等で堆積する。次にホトエツチング法等の方法で
、画素電極15とライン状のゲート電極とその配線3ゲ
ート端子8、ソース端子9及びゲート端子8とソース端
子9をその外側で電気的に短絡させるショートリング1
0を形成する。次に電気メッキ法により、ゲート電極と
その配線3、ゲート端子8、ソース端子9、ショートリ
ング10にNi、Cr等の金属のメッキ膜11を析出さ
せる。このとき画素電極2は、電気的に導電がないので
、メッキ膜は、析出しない。
First, ITO (Incl.
Transparent conductive film such as ium Tin Oxide) is
It is deposited using the fish deposition method, etc. Next, using a method such as photo-etching, a short ring 1 is formed to electrically short-circuit the pixel electrode 15, the linear gate electrode, its wiring 3, gate terminal 8, source terminal 9, and gate terminal 8 and source terminal 9 on the outside thereof.
form 0. Next, a plating film 11 of a metal such as Ni or Cr is deposited on the gate electrode, its wiring 3, gate terminal 8, source terminal 9, and short ring 10 by electroplating. At this time, since the pixel electrode 2 is not electrically conductive, no plating film is deposited.

次にゲート絶縁膜4となるS:N又はS:C2等、及び
半導体膜5となる水素化アモルファス・シリコン゛(a
−8i:H)等を連続してCVD法等により堆積する。
Next, S:N or S:C2, etc., which will become the gate insulating film 4, and hydrogenated amorphous silicon (a
-8i:H) etc. are successively deposited by CVD method or the like.

次いで順次半導体膜5をアイランド状に形成し、ゲート
絶縁膜4を少くとも画素電極2とドレイン電極7が接続
され、さらにソース端子9とソース配線6が接続される
様にパターン形成を行う。次にAj、Cr等の金属を堆
積し、ソース電極とその配線6及びドレイン電i7を形
成する。
Next, the semiconductor film 5 is sequentially formed into an island shape, and the gate insulating film 4 is patterned so that at least the pixel electrode 2 and the drain electrode 7 are connected, and further, the source terminal 9 and the source wiring 6 are connected. Next, metals such as Aj and Cr are deposited to form a source electrode, its wiring 6, and a drain electrode i7.

これでTFTアレイ基板が完成する。This completes the TFT array substrate.

この様にして形成されたTFTアレイ基板と、透明導電
電極及びカラーフィルタ等を有する対向電極基板との間
に、液晶等の表示材料が挾持され、マトリクス形表示装
置が製造される。
A display material such as a liquid crystal is sandwiched between the thus formed TFT array substrate and a counter electrode substrate having transparent conductive electrodes, color filters, etc., thereby manufacturing a matrix type display device.

〔発明の効果〕〔Effect of the invention〕

以上説明したようにこの発明によれば、画素電極、ゲー
ト電極とその配線、ゲート端子、ソース端子およびゲー
ト端子とソース端子を電気的に接続するショートリング
を形成し、これに通電してゲート電極とその配線、デー
1一端子およびソース端子に金属メッキを施こしたので
、ゲート電極とその配線、ゲート端子及びソース端子は
ITOとその上にメッキ析出された金属とからなり、従
来の方法よりパターン加工工程が1回生く低コスト化及
び高歩留化が期待できる。またゲート電極とその配線は
従来スパッタ法等で成膜するため高価な装置が必要であ
ったがこの発明ではメッキ法であるので高価な装置は不
要で安価となる。さらにメッキする金属をNiに選べば
、端子と外部回路との接続に、ばんだづけが使用でき、
安価で信頼性が高くなることが期待てきる。
As explained above, according to the present invention, a pixel electrode, a gate electrode and its wiring, a gate terminal, a source terminal, and a short ring that electrically connects the gate terminal and the source terminal are formed, and a current is applied to the short ring to connect the gate electrode to the gate electrode. Since the gate electrode and its wiring, the data terminal and the source terminal are plated with metal, the gate electrode, its wiring, the gate terminal and the source terminal are made of ITO and the metal plated on it, which is easier than the conventional method. Since the pattern processing process is repeated once, lower costs and higher yields can be expected. Further, the gate electrode and its wiring were conventionally formed by sputtering or the like, which required expensive equipment, but in this invention, plating is used, so expensive equipment is unnecessary and the cost is reduced. Furthermore, if you choose Ni as the metal to be plated, you can use soldering to connect the terminals to external circuits.
It is expected that it will be cheaper and more reliable.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はこの発明の一実施例による7トリクス、形の表
示装置の製造方法によって製造されたTFTアレイ基板
の全体を示す平面図、第2図はその一画素の拡大平面図
、第3図は第2図の■−■線断面図、第4図は従来のマ
トリクス形表示装置の製造方法によって製造されたTF
Tアレイ基板の全体を示す平面図、第5図はその一画素
の拡大平面図、第6図は第5図の■−■断面図である。 1は透明絶縁基板、2は画素電極、3はゲート電極とそ
の配線、4はゲート絶縁膜、5は半導体膜、6はソース
電極とその配線、7はドレイン電極、8はゲート端子、
9はソース端子、10はショートリング、11は金属メ
ッキ膜。 なお図中、同一符号は同−又は相当部分を示す。
FIG. 1 is a plan view showing the entire TFT array substrate manufactured by a method for manufacturing a 7-trix display device according to an embodiment of the present invention, FIG. 2 is an enlarged plan view of one pixel, and FIG. 3 is a sectional view taken along the line ■-■ in Fig. 2, and Fig. 4 is a TF manufactured by the conventional method for manufacturing a matrix type display device.
FIG. 5 is an enlarged plan view of one pixel of the T-array substrate, and FIG. 6 is a sectional view taken along the line 1--2 of FIG. 1 is a transparent insulating substrate, 2 is a pixel electrode, 3 is a gate electrode and its wiring, 4 is a gate insulating film, 5 is a semiconductor film, 6 is a source electrode and its wiring, 7 is a drain electrode, 8 is a gate terminal,
9 is a source terminal, 10 is a short ring, and 11 is a metal plating film. In the drawings, the same reference numerals indicate the same or equivalent parts.

Claims (1)

【特許請求の範囲】[Claims] 透明絶縁基板上に並設された複数のゲート電極とその配
線、この電極配線に交叉する複数のソース電極とその配
線および両電極配線の交叉部に設けられた非線形特性を
有する能動素子と表示電極を有する薄膜トランジスタ(
TFT)アレイ基板、このアレイ基板に対向しかつ、表
面に透明導電膜を有する対向電極基板並びに該対向電極
基板と上記アレイ基板の間に挾持される液晶等の表示材
料を備えたマトリクス形表示装置において、画素電極、
ゲート電極とその配線、ゲート端子、ソース端子および
全てのゲート端子とソース端子を電気的に接続するショ
ートリングを形成し、次にショートリングに通電するこ
とによりゲート電極とその配線、ゲート端子およびソー
ス端子に金属をメッキすることにより形成したことを特
徴とする表示装置の製造方法。
A plurality of gate electrodes and their wiring arranged in parallel on a transparent insulating substrate, a plurality of source electrodes and their wiring that intersect with the electrode wiring, and an active element with nonlinear characteristics and a display electrode provided at the intersection of both electrode wirings. Thin film transistor (
TFT) array substrate, a counter electrode substrate facing the array substrate and having a transparent conductive film on its surface, and a display material such as a liquid crystal sandwiched between the counter electrode substrate and the array substrate. In the pixel electrode,
Form a short ring that electrically connects the gate electrode, its wiring, the gate terminal, the source terminal, and all gate terminals and source terminals, and then energizes the short ring to connect the gate electrode, its wiring, the gate terminal, and the source. A method for manufacturing a display device, characterized in that the terminal is formed by plating metal.
JP12093288A 1988-05-17 1988-05-17 Display device manufacturing method Expired - Lifetime JP2605346B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12093288A JP2605346B2 (en) 1988-05-17 1988-05-17 Display device manufacturing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12093288A JP2605346B2 (en) 1988-05-17 1988-05-17 Display device manufacturing method

Publications (2)

Publication Number Publication Date
JPH01289919A true JPH01289919A (en) 1989-11-21
JP2605346B2 JP2605346B2 (en) 1997-04-30

Family

ID=14798542

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12093288A Expired - Lifetime JP2605346B2 (en) 1988-05-17 1988-05-17 Display device manufacturing method

Country Status (1)

Country Link
JP (1) JP2605346B2 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002182237A (en) * 2000-12-11 2002-06-26 Semiconductor Energy Lab Co Ltd Semiconductor device and its manufacturing method
US9059216B2 (en) 2000-12-11 2015-06-16 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device, and manufacturing method thereof
US9231044B2 (en) 2000-12-21 2016-01-05 Semiconductor Energy Laboratory Co., Ltd. Light emitting device and method of manufacturing the same

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60209780A (en) * 1984-04-04 1985-10-22 セイコーエプソン株式会社 Manufacture of liquid crystal display body

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60209780A (en) * 1984-04-04 1985-10-22 セイコーエプソン株式会社 Manufacture of liquid crystal display body

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002182237A (en) * 2000-12-11 2002-06-26 Semiconductor Energy Lab Co Ltd Semiconductor device and its manufacturing method
US9059216B2 (en) 2000-12-11 2015-06-16 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device, and manufacturing method thereof
US9666601B2 (en) 2000-12-11 2017-05-30 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device, and manufacturing method thereof
US10665610B2 (en) 2000-12-11 2020-05-26 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device, and manufacturing method thereof
US9231044B2 (en) 2000-12-21 2016-01-05 Semiconductor Energy Laboratory Co., Ltd. Light emitting device and method of manufacturing the same
US9793335B2 (en) 2000-12-21 2017-10-17 Semiconductor Energy Laboratory Co., Ltd. Light emitting device and method of manufacturing the same

Also Published As

Publication number Publication date
JP2605346B2 (en) 1997-04-30

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