JPH01286348A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH01286348A JPH01286348A JP63117716A JP11771688A JPH01286348A JP H01286348 A JPH01286348 A JP H01286348A JP 63117716 A JP63117716 A JP 63117716A JP 11771688 A JP11771688 A JP 11771688A JP H01286348 A JPH01286348 A JP H01286348A
- Authority
- JP
- Japan
- Prior art keywords
- insulating substrate
- heat sink
- plate
- heat radiation
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims description 30
- 239000000758 substrate Substances 0.000 claims abstract description 36
- 239000002184 metal Substances 0.000 claims description 30
- 229910052751 metal Inorganic materials 0.000 claims description 30
- 238000001816 cooling Methods 0.000 abstract description 10
- 239000000919 ceramic Substances 0.000 abstract description 7
- 229910045601 alloy Inorganic materials 0.000 abstract description 4
- 239000000956 alloy Substances 0.000 abstract description 4
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 abstract description 4
- 229910052759 nickel Inorganic materials 0.000 abstract description 2
- 230000005855 radiation Effects 0.000 abstract 7
- 238000005452 bending Methods 0.000 abstract 1
- 239000000463 material Substances 0.000 description 8
- 229910000679 solder Inorganic materials 0.000 description 7
- 230000017525 heat dissipation Effects 0.000 description 5
- 238000000034 method Methods 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 239000010949 copper Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 229910000831 Steel Inorganic materials 0.000 description 2
- 238000005219 brazing Methods 0.000 description 2
- 239000010959 steel Substances 0.000 description 2
- 238000005253 cladding Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 230000001052 transient effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
- H01L2924/3511—Warping
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0201—Thermal arrangements, e.g. for cooling, heating or preventing overheating
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/05—Insulated conductive substrates, e.g. insulated metal substrate
Abstract
Description
【発明の詳細な説明】
［産業上の利用分野］
この発明は半導体装置に関するものであり、特に、放熱
板と半導体装置の外部電極とが絶縁基板により絶縁され
たモジュール構造の半導体装置に関するものである。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor device, and particularly relates to a semiconductor device having a module structure in which a heat sink and an external electrode of the semiconductor device are insulated by an insulating substrate. be.
［従来の技術］
第４図は従来のモジュール構造半導体装置の断面図であ
る。図中、１は放熱板である。放熱板１には、熱放散性
の良好な鋼材が用いられている。[Prior Art] FIG. 4 is a sectional view of a conventional module structure semiconductor device. In the figure, 1 is a heat sink. The heat sink 1 is made of steel with good heat dissipation properties.
放熱板１の上面に、半田２を介して、絶縁基数３が接着
されている。絶縁基板３の材質は、たとえばセラミック
スである。この絶縁基板３の上には、所定のパターン形
状を有する金属パターン４が設けられている。金属パタ
ーン４の所定の位置には、たとえば半導体素子５または
外部電極端子６が半田等の鑞材にて接着されており、放
熱板１とは絶縁された状態で、所望の電気回路が構成さ
れている。なお、ここでは図示していないが、電気回路
を構成するために、半導体素子５の電極と外部電極６と
は、Ａ１線等の金属細線で接続されている。An insulating base 3 is bonded to the upper surface of the heat sink 1 via solder 2. The material of the insulating substrate 3 is, for example, ceramics. On this insulating substrate 3, a metal pattern 4 having a predetermined pattern shape is provided. For example, a semiconductor element 5 or an external electrode terminal 6 is bonded to a predetermined position of the metal pattern 4 with a brazing material such as solder, and a desired electric circuit is configured while being insulated from the heat sink 1. ing. Although not shown here, in order to configure an electric circuit, the electrodes of the semiconductor element 5 and the external electrodes 6 are connected with a thin metal wire such as an A1 wire.
［発明が解決しようとする課題］
従来のモジュール構造半導体装置は以上のように構成さ
れている。しかしながら、放熱板１の材質である銅と絶
縁基板３の材質であるセラミックスとの熱膨張係数が違
う（銅が１６．７Ｘ１０−６１／’Ｃ，セラミックスが
７ｘｌＯ−’ １／’Ｃ）。[Problems to be Solved by the Invention] A conventional module structure semiconductor device is configured as described above. However, the thermal expansion coefficients of copper, which is the material of the heat sink 1, and the ceramic, which is the material of the insulating substrate 3, are different (16.7×10-61/'C for copper and 7×10-'1/'C for ceramics).
そのため、第４図を参照して、半ＩＩＪ ２により、放
熱板１と絶縁基板３とを接管した後、冷却して常温に戻
すと、絶縁基板３の熱膨張係数が小さいことより、放熱
板１が絶縁基＆Ｅ３側に向けて凸に撓むという現象が起
こる。放熱板１がこのように絶縁基板３側に撓むと、該
半導体装置は、冷却板（図示せず）に取付けられる際に
、隙間Ｃが生じた状態で取付けられることになる。その
結果、半導体装置の接触熱抵抗が増大するという問題点
が生じていた。Therefore, referring to FIG. 4, when the heat sink 1 and the insulating substrate 3 are connected together using the semi-IIJ 2 and then cooled to room temperature, the heat sink A phenomenon occurs in which 1 bends convexly toward the insulating base &E3 side. If the heat sink 1 is bent toward the insulating substrate 3 in this way, the semiconductor device will be attached with a gap C when it is attached to a cooling plate (not shown). As a result, a problem has arisen in that the contact thermal resistance of the semiconductor device increases.
この発明は上記のような問題点を解決するためなされた
もので、放熱板の撓みを極力小さく抑え、当該半導体装
置を冷却仮に取付けた際の接触熱抵抗を極めて小さく抑
えることのできる、半導体装置を提供することを目的と
する。This invention was made in order to solve the above-mentioned problems, and provides a semiconductor device in which the deflection of the heat sink can be minimized and the contact thermal resistance when the semiconductor device is temporarily mounted for cooling can be minimized. The purpose is to provide
［課題を解決するための手段］
この発明は、放熱板と、該放熱板の一方の面に設けられ
た絶縁基板と、を備えた半導体装置に係るものである。[Means for Solving the Problems] The present invention relates to a semiconductor device including a heat sink and an insulating substrate provided on one surface of the heat sink.
そして、前記問題点を解決するために、放熱板の他方の
面に、上記絶縁基板とほぼ同一の熱膨張係数を有する金
属板を設けたことを特徴とする。In order to solve the above-mentioned problem, a metal plate having substantially the same coefficient of thermal expansion as the insulating substrate is provided on the other surface of the heat sink.
［作用］
この発明に係る半導体装置では、絶縁基板と、該絶縁基
板とほぼ同一の熱膨張係数を有する金属板との間に、放
熱板が挾み込まれるように設けられているので、絶縁基
数と放熱板との間に熱膨張係数の差があったとしても、
原理的に、放熱板の撓みは生じなくなる。それゆえ、当
該半導体装置の底面は、その平面性が良好に保たれる。[Function] In the semiconductor device according to the present invention, since the heat dissipation plate is interposed between the insulating substrate and the metal plate having almost the same coefficient of thermal expansion as the insulating substrate, the insulating Even if there is a difference in thermal expansion coefficient between the base and the heat sink,
In principle, the heat sink no longer bends. Therefore, the bottom surface of the semiconductor device maintains good flatness.
［実施例コ 以下、この発明の一実施例を図について説明する。[Example code] An embodiment of the present invention will be described below with reference to the drawings.
第１Ａ図はこの発明の一実施例に係る半導体装置の断面
図である。FIG. 1A is a sectional view of a semiconductor device according to an embodiment of the present invention.
図において、１は放熱板である。放熱板１には、熱放散
性の良好なたとえば鋼材が用いられる。放熱板１の上に
絶縁基板３が半田２等を介して接着されている。絶縁基
板３には、たとえばアルミナセラミックスが用いられる
。この絶縁基板３の上面には、所定の形状にパターニン
グされた金属パターン４が設けられている。金属パター
ン４の所定の位置には、たとえば半導体索子５または外
部電極端子６が半田等の鑞材にて接着されており、放熱
板１とは絶縁された状態で、所望の電気回路が構成され
ている。放熱板１の裏面には、上記絶縁基板３とほぼ同
一の熱膨張係数を有する金属板たとえば４２アロイ（Ｆ
ｅ５８％、Ｎｉ４２％）が張りつけられて設けられてい
る。この金属板７は、第１Ａ図を参照して、絶縁基板３
とほぼ同じ厚みで設けられている。第１Ｂ図は当該半導
体装置の底面図である。図中、７は金属板である。金属
板７は放熱板１の裏面全体にわたって設けられている。In the figure, 1 is a heat sink. For the heat sink 1, a steel material having good heat dissipation properties is used, for example. An insulating substrate 3 is bonded onto the heat sink 1 via solder 2 or the like. For example, alumina ceramics is used for the insulating substrate 3. A metal pattern 4 patterned into a predetermined shape is provided on the upper surface of this insulating substrate 3. For example, a semiconductor cable 5 or an external electrode terminal 6 is bonded to a predetermined position of the metal pattern 4 with a brazing material such as solder, and is insulated from the heat sink 1 to form a desired electric circuit. has been done. A metal plate having almost the same coefficient of thermal expansion as the insulating substrate 3, for example, 42 alloy (F
58% e, 42% nickel) is attached. This metal plate 7 is made of an insulating substrate 3, as shown in FIG. 1A.
It is provided with approximately the same thickness. FIG. 1B is a bottom view of the semiconductor device. In the figure, 7 is a metal plate. The metal plate 7 is provided over the entire back surface of the heat sink 1.
図中、絶縁基板３を隠れ線で示し、絶縁基板３と金属板
７との位置関係を明確にしている。In the figure, the insulating substrate 3 is shown by hidden lines to clarify the positional relationship between the insulating substrate 3 and the metal plate 7.
第１Ａ図および第１Ｂ図より明らかなように、絶縁基板
３の占有面積より金属板７の占有面積が大きくなるよう
に、放熱板１の裏面に金属板７が設けられている。放熱
板１の裏面に金属板７を設ける方法は、たとえば圧延ク
ラッド技術で行なう方法でもよい。また、半田等の鑞材
て、絶縁基板３を放熱板１に接着する、と同時に、該放
熱板１に金属板７を接着してもよい。As is clear from FIGS. 1A and 1B, the metal plate 7 is provided on the back surface of the heat sink 1 so that the area occupied by the metal plate 7 is larger than the area occupied by the insulating substrate 3. The method of providing the metal plate 7 on the back surface of the heat sink 1 may be, for example, a method using a rolled cladding technique. Alternatively, the metal plate 7 may be bonded to the heat sink 1 at the same time as the insulating substrate 3 is bonded to the heat sink 1 using a solder material such as solder.
さて、絶縁基板３がアルミナセラミックスの場合、その
熱膨張係数は６．７Ｘ１０−６１／℃であり、４２アロ
イの熱膨張係数は４．２Ｘ１０−６１／℃であるので、
両者はほぼ等しい。しかし、厳密に言うと４２７０イの
熱膨張係数が絶縁基板３のそれよりも少し小さいので、
絶縁基板３を放熱板１に半田付けした後、冷却すると、
放熱板１が金属板７側に向けてわずかに凸に撓むだろう
。Now, if the insulating substrate 3 is made of alumina ceramics, its thermal expansion coefficient is 6.7X10-61/℃, and the thermal expansion coefficient of 42 alloy is 4.2X10-61/℃, so
Both are almost equal. However, strictly speaking, the thermal expansion coefficient of 4270i is slightly smaller than that of insulating substrate 3, so
After soldering the insulating board 3 to the heat sink 1, when it is cooled,
The heat sink 1 will be slightly bent toward the metal plate 7 side.
しかしながら、当該半導体装置を冷却板に取付けるにあ
たり、放熱板１の両側をねじで締め付けて固定するので
、放熱板１の撓みは冷却板の面に沿うように矯正される
。したがって、第４図に示すような絶縁基板３側に向け
て凸に撓んだ場合と異なり、隙間Ｃは発生しない。した
がって、冷却板と放熱板との間に生じる隙間に起因する
、接触熱抵抗は無視できる。However, when attaching the semiconductor device to the cooling plate, both sides of the heat sink 1 are tightened and fixed with screws, so that the deflection of the heat sink 1 is corrected so as to follow the surface of the cooling plate. Therefore, unlike the case where it is bent convexly toward the insulating substrate 3 side as shown in FIG. 4, a gap C is not generated. Therefore, the contact thermal resistance caused by the gap between the cooling plate and the heat sink can be ignored.
また、金属板７の厚みも絶縁基板３の厚み（通常は、０
．５〜０．６Ｂ５ｔの厚みが一般的である。）と同一に
しであるので、金属板７の熱伝導率が放熱板１に比べて
小さくても、定常熱抵抗にはほとんど影響を与えない。The thickness of the metal plate 7 is also the same as the thickness of the insulating substrate 3 (usually 0
．． A thickness of 5 to 0.6B5t is common. ), so even if the thermal conductivity of the metal plate 7 is lower than that of the heat sink 1, it has almost no effect on the steady-state thermal resistance.
なお、特に過渡的な熱抵抗を小さくする必要があるとき
には、第２図に示すように、金属板７の、半導体素子が
搭載されている位置に相当する部分に該半導体素子の６
何面積よりも大きい面積の切欠８を設け、この切欠８よ
り放熱板１を露出させるように構成し、てもよい。半導
体素子の直下に切欠８を設けるのは、半導体素子で消費
される電力により発生する熱はほとんどが半導体素子の
直下に放散され、面方向には拡散しないという理由によ
る。この場合、放熱板１の露出面を金属板７と而−にし
ておく方がより好ましい。これらを而−にすることは、
たとえば、次のようにして実現できる。すなイつち放熱
板１の裏面であって、金属板７の切欠８が対応する部分
に、切欠８に而−に１茨合し得る形状に選ばれた突出部
を、予め、コイニング加工により設けておくことで実現
できる。Note that when it is particularly necessary to reduce the transient thermal resistance, as shown in FIG.
It is also possible to provide a notch 8 with an area larger than the number of areas, and to expose the heat sink 1 through this notch 8. The reason why the notch 8 is provided directly under the semiconductor element is that most of the heat generated by the power consumed by the semiconductor element is dissipated directly under the semiconductor element and is not diffused in the plane direction. In this case, it is more preferable to keep the exposed surface of the heat sink 1 as the metal plate 7. To make these things,
For example, this can be accomplished as follows. In other words, on the back side of the heat dissipation plate 1, in the part corresponding to the notch 8 of the metal plate 7, a protrusion selected to have a shape that can fit into the notch 8 is pre-coined. This can be achieved by providing the following.
また、第３Ａ図および第３Ｂ図に示すように、放熱板１
の裏面にストライブ状に金属板７を設けてもよい。この
場合において、絶縁基板３の平面積より金属板７の平面
積が小さい場合は、金属板７の厚さを絶縁基板３よりも
厚くした方が、撓みのバランスがとりやすくなる。なお
、第３Ｂ図は、第３Ａ図におけるＢ−Ｂ線に沿う断面図
である。In addition, as shown in FIGS. 3A and 3B, the heat sink 1
A metal plate 7 may be provided in a striped manner on the back surface of the holder. In this case, if the planar area of the metal plate 7 is smaller than the planar area of the insulating substrate 3, it is easier to balance the deflection by making the metal plate 7 thicker than the insulating substrate 3. Note that FIG. 3B is a sectional view taken along line BB in FIG. 3A.
放熱板１の上に絶縁基板３が半田２を介して接着されて
いる。放熱板１の底面には、金属板７がストライブ状に
設けられている。そして、このストライブ状の金属板７
と放熱板１は而−となっている。面一にする方法は、上
述のとおりである。An insulating substrate 3 is bonded onto a heat sink 1 via solder 2. A metal plate 7 is provided in a stripe shape on the bottom surface of the heat sink 1. And this striped metal plate 7
And the heat sink 1 is -. The method for making it flush is as described above.
なお、上記実施例では、放熱板の材質を銅とし、絶縁基
板の材質をアルミナセラミックスにした場合を例示して
説明したが、この発明はこれに限られるものでなく、他
の材質を選んでも実施例と同様の効果を実現する。In the above embodiment, the heat dissipation plate is made of copper and the insulating substrate is made of alumina ceramics. However, the present invention is not limited to this, and other materials may be used. The same effect as the embodiment is achieved.
以上、具体的な実施例を挙げてこの発明の半導体装置に
ついて説明したが、本発明は、その精神または主要な特
徴から逸脱することなく、他の色々な形で実施すること
ができる。それゆえ、前述の実施例はあらゆる点で単な
る例示にすぎず、限定的に解釈してはならない。本発明
の範囲は、特許請求の範囲によって示すものであって、
明細古本文には何ら拘束されない。さらに、特許請求の
範囲の均等範囲に属する変形や変更は、すべて本発明の
範囲内のものである。Although the semiconductor device of the present invention has been described above with reference to specific embodiments, the present invention can be implemented in various other forms without departing from its spirit or main characteristics. Therefore, the above-described embodiments are merely illustrative in all respects and should not be construed as limiting. The scope of the invention is indicated by the claims,
There is no restriction on the original text of the specification. Furthermore, all modifications and changes that come within the scope of equivalents of the claims are intended to be within the scope of the present invention.
［発明の効果コ
本発明に係る半導体装置では、絶縁基板と、該絶縁、！
！仮とほぼ同一の熱膨張係数を何する金属板との間に、
放熱板が挾み込まれて設けられているので、絶縁基板と
放熱板との間に熱膨張係数の差があったとしても、原理
的に放熱板の撓みは生じなくなる。それゆえ、当該半導
体装置の底面はその平面性が良好に保たれる。それゆえ
、当該半導体装置を冷却板に取付けても、当該半導体装
置と冷却板との間に隙間は発生せず、接触熱抵抗を極め
て小さく抑えることができるという効果を奏する。[Effects of the Invention] The semiconductor device according to the present invention includes an insulating substrate, the insulating,!
! Between a metal plate and a metal plate that has almost the same coefficient of thermal expansion,
Since the heat sink is sandwiched between the heat sink and the heat sink, even if there is a difference in thermal expansion coefficient between the insulating substrate and the heat sink, the heat sink will not bend in principle. Therefore, the bottom surface of the semiconductor device maintains good flatness. Therefore, even when the semiconductor device is attached to the cooling plate, no gap is generated between the semiconductor device and the cooling plate, and it is possible to suppress the contact thermal resistance to an extremely low level.
第１Ａ図はこの発明の一実施例の正面断面図であり、第
１Ｂ図はその底面図である。第２図はこの発明の他の実
施例の底面図である。第３Ａ図はこの発明のさらに他の
実施例の底面図であり、第３Ｂ図は第３Ａ図におけるＢ
−Ｂ断面図である。
第４図は従来のモジュール構造半導体装置の正面断面図
である。
図において、１は放熱板、３は絶縁基板、７は金属板で
ある。
なお、各図中、同一符号は同一または相当部分を示す。FIG. 1A is a front sectional view of an embodiment of the present invention, and FIG. 1B is a bottom view thereof. FIG. 2 is a bottom view of another embodiment of the invention. FIG. 3A is a bottom view of still another embodiment of the present invention, and FIG. 3B is a bottom view of still another embodiment of the present invention.
-B sectional view. FIG. 4 is a front sectional view of a conventional module structure semiconductor device. In the figure, 1 is a heat sink, 3 is an insulating substrate, and 7 is a metal plate. In each figure, the same reference numerals indicate the same or corresponding parts.
Claims (1)
と、を備えた半導体装置において、 前記放熱板の他方の面に、前記絶縁基板とほぼ同一の熱
膨張係数を有する金属板を設けたことを特徴とする半導
体装置。[Scope of Claims] A semiconductor device comprising a heat sink and an insulating substrate provided on one surface of the heat sink, wherein the other surface of the heat sink has a thermal expansion layer approximately the same as that of the insulating substrate. A semiconductor device comprising a metal plate having a coefficient.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63117716A JPH0732219B2 (en) | 1988-05-12 | 1988-05-12 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63117716A JPH0732219B2 (en) | 1988-05-12 | 1988-05-12 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01286348A true JPH01286348A (en) | 1989-11-17 |
| JPH0732219B2 JPH0732219B2 (en) | 1995-04-10 |
Family
ID=14718527
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63117716A Expired - Lifetime JPH0732219B2 (en) | 1988-05-12 | 1988-05-12 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0732219B2 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5793106A (en) * | 1995-02-28 | 1998-08-11 | Hitachi, Ltd. | Semiconductor device |
| US6046498A (en) * | 1997-06-30 | 2000-04-04 | Nec Corporation | Device having a heat sink for cooling an integrated circuit |
| WO2005076675A1 (en) * | 2004-01-28 | 2005-08-18 | Infineon Technologies Ag | Method for bonding ceramic to copper, without creating a bow in the copper |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5844636A (en) * | 1981-09-09 | 1983-03-15 | 三菱電機株式会社 | Circuit breaker |
| JPS5849674A (en) * | 1981-09-18 | 1983-03-23 | 株式会社日立製作所 | Metal-ceramics unified part |
-
1988
- 1988-05-12 JP JP63117716A patent/JPH0732219B2/en not_active Expired - Lifetime
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5844636A (en) * | 1981-09-09 | 1983-03-15 | 三菱電機株式会社 | Circuit breaker |
| JPS5849674A (en) * | 1981-09-18 | 1983-03-23 | 株式会社日立製作所 | Metal-ceramics unified part |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5793106A (en) * | 1995-02-28 | 1998-08-11 | Hitachi, Ltd. | Semiconductor device |
| US6046498A (en) * | 1997-06-30 | 2000-04-04 | Nec Corporation | Device having a heat sink for cooling an integrated circuit |
| US6251709B1 (en) | 1997-06-30 | 2001-06-26 | Nec Corporation | Method of manufacturing a cooling structure of a multichip module |
| WO2005076675A1 (en) * | 2004-01-28 | 2005-08-18 | Infineon Technologies Ag | Method for bonding ceramic to copper, without creating a bow in the copper |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0732219B2 (en) | 1995-04-10 |
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