JPH01279499A - Nonvolatile storage and its verification method - Google Patents

Abstract

PURPOSE:To attain margin guarantee of a write state at verification by increasing an equivalent resistance of a part converting a current flowing to a memory in a readout circuit into a voltage. CONSTITUTION:With a signal Vin applied to a gate of a p-channel MOSFET 3, the voltage is 0V in the normal readout mode and reaches an intermediate voltage between 0V and Vcc-Vthp (Vthp is a threshold value of the FET 3) in the verify mode. The potential of a node A is decreased by increasing the voltage Vin resulting in increasing the equivalent resistance. If the voltage of the node A is high, the output of the inverter of the next stage goes to L and the written memory is read correctly.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory device, and in particular to a read circuit and a verify circuit suitable for guaranteeing a write level margin during read verify after writing to a nonvolatile memory. Regarding the method.

[Conventional technology]

Semiconductor nonvolatile memory devices retain memory even when power is cut off, and are widely used as program memories and data memories.

Semiconductor non-volatile memory devices include mask ROM and EPROM whose memory contents cannot be erased.

There is an electrically erasable nonvolatile memory called E2PROM, flash-1 type EPROM, or flash type EZFROM. Memory cell structures are diverse, and their writing and erasing mechanisms are different.
All memory uses information about the height of the threshold, or in other words, the magnitude of the current when a certain voltage is applied to the gate.
They are common in that they correspond to the I and 140 II.

In Azusa, reading from such a memory is performed under a power supply voltage (called Vcc or VOO), similar to a dynamic RAM or the like.

On the other hand, nonvolatile memories may have a read mode called verify (verj, fy). This is used for the purpose of reading the written information after writing and checking whether it has been written correctly. At this time, Vcc is generally set higher, for example, by 8 degrees IV, than in the normal read mode. This checks whether the written level has sufficient margin. That is, this is to check whether the threshold value is sufficiently high. As mentioned earlier, Vcc is applied to the memory gate or control gate, so if the threshold value is not high enough, set it high. There is. If it is determined that the threshold value is not high enough, additional writing is performed and verification is performed again. This may be repeated until it is determined that the threshold value is sufficiently high.

In this way, a margin corresponding to the difference between the Vcc value in the normal read mode and the Vcc value in the verify mode is guaranteed.

(Problem to be Solved by the Invention) However, when a general EPROM is removed from the system used and written by a dedicated program, this switching of Vcc does not pose much of a problem, but memory is used. Incorporate it into the system and write it (
Programs) will cause trouble. That is, each time the nonvolatile memory is verified, it becomes necessary to raise Vcc from the normal voltage value or to switch to another power source higher than the normal voltage value.

In other words, with one Vcc power supply, if this value cannot be changed high enough to meet the purpose of verification, it is possible to check whether it has been written, but since the Vcc value cannot be increased, it is not possible to tell whether there is sufficient margin. There won't be any.

It is an object of the present invention to provide a non-volatile memory device and a non-volatile memory device that can guarantee the margin of the written state without setting Vcc higher than during normal reading or switching to another power supply when verifying after writing to the non-volatile memory. The purpose is to provide a verification method.

[Means to solve the problem]

The above objective is achieved, as a first means, by increasing the portion of the readout circuit that converts the current flowing through the memory into voltage, or in other words, increasing the equivalent resistance of the load as seen from the memory, only during verification. .

Furthermore, the above object can also be achieved, as a second means, by increasing the logic threshold of the primary stage inverter instead of controlling the load.

[Effect]

Above 1st. According to this method, if the writing to the memory is insufficient and the threshold value is not high enough, even if it cannot be detected by normal reading, it can be detected with a small current because the resistance is high in verify mode. The voltage drop at the load becomes large, and it can be detected that the threshold value is not high enough. Further, according to the second means, if there is even a slight voltage drop in the load, it can be determined that the writing is insufficient.

〔Example〕

The present invention will be explained below with reference to Examples.

First, the basic configuration of a semiconductor nonvolatile memory device will be explained with reference to FIG. 2, focusing on reading. That is, the push circuit, erase circuit, etc. are omitted. M indicates a memory cell array. In the memory cell array, j word lines W and j data lines are arranged in an intersecting manner, and a memory cell 10 is arranged at the intersection of each word line and data line. Address buffer circuit 1
1x.

1], Y is address human power XO~X, nT, respectively
Y o −Y m is input, and its output is transmitted to the decoder/driver circuits 12X and 12Y. The decoder
Word line W is connected to 12Y by 12X of the driver circuit.
The read circuit (sense amplifier) 13 is driven, and information is read from the selected memory cell 10 in the memory cell array M. 15 is a control circuit and control signal 0
Peripheral circuits of the memory cell array are controlled by inputs 1 to Cm.

14 is a data output circuit.

Figure 2 shows dynamic RAM (Random Ac
cessMemory) or static RAM, but there is a difference in the structure of the memory cell 10, and as a result, the reading method is different.

FIG. 3 schematically shows the cross-sectional structure of a typical memory cell of an EPROM, and in this case it is a MOSFET having two gates, a floating gate 16 and a control gate 17. 18
is an insulator, 19.20 is a diffusion layer, and 21 is a semiconductor substrate. When a high voltage is applied to the control gate and drain of this memory cell, hot electrons are generated near the drain, and these electrons are accumulated in the floating gate (called a write operation), the threshold value as seen from the control gate increases. . On the other hand, the threshold value is low when no writing is performed. When reading, apply an appropriate voltage to the drain, and apply voltage (
Usually, the voltage value of Vcc is about 5V supplied from the outside)
is applied, and the current flowing through the memory cell is 111 F of information.
Make it correspond to l and it O++. In other words, if the threshold value is high, almost no current will flow.

It utilizes the fact that current flows in memory cells that are not being written to.

As mentioned earlier, in addition to EPRoM like Kono, there are also E2FROM and 7-latch type EP as non-volatile memory.
There is an electrically erasable nonvolatile memory called ROM (or flash type E2FROM). Memory cell structures are diverse, and the writing and erasing mechanisms are different, but all memories use information t to determine the level of the threshold value, or in other words, the magnitude of the current when a constant voltage is applied to the gate.
This is similar to the case of the EPROM described above in that it corresponds to r 1 u and 110 II. For example, Figure 4 shows FLOTOX (Floating Gate
E2FRO called Tunnel Oxj, de) type
FIG. 2 is a schematic cross-sectional view of a memory cell of M. Writing and erasing utilizes a tunnel phenomenon in which a thin portion provided in a part of the gate oxide film is passed through a tunnel insulating film 24. Since the two transistors are connected in series, during writing, erasing, and reading, not only the control gate 17 but also the selection gate 2
It is necessary to apply a voltage to 3 as well. However, information on the presence or absence of electrons in the floating gate, that is, the height of the threshold value, is
+ and "O++" is the same as E P ROM.This situation is also the same for most other E2FROMs with small memory cells for EzPROM. I'll call it "in."

Next, the information readout circuit (sense amplifier) 13 will be explained. As described above, the value of the threshold voltage of the memory cell 10 is associated with information.

FIG. 5 is an example of a readout circuit 13 including a memory cell 1 announced at the 1982 International Conference on Solid State Circuits. ISSCCDi Digest of Technical Papers pages 182 to 183 (ISSCCDi
gest of Technical Papers.

(pp, 182-183) However, only the basic configuration with column selection gates omitted is depicted. It consists of a drive circuit 8 including a memory cell 1 and a load 9 including a p-channel MOSFET 3. vcc is a power supply terminal.

The current flowing through the memory cell is transferred to P-channel MOSFET 3.
Read as the change in potential at a load.

Next, the characteristic parts of the present invention will be explained.

FIG. 1 is a diagram showing the basic configuration of a readout circuit according to the first means. According to the first means, p-channel M
A signal vIn is applied to the gate of OSFET 3.

That is, in the normal read mode, it is Ov, and the fifth
It will be the same as the figure, but in verify mode, OV and Vcc
-V thp (V thp is P channel MO5F
(threshold voltage of E-3). FIG. 6 schematically shows the relationship between the voltage at node A and the current flowing through p-channel MO3FET 3 when only this P-channel transistor is taken out, using gate voltage V In as a parameter. Obviously, by increasing Vln, the potential at node A at the same current value decreases. If j″ is changed, the equivalent resistance has increased.

Figure 7 shows the voltage at node A and V when the entire circuit is operated.
It shows the relationship between cc. Indicates a write state (memory threshold state is high). In addition, p-channel MOSFE
The logic threshold of the next stage inverter formed by T6 and n-channel MOSFET5 is shown.

If the voltage at node A is higher than this logic threshold, the output of the inverter becomes low, meaning that the written memory has been correctly read. In this figure, V cc ”V
I can read up to t correctly. In verify mode, V +
With the application of n, the voltage at node A changes as shown in the figure, and V
It is possible to read correctly only up to cc=Vz. In other words, if the writing depth is insufficient, this Vz will be lower than the normal read power supply voltage (
It is only necessary to determine the level of V (n level and the configuration of the generation circuit for vIn) so that the voltage level is approximately 5 V).

Next, the case of the second means will be explained using FIG. It is the same as FIG. 5 except for the last inverter section. Assuming that the heavy voltage Vg measured during normal reading is applied to the gate of P-channel MOSFET 25, an appropriate voltage Vε' from Ov to Vt is applied during verification. Of course, this Vδ may be Vcc. At this time, if you draw the same diagram as Figure 7, it will look like Figure 9. The Vcc dependence of node A remains the same, but MO3FET5
, 6, 25, the equivalent logic threshold of the next stage inverter becomes higher, and the intersection point with the potential curve of node A becomes V
+ to the lower Vcc side v2. That is, if the writing depth is insufficient, this Vz will be lower than the normal read power supply voltage (5V
It is only necessary to determine the level of Vt' and the configuration of the generation circuit for V□' so that the level of Vt' is satisfied.

A more specific explanation will be given below using Examples 1 to 3.

[Example 1] This will be explained with reference to FIG. 10. It is basically the same as in FIG. 1, but includes column selection gates 26 and 27, and also includes n-channel MO3FETs 28, 29, 30 and p-channel MOSFETs.
It includes a precharge circuit consisting of T31.

This circuit is used to quickly charge selected data lines. Furthermore, an n-channel MOSFET 30.

By making it possible to apply a sense amplifier activation signal to 32 and p-channel MO3FET 2 and 31, it is possible to power down the entire circuit. If the selected memory cell 1 has a low threshold, the potential of the node A decreases due to the memory current, and the primary stage P-channel MO3
The output voltage Vo becomes lower than the logic threshold of the inverter composed of FET 6 and n-channel MO8FET 5.
ut becomes High level.

33 is an intermediate potential generation circuit, and during verification, the signal a is high, and the signal a is low, changing from OV to Vc.
c P-channel MO
Supplied to the gate of SFET 3. At other times a
is low and a is high, p-channel MOSFE
The gate potential of T3 is grounded. In this way, the margin of the writing depth can be checked without changing Vcc, as shown in the explanation of the first means described in the above [Operation] section.

[Example 2] FIG. 11 shows a circuit configuration. p-channel MO in Figure 10
3FET 3 to two p-channel MOSFETs 34
.

It was replaced with 35. Operation 2 The operation is almost the same, except that the p-channel MO3FET 35 always operates in the saturation region, and the current vs. voltage characteristics corresponding to FIG. 6 are different.

[Example 3] This example is an example in which the second means is used, and will be explained using FIG. 12. Here, F is used as a memory cell.
A LOTOX type E"FROM memory cell 38 is used. Unlike the EPROM shown in FIGS. 10 and 11, a selection gate 23 is used in addition to the control gate 17 for cell selection.
A signal must also be applied to the In this figure, the sense amplifier activation signals of the precharge section and the amplifier section are inputted separately, but they may be inputted together. The p-channel MO3FET 25 has a p-channel MO3FET at its gate.
A signal is input from an inverter composed of a 3FET 36 and an n-channel MOSFET 37. The input signal to the inverter is at a low level in the normal read mode, and at a high level during verification. In this way, in normal read mode, Vcc is applied to the gate of p-channel MO3FET 25, so it is cut off, and in verify mode, Ov is applied, so it turns on, and as mentioned earlier, it is checked whether the write margin is sufficient. I can do it.

Here, a signal is applied to the gate of the p-channel MOSFET 25 using an inverter, but an intermediate voltage generating circuit as shown in FIG. 13 may also be used. In this case, if the signal level of b is defined in the same way as before, the output will be Vc during normal reading.
c. At the time of verification, it becomes an intermediate voltage between Ov and Vcc.

Both the dimensions and gate input voltage of p-channel MOSFET 25 may be appropriately set to ensure a desired margin.

〔Effect of the invention〕

According to the present invention, it is possible to verify the nonvolatile memory and check the margin of the write level without requiring an extra power supply, thereby facilitating on-board writing and rewriting.

Incidentally, as is clear from the above explanation, there is no harm in using the present invention together with increasing Vcc during verification. In fact, it is possible to guarantee a larger margin than with conventional methods.

[Brief explanation of the drawing]

1, 8, 10 to 13 are diagrams showing a readout circuit according to an embodiment of the present invention, FIG. 2 is a diagram showing the structure of a memory, FIG. 3 is a cross-sectional view of an EPROM cell, and FIG. Figure 4 is E2
FIG. 5 is a cross-sectional view of a FROM cell, FIG. 5 is a diagram showing a memory read circuit, and FIGS. 6, 7, and 9 are detailed explanatory diagrams of the present invention. 1...Memory cell, 3, 25...p channel MO3
FET, Figure 1 Figure 21 Kendorin board No. Z mouth IIχ Figure 3 13 Device removal circuit 14 Exit, Kahat 7r 15 Seikai map Figure 5 Vcc Shito Otsu. g Tokuino\゛Kaisho Misakiq 4 Carrying sword 6 Figure no kAOden IE Figure 7 Not 13 Figure Vc v g Figure whisper 9 Figure V2 〆, -- Vcc ■ /θ Figure 33 Cause potential release ball Kari dai II (2B % /Z Figure/Death Niru

Claims (1)

[Scope of Claims] 1. A nonvolatile semiconductor memory device in which the magnitude of a current flowing through a memory cell corresponds to binary information, including means for increasing the equivalent resistance of a load when detecting the current during verification. A nonvolatile semiconductor memory device characterized by: 2. The nonvolatile semiconductor memory device according to claim 1, wherein the means for increasing the equivalent resistance is increasing the gate voltage of at least one p-channel MOSFET serving as a load during verification. 3. A non-volatile memory device that corresponds to binary information regarding the magnitude of the current flowing through the memory cell, has a circuit that detects and judges the voltage obtained by converting the above current, and when verifying, the equivalent logic of the above circuit is used. A nonvolatile semiconductor memory device characterized by having means for raising a threshold value. 4. The means for increasing the logic threshold is to connect the drain to the inverter and its output, connect the source to the power supply,
4. The nonvolatile semiconductor memory device according to claim 3, wherein the equivalent logic threshold is raised by applying a voltage lower than that during normal reading to the gate. 5. A nonvolatile method for verifying a nonvolatile semiconductor memory device in which the magnitude of the current flowing through a memory cell corresponds to binary information, which is characterized by increasing the equivalent resistance of the load when detecting the current during verification. Verification method for semiconductor storage devices. 6. A method for verifying a non-volatile memory device that corresponds to binary information of the magnitude of a current flowing through a memory cell, characterized by raising the equivalent logic threshold of a circuit that converts the current into a voltage during verification. A verification method for non-volatile semiconductor storage devices.