JPH01241218A - Logic circuit - Google Patents

Abstract

PURPOSE:To attain a logic circuit contrived to be operated by a single power supply by providing a bias generating means so as to boost a source potential of a depletion field effect transistor(TR) to a positive potential larger than a threshold voltage of the said TR. CONSTITUTION:With a power voltage VDD supplied to a logic circuit 21, a constant current decided by a load FET 6 flows to a diode 25 via a driver FET 5 or a bypass means 22. That is, while the FET 5 is turned on, a constant current decided by a FET 6, that is, a drain current of the FET 5 flows to a diode 25. While the FET 6 is turned off, a constant current decided by the FET 6 flows to the diode 25 via the means 22. A forward voltage drop in response to the constant current is caused across the diode 25. Since the anode of the diode 25 is connected to the source of the FET 5, the source of the FET 5 is boosted to a positive potential by the forward voltage drop of the diode 25 with respect to a power line VEE.

Description

[Detailed Description of the Invention] [Summary] Regarding a logic circuit suitable for application to an ultra-high-speed logic operation integrated circuit, an object of the present invention is to provide a logic circuit that uses a depletion type field effect transistor and has a single power supply. A depletion type field effect transistor that selects and outputs a logic value on the high potential side or the low potential side according to a human logic level with a predetermined negative reference potential as the boundary with respect to the source potential; a bypass means that is connected in parallel between the drain and the source and bypasses the same current as the drain current when the field effect transistor is conductive to the source side; and a drain current when the field effect transistor is conductive, or the bypass means bias generating means that generates a positive voltage greater than the absolute value of the predetermined negative reference potential based on a bypass current caused by the bias current, and applies the voltage to the source of the field effect transistor to shift up the source potential; Consisting of:

[Industrial application field]

The present invention relates to a logic circuit, and more particularly to a logic circuit suitable for application to an ultra-high-speed logic operation integrated circuit using a single power supply while using depletion type field effect transistors.

Recently, there has been an increasing demand for high-speed operation in semiconductor integrated circuits, and Schottky barrier gate type FETs (
Below, MESFET: metalSemio
The realization of high-speed operation is being achieved through the practical application of FET (inductor FET).

GaAs has an electron mobility of approximately 5 compared to silicon.
It is more than twice as large and has various excellent physical properties as a high-speed, high-frequency device material. For example, GaAs has a larger band gap than silicon, so it is possible to obtain a high-resistance crystal called a semi-insulating crystal. In this case, parasitic capacitance can be reduced by configuring a single MESFET or an integrated circuit using MESFETs based on semi-insulating crystals, making it easy to separate elements, and realizing an integrated circuit capable of ultra-high-speed operation. can.

In addition to GaAs, there are various combinations of compound semiconductors such as gallium phosphide (GaP), indium phosphide (InP), and indium arsenide (InAs).
The above-mentioned compound semiconductors composed of elements of groups 1 and 2 are hereinafter referred to as m-v group raw conductors.

MES FETs made of m-v group raw conductors are capable of ultra-high-speed operation as described above, and can exhibit an amplification effect even at frequencies of about 30 GHz. Therefore, it can be applied to various fields that handle high-speed, high-frequency signals, and for example, it has been applied to logic circuits that perform logic operations at ultra-high speeds to realize ultra-high-speed logic operation integrated circuits.

[Conventional technology]

An example of such a conventional logic circuit is an S D F L (Shottky Diode) as shown in FIG.
FET Logic) or as shown in Figure 4.
There is L (Buffered FETLogic).

In FIG. 3, 1 is a logic circuit using 5DFL,
Logic circuit 1 functions as an inverter that inverts the input logic level and outputs it. The logic circuit l has a power supply line Vs
Power supply voltages [+2V] and (-1V) are applied by a positive power supply line VDD and a negative power supply line VEE that share s, and the input signal D in is connected to a level shift diode 2 and a constant current. pull down F
A level shift circuit 4 consisting of an ET3 converts the signal into a signal at a logic level bordering on the threshold voltage of a driver FET5 formed by a depletion type MESFET, and inputs the signal to the gate of the driver FET5. The drain of the driver FET 5 is connected to the power line vDD via the constant current-connected load FET 6, and the source is connected to the power line VSS.
The gate potential of 5 is the threshold voltage V, for example (-
When the potential becomes high (0.3V) or higher, driver FET5 becomes O.
Therefore, the output signal Dout becomes an L level that almost matches the potential of the power supply line VSS. Also, driver FET
When the gate potential of FET 5 becomes a low potential below the threshold voltage Vth, the driver FET 5 is turned off, so the output signal Dout becomes level 11, which almost matches the power supply line VDtl. That is, input signal 8. , is H level,
For example, when the voltage is 2V, a current flows to the negative power supply line VEH via the level shift diode 2 and pull-down FET3, and the gate potential of the driver FET5 is
] level, that is, the potential is lower than 2■ by the forward drop voltage of the level shift diode 2, but at this time, the gate potential of the driver FET 5 is equal to the threshold voltage V.
Since the potential is sufficiently higher than th, the driver FET 5 is turned on. Furthermore, when the input signal D in is L level, for example OV, the gate potential of the driver FET 5 becomes negative by the forward drop potential of the level shift diode 2, and the gate potential of the driver FET 5 decreases below the threshold voltage Vth. As a result, driver FET5 is turned off. In this case, in order to realize an integrated circuit by combining a large number of logic circuits 1, an input signal D in and an output signal are required.

, , the prescribed values of the logic levels, that is, the H level and L level potentials must match between the input and output, and the input signal. By providing a pull-down FET 3 on the side and pulling it down to the negative power supply line (2), the prescribed values of the logic levels on the input and output sides are made to match.

On the other hand, in FIG. 4, reference numeral 11 denotes a logic circuit using a BFL, which functions as an inverter similarly to the logic circuit 1 described above. The logic circuit 11 has a positive power line ■ that shares the power line V3S. . Power supply voltages of (+2V) and (-1V) are applied by a negative power supply line VEE. In addition, in the figure, the same components as those of the logic circuit 1 described above are given the same reference numerals, and the explanation thereof will be omitted.

Input signal. turns driver FET5 ON or OFF
By setting F, the gate potential of the source follower FET 12 is set to the potential of the power supply line VSS or power supply line VDD. That is, the input signal D in is connected to the driver FET.
When the potential is higher than the threshold voltage V of 5, the triver FET 5 is turned on and the gate potential of the source follower FET 12 becomes almost the potential of the power supply line VSS. At this time, the source follower FET 12 is turned off, so the output signal changes. , becomes almost the negative potential of the power supply line VEE via the pull-down FET 13 connected with a constant current. Furthermore, when the input signal D in has a lower potential than the threshold voltage Vth, the driver FET 5 is turned off and the source follower FET5 is turned off.
The gate potential of ET12 becomes almost the potential of the power supply line VDD, and at this time, the source follower FET12 is turned on, so the output signal is increased. The potential of ut is lower than the potential of the positive power supply line VDD by the forward drop voltage of the level shift diode 14, and higher than the threshold voltage V of the driver FET 5.

In this case, the input signal D in and the output signal are as described above. . Since the specified logic levels of the output signals must match, the output signal will change. Pull-down FET on uL side
13 and pulls down to the negative power supply line VEE, the prescribed values of the logic levels on the input side and the output side are made to match.

[Problem to be solved by the invention]

However, in such conventional logic circuits,
Since it was necessary to use a depletion type MESFET as the driver FET 5 and to match the specified logic levels on the input and output sides, there was a problem in that different types of power supplies, that is, two power supply systems, positive and negative, were required. Ta.

In this case, even if a predetermined ultra-high-speed logic operation integrated circuit is realized using logic circuit 1 or logic circuit 11, it is necessary to provide two external power supplies for positive and negative systems, and the configuration and wiring of the power supply device of the integrated circuit are It becomes complicated.

However, from the viewpoint of actual use, there is a tendency to require a device that operates with only one power source, and it is desirable to use a single power source.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a logic circuit using a depletion type field effect transistor and using a single power source.

(Means for Solving the Problems) In order to achieve the above object, the logic circuit according to the present invention has a high potential side or a low potential side, depending on the input logic level with a predetermined negative reference potential as a boundary with respect to the source potential. A depletion type field effect transistor that selects and outputs a logical value is connected in parallel between the train and source of the field effect transistor, and the same current as the drain current when the field effect transistor is conductive is passed to the source side. Generates a positive voltage larger than the absolute value of the predetermined negative reference potential based on the drain current when the field effect transistor is conductive or the bypass current by the bypass means, and bias generating means for applying the voltage to the source of the field effect transistor to shift up the source potential.

[For production]

In the present invention, a positive voltage larger than the threshold voltage of the field effect transistor is applied to bias the 1" drain current of a depletion type field effect transistor or a bypass current of the same magnitude that flows by bypassing the drain current. The voltage is generated by the generating means and applied to the source side of the field effect transistor.

Therefore, the source potential of the field effect transistor is shifted up to a positive potential greater than the threshold potential, and a voltage is generated internally to make the gate potential negative with respect to the source, thereby achieving negative power supply.

〔Example〕

FIG. 1 is a diagram showing a first embodiment of the logic circuit according to the present invention, and this embodiment is an attempt to unify the 5DFL shown in FIG. 3, and the logic circuit shown in FIG. The same reference numerals are given to the same constituent members as those in FIG.

First, the configuration will be explained. In FIG. 1, 21 is a logic circuit, and the logic circuit 21 is connected to a power supply line V.

A power supply line VDD is connected to the logic circuit 21, and the power supply line VDD applies a voltage of (+3V) to the logic circuit 21. The output of the level shift circuit 4 is a triver FET (
A bypass means 2 is input between the drain and source of the driver FET 5.
2 is connected. The bypass means 22 consists of diodes 23 and 24, which are connected in series with their respective cathodes facing the source side of the driver FET 5.

When the driver FET 5 is off, each diode 23.24 clamps the drain-source voltage to a voltage that matches the sum of the forward drop voltages of each diode 23.24, and also carries a constant current determined by the load FET 6. Bypass to the source side of driver FET5. A diode (bias generation means) 25 is connected between the source of the driver FET 5 and the power supply line VEE.
The diode 25 is connected with its cathode located on the power supply line VEE side. The diode 25 shifts the potential on the source side of the driver FET 5 to the positive side by the forward drop voltage of the diode 25, and the shape of the diode 25 is such that the forward drop voltage of the diode 25 is higher than the threshold voltage of the driver FET 5. It may be determined to have a large value. For example, each component including the diode 25 is preferably formed with shapes and dimensions as shown in Table 1 below.

Table 1 However, Lg: gate length Wg: Gate width Vth: threshold voltage Next, the effect will be explained.

Now, when the power supply voltage VDD is supplied to the logic circuit 21,
A constant current determined by the load FET 6 flows through the diode 25 via the driver FET 5 or the bypass means 22. That is, when the driver FET 5 is ON, a constant current determined by the load FET 6, that is, the drain current of the driver FET 5, flows to the diode 25, and when the driver FET 5 is OFF, the load FET 5 flows through the diode 25.
A constant current determined by ET6 flows through the diode 25 via the bypass means 22. Therefore, diode 2
5, a constant current determined by the load FET 6 will flow regardless of whether the driver FET 5 is ON or OFF.
A load FET is connected between the anode and cathode of the diode 25.
6, a forward voltage drop is generated in accordance with the constant current.

In this case, the anode of the diode 25 is connected to the driver FET.
Since the source of the driver FET 5 is connected to the source of the driver FET 5, the source of the driver FET 5 is shifted up to a positive potential by the forward voltage drop of the diode 25 with respect to the power supply line VEE.

Therefore, even if the driver I;'ET 5 is to be turned off, the gate of the driver FET 5 should be set at a negative potential higher than the threshold voltage with respect to the source, and the source of the driver FET 5 may be connected to the power supply line. Since the potential is shifted up to a positive potential with respect to VEE, the gate potential of driver FET5 is the same as that of driver FET5.
Regardless of whether 5 is ON or OFF, the potential is always positive with respect to the power supply line VEE.

In this way, in this embodiment, the potential of the power supply line VEE with respect to the power supply line VS5, which was conventionally required, is changed to the diode 2.
5, the logic circuit 21 can be generated internally.
The power supply required for this can be made into one system, and the logic circuit 21 can be provided with a single power supply. In this case, the diode 25 is connected to the output signal. The L level of uL is clamped, and the bypass means 22 outputs an output signal. Since 11 levels are clamped to the L level of uL, a predetermined specified value can be maintained even if the voltage supplied by the power line VOO fluctuates.
The stability of the output logic level can be improved. Also, the output signal. Since the amplitude of uu matches the clamp voltage of the bypass means 22, the logic amplitude is smaller than in the conventional case. Therefore, if the capacitance components serving as the load of the logic circuit 21 are the same, the logic circuit B2 for the load capacitance
1 can improve the output responsiveness. In other words, signal delay due to capacitive load can be reduced,
It is possible to achieve faster responsiveness.

In the above first embodiment, a case was shown in which the 5DFL shown in FIG.
A case in which the BFL shown in the figure is made to have a single power source will be described with reference to FIG. 2. In addition, in FIG. 2, the BF shown in FIG.
Components that are the same as those in L are given the same reference numerals, and their explanations will be omitted.

In the figure, 31 is a logic circuit, and the logic circuit 31 includes a power line V9. A voltage of (+3 V) is applied. Driver FE
A bypass means 34 consisting of diodes 32, 33 is connected between the drain and source of T5, and each diode 32, 33 has its cathode connected to the driver FET 5.
A bias generating means 37 consisting of diodes 35 and 36 is connected between the source of the driver FET 5 and the power supply line VEE, and each diode 35 and 36 are connected in series with the cathodes facing the power supply line VI side. Therefore, the bias generating means 37 has a load F E
A constant current determined by T6 always flows through the driver FET5 or the bypass means 34,
The source potential of the driver FET 5 is shifted up to a positive potential with respect to the power supply line V by the sum of the forward drop voltages of the diodes 35 and 36. In this case, the shape of the diodes 35, 36 may be determined so that the sum of the forward drop voltages of the diodes 35, 36 is larger than the threshold voltage of the driver FET 5. Each component is shown in Table 2 below.
It is preferable to form the shape and dimensions as shown in FIG.

Table 2 However, Lg: Gate length Wg: Gate width Vth: Threshold voltage As described above, in this embodiment as well, the source potential of the driver FET 5 becomes a larger positive potential with respect to the power supply line VEE than the threshold voltage of the driver FET 5. Since it is shifted up, it is possible to use one power source for the logic circuit 31 as in the first embodiment.

Furthermore, since the bypass means 34 and the bias generation means 37 clamp the source potential of the driver FET 5, that is, the L level, and the drain potential of the driver FE 75, that is, the 1 (level), the same effect as in the first embodiment can be obtained. Can be done.

〔effect〕

According to the present invention, the source potential of the depletion type field effect transistor is shifted up to a positive potential greater than the threshold voltage of the field effect transistor by providing the bias generating means, so that the gate potential is shifted to the source potential. A voltage for making the voltage negative can be internally generated, and a logic circuit that can be used as a negative power source can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing a first embodiment of a logic circuit according to the present invention, FIG. 2 is a circuit diagram showing a second embodiment of a logic circuit according to the present invention, and FIG. 3.4 is a circuit diagram of a conventional logic circuit. FIG. 3 is a circuit diagram showing a configuration using 5DFL, and FIG. 4 is a diagram showing a logic circuit.
FIG. 3 is a circuit diagram showing a configuration using FL. 21.31...Logic circuit, 5...Driver FET (field effect transistor), 22.34...Bypass means, 25...
・Diode (bias generation means), 37...
Bias generation means. Patent applicant: Fujitsu Limited 3. Agent: Patent attorney Igata Tei -1,6'9 謁υ王ゆう 21;
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Claims (1)

[Claims] A depletion type field effect transistor that selects and outputs a logic value on the high potential side or the low potential side according to the input logic level with a predetermined negative reference potential as the boundary with respect to the source potential. , a bypass means connected in parallel between the drain and source of the field effect transistor to bypass the same current as the drain current when the field effect transistor is conductive to the source side; Based on the drain current or bypass current by bypass means,
Bias generating means for generating a positive voltage larger than the absolute value of the predetermined negative reference potential and applying the voltage to the source of the field effect transistor to shift up the source potential. A logic circuit that