JPH01241091A - Semiconductor device - Google Patents

Abstract

PURPOSE:To obtain internal voltage generation circuits which are less in noise, small in occupying area, and low in power consumption by causing plural internal circuits to selectively operate by means of control signals and at least two internal circuits which do not operate simultaneously to share one internal voltage generating circuit. CONSTITUTION:Internal voltage generating circuit 3-5 and load circuits, such as pulse generating circuit 6-9, etc., using the outputs of the circuits 3-5 are arranged closely to each other and two load circuits which have a selected- nonselected relation between them about an address signal ai, etc., share one internal voltage generating circuits. Since the load circuits are provided closely to the internal voltage generating circuits 3-5, the impedance of the wirings can be reduced and, as a result, the level of produced noises can be suppressed. Moreover, since two load circuits having a selected-nonselected relation between them about the address signal ai share one internal voltage generating circuit, the chip occupying area and power consumption of the circuit can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a semiconductor device that uses an internal power supply voltage different from an external power supply voltage inside the device.

[Conventional technology]

As the elements of ultra-highly integrated circuits become smaller, the withstand voltage of the elements tends to decrease, and the power supply voltage for operating the circuits has to be lowered.

However, it is desirable for the power supply voltage to be supplied from the outside to be the same as before in terms of usability.As a means to meet such demands, an external power supply voltage Vcc (for example) is used.

There is a semiconductor device in which a voltage (5V) is dropped within a chip, and a circuit using microscopic elements is operated using the dropped internal voltage (V) (for example, 3V).

In this regard, see, for example, I.N.S.C., Digest of Technical Papers, pp. 282-283, February 1984, 1Iss.
cc DIGEST OF TECHNICAL PA
PER3,P P2S5-283. Feb,, 19
84).

This is described in this document in Figure 3. The above technology is MOS
Showing an example applied to DREM, 1 is a semiconductor chip,
2 is a peripheral circuit, 3 is an internal voltage generation circuit, 6 is a pulse generation circuit, and 1o is a memory array. The pulse generating circuit 6 consists of two AND circuits 23 and 24. The memory array 10 has the following configuration. 14.15 is the data line,
16 and 17 are MoS transistors (MO8T) for data line precharging, and 18 is a sense amplifier.

Reference numeral 19 denotes a memory cell, which consists of 20 storage capacitors and 21 transfer gates.

The memory array 10 has a 16.1
7.21 MO8T is used, so the withstand voltage is low. Therefore, the internal voltage Vm (for example, 3V) is lower than the external power supply voltage Vcc (for example, 5V).
It is operated by pulses.

For this reason, an internal voltage generating circuit 3 that generates an internal power supply voltage v billion, and a pulse generating circuit 6 that generates a pulse with an amplitude of this Va are provided. Here, the internal power supply voltage Vt is lowered from the external power supply Vcc through the internal voltage generation circuit 3.

The memory array 10 receives the pulse φP as MO8T16.1
A pulse φ is applied to the transfer gate 21 to precharge the data line, and a pulse φ is applied to the transfer gate 21 to read information stored in the memory cell. Timing pulses φP, φ, of voltage amplitude Vcc output from
With AND output.

Voltage amplitude ■ Dew pulse.

As described above, by using the internal voltage generating circuit, the problem of the reduction in element breakdown voltage can be solved while keeping the external interface the same as before.

[Problem that the invention seeks to solve]

In the above-mentioned conventional technique, no consideration was given to the arrangement and structure on the chip of the circuit operated by the internal power supply voltage Va. That is, the internal power supply voltage V.

No consideration was given to the placement of internal voltage generation circuits or the wiring of their output voltages when there are multiple circuits that operate in the same manner.

For example, when the above-mentioned conventional technique is applied to a semiconductor memory, the following problems occur. Figures 4 and 5
The figure shows an example to which the above conventional technology is applied. In FIG. 4, 1 is the entire semiconductor memory chip, 2 is a peripheral circuit, 3 is an internal voltage generation circuit, 6°7.8.9 is a pulse generation circuit, 1
0, 11, 12° 13 are memory mats composed of fine MO8T. Since the memory mat uses minute elements, it is operated with an internal power supply voltage Vm. Internal voltage generating circuit 3 and pulse generating circuits 6 to 9 are circuits for this purpose. Internal voltage generation circuit 3 generates internal voltage ■1,
The pulse generating circuits 6 to 9 generate pulses φPitφP2. of the amplitude of the internal power supply voltage v1. φpa.

φ1 is generated respectively.

In this example, there is only one internal voltage generating circuit 3 for four pulse generating circuits 6 to 9. Therefore, the internal power supply voltage VA generated by this internal voltage generation circuit 3
In order to supply each pulse generation circuit with a long wire extending from the top side to the bottom side of the chip, the parasitic impedance of the wire increases, causing noise generation. Therefore, if the wiring width is increased in order to reduce this impedance, a problem arises in that the area occupied by this on the chip increases.

FIG. 5 shows an example in which one internal voltage generation circuit 3, 4, 24.5 is provided for each pulse generation circuit in order to avoid the problem of the example of FIG. 4 in which the wiring becomes long. In this way, the pulse generation circuits 6 to 9 and each internal voltage generation circuit 3
, 4, 24.5 can be minimized, but
The same number of internal voltage generation circuits as the number of pulse generation circuits are required.

Therefore, the area occupied by the internal voltage generating circuit on the chip and the current consumed by the circuit are increased compared to the example shown in FIG. If the number n of pulse generation circuits serving as load circuits for the internal voltage generation circuit increases further, the occupied area and power consumption become serious problems for high integration and low power consumption.

The purpose of the present invention is to solve the above problems and achieve low noise.

An object of the present invention is to provide an internal voltage generation circuit that occupies a small area and consumes low power.

[Means for solving problems]

The above purpose is to place an internal voltage generation circuit and a load circuit such as a pulse generation circuit that uses its output as a power source in close proximity, and to create one load circuit that can be selected or unselected by control signals such as address signals. This is achieved by adopting a configuration in which the internal voltage generation circuits of the two are shared.

For example, the plurality of internal circuits mentioned above are semiconductor memories,
The present invention is extremely effective when the control signal is an address signal of the semiconductor memory.

[Effect]

By placing the internal voltage generating circuit and a load circuit such as a pulse generating circuit that uses its output as a power source in close proximity, the impedance of the wiring between them can be reduced, thereby suppressing the level of noise generated. be able to.

Further, by sharing one internal voltage generating circuit with load circuits that are selected and unselected by control signals such as address signals, the number of internal voltage generating circuits can be reduced. Therefore, the chip area occupied by the circuit and the power consumed by the circuit can be reduced. Here, select among the load circuits.

When the number of circuits in the non-selected state is m and Q, respectively, the driving capacity of the internal voltage generation circuit is sufficient for m circuits. That is, there is no need to increase the driving capacity by sharing.

〔Example〕

An embodiment of the present invention will be described below with reference to FIGS. 1 and 2. Although an example in which the present invention is applied to a semiconductor memory will be described here, the present invention can also be applied to other semiconductor devices. In FIG. 1, 1 indicates the entire chip, 2 is a peripheral circuit, and 3 and 4.5 are internal voltage generation circuits that generate an internal full voltage m.

6.7 and 8.9 use the output of this internal voltage generation circuit as a power source to generate pulses φPitφpH, φp with voltage amplitude v1.
Pulse generation circuit that generates at φP4, 10.11,
12.13 are φF small, φPatφp8. φF
This is a memory mat using microscopic elements operated by 4. FIG. 2 is a diagram showing the operation timing of these circuits.

A voltage from a single external power supply Vcc (for example, 5V) is applied to this semiconductor memory chip.

The internal voltage generating circuits 3, 4.5 output an internal power supply voltage Vm (for example, 3 V) lowered from Vcc, and are supplied to the pulse generating circuits 6, 7, 8.9, respectively. And for the pulse generation circuit.

The timing pulse φ shown in FIG. 2 and the address signal a
t and 8 dishes and 77 in reverse phase are input.

The peripheral circuit receives external addressless signal A1 and outputs internal address signals a1 and al using external control signals (here, row address strobe signal RAS, column address strobe signal CAS, and write enable signal WE).
) and generates an internal timing pulse φt. This circuit is operated directly with the external power supply voltage Vcc because it does not have much effect on the degree of integration of the chip, so there is no need to use minute elements, and because of the external interface, but of course it is operated directly with the internal power supply voltage Va. You may run it.

In the memory, only the mat selected by the address operates. In this example, a, = 11 Q? + (
,.

= i411#), mats 10 and 12 are selected (1
1 and 13 are not selected), a arc = ''1'' 6 u = 110
'1), mat 11 and 1:3 are selected (10 and 12
is not selected). Therefore, only the pulses for the selected mat are output.

That is, as shown in FIG. 2, when az="0", the pulse generating circuits 6 and 8 output φPi and φP8 by the timing pulse φt, and the mats 10 and 12, conversely,
When a1="1", pulse generation circuits 7 and 9 generate pulses φ, 2 . Output φF4 and mats 11 and 13
make it work.

The feature of this embodiment is that each internal voltage generating circuit is arranged close to the pulse generating circuit, and moreover, the internal voltage generating circuit 4 is shared by the pulse generating circuits 7 and 8. Therefore, the wiring is shorter and the impedance due to the wiring is lower than in the example shown in FIG. 4, and the level of noise generated thereby can be suppressed. Furthermore, compared to FIG. 5, the number of internal voltage generating circuits is reduced by one, thereby reducing the chip area and power consumption. Moreover, since the pulse generation circuits 7 and 8 do not operate simultaneously, the internal voltage generation circuit 4 only needs to drive one pulse generation circuit, and there is no need to double its driving capacity.

Here, for a specific example of the internal voltage generation circuit, see, for example, Japanese Patent Application No. 57-220083. and Literature I Nis Niskenshi Shi, Digest of Technical Papers, pp. 282-283 (19
February 1984), (l5SCCDIGEST OF TE
CHNICAL PAPER5, PP 282-283
.

Feb., 1984).

Further, the pulse generating circuits 5 to 8 can be realized by the circuit shown in FIG. 6, for example. In Figure 6(a), 25 is P
Two-man power AN consisting of a channel MOS transistor ゛l゛1゜T2 and an N-channel MOS transistor T3゜T4.
This is the D circuit. The circuit operates with Vcc, and its inputs are a timing pulse φ and an address signal am (or a
t).

26 is an inverter consisting of a P-channel MOS transistor T5 and an N-channel MOS transistor T6;
Operates on Va. In other words, as shown in FIG.
1'' (potential Vcc), when φ is input, a pulse φP with the amplitude of the internal power supply V is output.The power supply of the NAND circuit is the same external power supply Vcc as the power supply of the 5 peripheral circuits. is used, but it may be operated with internal power supply voltage of 7 sections.

However, in this case, the load of the internal voltage generation circuit is
Increases by the number of circuits.

FIG. 7 shows an example in which the number of internal voltage generating circuits is further reduced by one compared to the embodiment shown in FIG. address signal am
(or 〒1), the timing pulse φ0, and the pulses φPI, φPatφpJlt φp4 are the same as those described in FIGS. 1 and 2.

In this embodiment, pulse generation circuits 6 and 7 share internal voltage generation circuit 3, and pulse generation circuits 8 and 9 share internal voltage generation circuit 5, respectively. Therefore, the number of internal voltage generation circuits is further reduced by one, thereby reducing the chip area and power consumption.

Here, as shown in FIG. 2, pulse generation circuits 6 and 7.
8 and 9 do not operate at the same time.

Therefore, each of the internal voltage generating circuits 3 and 5 only needs to be able to drive one pulse generating circuit, and there is no need to double the driving capacity.

FIG. 8 shows an embodiment in which the present invention is applied to a case where there are eight memory mats. Here, 1 is a semiconductor chip, 2 is a peripheral circuit, 3 and 4 are internal voltage generation circuits 6 to 9, 27 to 30 are pulse generation circuits, 10 to 13, and 31 to 34 are memory mats. , out of 8 memory mats,
two are selected by address signals a1 and a4,
Only the selected memory mat will work. That is, a
When iaJ="OO", memory mats 10 and 29, a@
When a4 = “01”, 11 and 30, 51, 1. ：“
10'', 12 and 31 are selected, and when 6, 6.="11", 13 and 32 are selected. Therefore, only the selected memory mat pulse φph (k=1 to 8) is output.

That is, as shown in FIG. 9, the address signal a*a
When J = “00”, pulses φP1 and φP6.

When a quantity aa = “01”, φP2 and φpet at
When aa="10", φ-3 and φP7. alaJ=“
11'', φF4 and φP6 are output, respectively. This pulse φPk (k=1 to 8) is a pulse output at the timing of the timing pulse φt, and its amplitude is equal to the internal power supply voltage V.

This embodiment is an example in which four pulse generation circuits for operating the memory mat are shared by one internal voltage generation circuit, so that the number of internal voltage generation circuits is two in total. In this way, by configuring multiple pulse generation circuits to share a smaller number of internal voltage generation circuits,
The number of circuits can be significantly reduced, resulting in reductions in chip area and power consumption.

〔Effect of the invention〕

According to the present invention, when there are multiple load circuits in a chip that use internal voltage as a power source, the wiring from each internal voltage generation circuit to each load circuit can be shortened, so the noise level can be kept low. can. Further, since the number of circuits can be reduced without increasing the driving capability of the internal voltage generation circuit, the occupied area and power consumption can be reduced.

[Brief explanation of the drawing]

1.7.8 is a plan view showing the configuration of a semiconductor memory according to an embodiment of the present invention, FIG. 2 is a pulse timing diagram of FIG. 1,
9 is a pulse timing diagram of FIG. 8, FIGS. 3, 4, and 5 are plan views showing the configuration of a conventional semiconductor memory, and FIG. 6 is a circuit diagram showing an embodiment of a pulse generation circuit. It is. 1... Semiconductor chip, 2... Peripheral circuit, 3-5, 2
4... Internal voltage generation circuit, 6-9, 27-30...
Pulse generation circuit, 10-13. 31-34...Memory mat, 14.15...Data line, 16, 17.21
...Fine MO5'r, 18...Sense amplifier, 19
...Memory cell, 20...Storage capacity, 22.23.
...AND circuit, 25...NAND circuit, 26...
Inverter circuit, Tl, T2. T5-P channel MO5
T. Figure 1 Figure 2 Figure 3. T4. Ding cN+1? 103τ茅 3 fig. er 40 fig.

Claims (1)

[Claims] 1. In a semiconductor device having a plurality of internal voltage generation circuits and a plurality of internal circuits that use the output of the internal voltage generation circuit as a power supply, the plurality of internal circuits can be selectively controlled by a control signal. A semiconductor device characterized in that at least two of the internal circuits that operate simultaneously and that do not operate simultaneously share one internal voltage generating circuit. 2. The semiconductor device according to claim 1, wherein the plurality of internal circuits are semiconductor memories, and the control signal is an address signal of the semiconductor memory.