JPH01238310A - Clock driver circuit - Google Patents

Abstract

PURPOSE:To attain high speed drive of a large capacity load by driving a switching element connected between an output terminal of a complementary emitter follower circuit of each stage and ground by a delay clock pulse corresponding to the delay time of each said stage. CONSTITUTION:Input transistors(TRs) QNa-QNd and a switching TR QNe, are switched by using each delay time giving each delay time corresponding to a delay time of the clock pulse by the complementary emitter follower circuit of each stage to an input clock pulse. Thus, with the input clock pulse fed to an input terminal 1 at a high level, the input and output terminals of each stage are brought forcibly to a ground potential thereby switching on/off the complementary emitter follower circuit of each stage completely. Thus, a rectangular pulse with a large amplitude of nearly 5-7V can drive the load CL surely at a high speed.

Description

DETAILED DESCRIPTION OF THE INVENTION A. Industrial Field of Application The present invention is directed to charge coupled devices (CCDs).
The present invention relates to a clock driver circuit for driving a capacitive load such as a D@vice), and particularly relates to an improvement of a clock driver circuit formed by cascading complementary emitter follower circuits.

B. Summary of the Invention The present invention provides a clock driver circuit in which complementary emitter follower circuits are connected in cascade, in which a switching element is provided between the output end of each stage of the complementary emitter follower circuit and ground, and the complementary emitter follower circuit in each stage is connected in series. By driving the switching element with a delayed clock pulse in which a delay time corresponding to the delay time in the circuit is given to the input clock pulse, a large capacity load can be driven at high speed.

C Conventional technology Conventionally, charge coupled devices (CCDs)
For example, as shown in FIG. 2, a clock driver circuit that drives a capacitive load such as a
transistor (Q-+mu)) and PNP transistor (
Q.

(1)) Multiple (1-3) stages of complementary emitter follower circuits are connected in cascade with each base as a common input terminal and each emitter as a common output terminal, and the first stage is an NP
Generally used are a structure in which an input circuit is provided using N) transistors (Q, ), and a structure in which inverter circuits using transistors (0MO3) are connected in cascade in multiple stages.

D Problems to be Solved by the Invention By the way, in the clock driver circuit using bipolar transistors described above, each stage of NPN) transistors (Q,
, (MU)) and PNP) transistor (Q.

. , ) are not completely switched on or off due to vF, and capacitive loads such as COD (
CL) cannot be driven at high speed.

In addition, a clock driver circuit using transistors (0MO3) can be easily configured in a complementary manner, but when driving a large capacity load,
There is a problem in that it is necessary to increase the number of cascade-connected impark circuits, resulting in an increase in area.

SUMMARY OF THE INVENTION In view of the above-mentioned conventional problems, the present invention aims to provide a clock driver circuit with a novel configuration that can drive a large capacity load at high speed using a complementary circuit using bipolar transistors. This is the purpose.

In order to achieve the above-mentioned object, the present invention provides cascaded complementary emitter follower circuits and an input clock pulse with a delay time corresponding to the delay time in each stage of the complementary emitter follower circuit. and a switching element connected between the output terminal of the complementary emitter follower circuit of each stage and the ground, and driven by a delay/clock pulse given a delay time in the delay circuit. It is characterized by consisting of

F. Effect In the clock driver circuit according to the present invention, the switching element connected between the output terminal of the complementary emitter follower circuit in each stage and the ground gives the input clock pulse a delay time corresponding to the delay time in each stage. By driving with a delayed clock pulse, the bases of the bipolar transistors constituting the complementary emitter follower circuits in each stage are forced to the ground potential.

G. Example Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

The embodiment shown in the circuit diagram of FIG. 1 is a complementary bipolar transistor (NPN) transistor (QN).
(1-4) Complementary emitter follower circuits with each base of transistor (QP) as a common input terminal and each emitter as a common output terminal.
The present invention is applied to a clock driver circuit formed by cascading stages.

In this embodiment, an NPN) transistor (Q) constituting the first stage complementary emitter follower circuit
ll(1)) and PNP) transistors (QP(,)) have their respective bases connected to the collector of the first input transistor (QN-) as a common input terminal, and are connected to the power supply via a resistor (R1). connected to the input terminal.

The first input transistor (QN-) has its base connected to the clock input terminal (1) via the first delay circuit (DL+), and its emitter is grounded.

The first delay circuit (DL, ) has a delay time determined by the resistor (R+) and capacitor (C9) at the input terminal (
1) is configured to provide input/clock pulses supplied to

The bases of the NPN transistor (Qmn+) and PNP transistor (QP(1)) constituting the next stage complementary emitter follower circuit serve as a common input terminal, which is the output terminal of the first stage complementary emitter follower circuit, that is, the NPN transistor. (Q□l)
) and PNP ) are commonly connected to the bases of the transistors (QP(1)), and are further connected to the collector of the second input transistor (QsJ) and connected to the resistor (R
5) is connected to the power supply input terminal.

The base of the second input transistor (QNb) is connected to the clock input terminal (1) via the second delay circuit (DLR), and the emitter is grounded.

The second delay circuit (DLR) has a delay time of τ8 using a resistor (R8) and a capacitor (C*) at the input terminal (
1).

Furthermore, the NPN ) transistor (Qo, )) and the PNP ) transistor (QFI.) that constitute the complementary emitter follower circuit in the next stage have their respective bases as a common input terminal and the output terminal of the complementary emitter follower circuit in the previous stage. In other words, the above NPN) transistor (Q
Nt. ) and PNP ) are commonly connected to the bases of the transistors (QP(1)), and are further connected to the collector of the third input transistor (Q, c) and connected to the above power supply via the resistor (R1). connected to the input terminal. The base of the third input transistor (QM-) is connected to the clock input terminal (1) via the second delay circuit (DLR), and the emitter is grounded.

The NPN transistor (QN(o)) and the PNP transistor (QP(41), which constitute the final stage complementary emitter follower circuit, have their respective bases as a common input terminal and the output terminal of the previous stage complementary emitter follower circuit, that is, the NPN ) transistor (QN(3)
) and PNP) transistors (QP(-1)), and a fourth input transistor (
Q, , ) is connected to the collector of the resistor (R
4) is connected to the power supply input terminal. Furthermore, the above NPN) transistor (QN+4>) and the PNP
Each emitter of the transistor (Q□4) is connected to a capacitive load (Ct) such as COD via the clock output terminal (2) as a common output terminal, and is also connected to the collector of the switching transistor (Qmd). has been done.

The fourth input transistor (QN, ) and the switching transistor (QN-) have their respective bases connected to the clock input terminal (1) via the third delay circuit (DL3), and each emitter connected to the ground. has been done.

The third delay circuit (DL) has a delay time of τ due to the resistor (R5) and capacitor (C5).
).

Here, the first to third delay circuits (DL+).

The delay times (τ, ), (τmaro), (τ, ) of (DLI) and (DL3) are made to correspond to the delay time of the clock pulse by the complementary emitter follower circuit of each stage, and <r, is set.

In the clock drive circuit configured as described above, each delay time (τ,), (τ,), (τ,) corresponding to the delay time of the clock pulse by the complementary emitter follower circuit of each stage is given to the input clock pulse. At each delayed clock pulse, each of the input transistors (QN-),
By switching and driving the switching transistors (Q-), (Q, lc), (QNm) and the switching transistors (Q, , ), each stage is activated when the input clock pulse supplied to the input terminal (1) is at a high level. The input terminal and output terminal of the
0~0. I V ), the complementary emitter follower circuit of each stage can be completely switched on and off, and even when the capacitance of the load (CL) is large, it can respond to high-speed input clock pulses. , the above load (
CL) can be reliably driven at high speed.

H Effects of the Invention In the clock driver circuit according to the present invention, the switching element connected between the output terminal of the complementary emitter follower circuit in each stage and the ground is connected to the input clock pulse by a delay time corresponding to the delay time in each stage. By driving with the given delayed clock pulse, the bases of the bipolar transistors constituting the combinatorial follower circuits in each stage are forced to the ground potential, so that the bipolar transistors are completely switched on and switched off. - Turns off, allowing high-capacity loads to be driven at high speed with rectangular pulses of relatively large amplitude.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing the configuration of a clock driver circuit according to the present invention. FIG. 2 is a circuit diagram showing the configuration of a conventional clock driver circuit. QN (11~QN (41...NPN) transistor Q
P(1)~Qp<a>...PNP) transistor Ct
, ...... Capacitive load DL, ~DL,
...delay circuit

Claims (1)

[Scope of Claims] Cascade-connected complementary emitter follower circuits, a delay circuit that provides an input clock pulse with a delay time corresponding to the delay time in the complementary emitter follower circuit at each stage, and an output of the complementary emitter follower circuit at each stage. 1. A clock driver circuit comprising: a switching element connected between an end of the switching element and a ground, and driven by a delayed clock pulse given a delay time by the delay circuit.