JPH01238171A - Gate-insulated bipolar transistor - Google Patents

Abstract

PURPOSE:To prevent a latching effect without a diffusion potential between a source layer and a channel layer being exceeded by the potential change under a source layer, by collecting carrier to be injected from a drain region by one conductivity type layer in the drain region under the channel layer. CONSTITUTION:The same conductivity type P<+> type collector layer 32 as that of a channel forming layer is formed with substantially the same width in the N<-> type layer 2 of a drain region under the P-type layer 3 of a channel layer, and connected by a P<+> type layer 31 to the layer 3 and a source electrode. Part of carrier (hole) 11 injected from a P<+> type layer 1 to a drain region 2 is collected to the layer 32 of a collector layer, and the number of holes arriving at the layer 3 of an N<+> type layer 4 is reduced. An important point to design an IGBT is of an interval W of the region 2 between the layers 32 for collecting the carrier. If the interval is excessively narrow, resistance is increased against the carrier (electrons) injected from a source layer 4 designated by a solid line 12, thereby causing a voltage drop between a source electrode 7 and a drain electrode 8 to increase.

Description

Detailed Description of the Invention [Industrial Application Field] The present invention relates to a bipolar transistor and an MO3 field effect transistor (hereinafter referred to as MO3F) that supplies a base current to the bipolar transistor.
The present invention relates to an insulated gate bipolar transistor (hereinafter referred to as IGBT) formed in the same semiconductor body.

[Conventional technology]

In recent years, in the field of semiconductor devices, bipolar types centered on PN junctions have been the main type, but with improvements in MO3 technology, field effect types have come to be used more frequently.Particularly in the field of power transistors, MOSFETs are increasingly being used in place of bipolar transistors.However, in the field of high-voltage applications, MOSFETs have a problem in their use because they have a large voltage drop in the conductive state.To solve this problem, vertical type An IGBT has been developed in which a region having a conductivity type opposite to that of the drain region is formed in the drain region of a MOSFET.As shown in FIG. forming an N-layer 2 with a low impurity concentration through the N-layer 2, selectively forming a 2-layer 3 on the surface of this N-layer 2, and further selectively forming a source region N0 layer 4 on this surface; 2 layer 3 N- layer 2
The surface order sandwiched between and N0 layer 4! ! This region is used as a channel formation region, and a gate electrode 6 is formed thereon via a gate oxide film 5.
form. Then, the source electrode 7 is made to straddle the deep P layer 31 and the N'' layer 4 formed on the side far from the gate electrode 6 of the second layer 3, and the drain of the P layer 1 is brought into contact with the edge 8. The top of the gate electrode 6 is covered with a nitride film 51. In this IGBT, conduction in the drain region 2 is improved by injecting carriers from the P" layer 1 into the drain region 2 in a conductive state. This reduces the voltage drop by causing frequency modulation.

[Problem to be solved by the invention]

However, when the number of injected carriers from the injected carrier layer 1 increases, the broken line 1 appears in the channel layer 3 below the source region N4 layer 4.
This injected carrier, denoted by 1, reaches and flows under the N'' layer 4 and reaches the source electrode 7, but the two layers 3 below the N° layer 4 reach the source electrode 7.
A lateral potential difference is generated under the N0 layer 4 due to the product of the lateral resistance of the N0 layer 4 and the current due to the arrived carriers (holes) and the heat generated in the 2nd layer 3 and the N- layer 2, and this potential difference becomes the N0 When the diffusion potential between layer 4 and layer 23 is exceeded, carriers (electrons) are injected from N' layer 4 of the source layer, and N''' layer 4, layer 2 3. A latching effect occurs in which the thyristor consisting of 1 becomes conductive regardless of the gate electrode 6, and the transistor effect is lost.

The N″″ layer 21 between the 21 layer 1 and the N− layer 2 is for preventing this, and reduces the injection of carriers from the P′ layer 1 to the N− layer 2. In addition, measures to prevent the latching effect are taken by lowering the lateral resistance of the two layers 3 below the N'' layer 4.

However, it is difficult to control the number of carriers (holes) that reach the bottom of the N0 layer 4, and the conductivity modulation effect in the drain region also decreases, resulting in a decrease in current density. To achieve the current and voltage drop, the chip area had to be increased.

An object of the present invention is to provide an IGBT that eliminates such drawbacks, prevents latching effects, and achieves desired current and voltage drop in a small area.

[Means to solve the problem]

In order to solve the above problems, the present invention provides a drain region consisting of a semiconductor layer of a first conductivity type in contact with a drain electrode, a semiconductor layer of a second conductivity type provided thereon, and a drain region of the drain region. a channel layer of a second conductivity type formed on a part of the surface opposite to the electrode side; a source layer of a second conductivity type formed on the surface of the channel layer with a channel formation region left at the end; In an IGET having a gate electrode formed on a channel forming region via a gate insulating film, a source electrode contacting a source layer and a channel layer interposed therebetween, a channel layer, a channel layer in a drain region below the channel layer, It is assumed that a layer of the first conductivity type having approximately the same extent as is formed, and that this layer and the surface in contact with the source electrode are connected by a layer of the first conductivity type with a high impurity concentration.

[Effect]

The layer of the second conductivity type in the drain region below the channel layer collects carriers injected from the drain region, reducing the number of carriers reaching the region below the source layer of the channel layer above it. , carriers are injected from the source layer to the drain region only through the channel region formed by the gate signal. As a result, the potential change under the source layer does not exceed the diffusion potential between the source layer and the channel layer, and the latching effect is prevented.

〔Example〕

FIG. 1 shows a cross section of an embodiment of the present invention, and parts common to those in FIG. 2 are given the same reference numerals. As is clear from the figure, there is a P" collector J of the same conductivity type as the channel forming layer in the N- layer 2 of the drain region under the second layer 3 of the channel layer.
I32 are formed with almost the same width, and 20 layers 3
1 is connected to the second layer 3 and the source electrode. A part of the carriers (holes) 11 injected into the drain region 2 from the P layer 1 are collected in the P layer 32 of the collector layer, and N
The number of holes reaching the second layer 3 below the fourth layer 4 is reduced.

Figures 3 (fal to ff) show the specific manufacturing process of the IGBT shown in Figure 1. First, a P layer 1 is formed on one surface of the N-type substrate 2 by diffusion, etc., and a P collector layer is formed on the other surface. 32 is partially formed by diffusion, etc. (Figure aL) Next, the N- layer 21, which covers the P layer 32 and becomes a part of the drain region, is formed by the Ebitaki-Soyal method (Figure b).
A P connection layer 31 is formed by diffusion or the like in the area where the source electrode is to be formed (Figure c), and a second layer portion 3 that will become the channel layer is further formed by ion implantation or the like (Figure d).
A N layer 4 serving as a source region is partially formed in the two layers 3, and the surface is covered with a gate insulating film 5 or the like. (Figure eL) On this insulating film 5, a gate electrode 6 is formed by patterning a polycrystalline silicon layer, sandwiching the channel formation region of the channel layer 3 and spanning the source region 4 and drain region 2, and After contacting the source electrode 7 over part of the layer 4 and N'' 113, it is covered with a surface protective film 51 such as SiJ, and finally, a drain electrode of the P layer 1 under the drain region 2 is formed. Figure f).

An important point in designing an IGBT as shown in FIG. 1 is the distance W between the drain regions 2 between the collectors 1i32 for collecting carriers; if this distance is too narrow, the source Carriers injected from layer 4 (
This increases the resistance to electrons), which causes an increase in the voltage drop between the source electrode 7 and the drain electrode 8. Therefore, from the relationship between the resistance of the drain region 2 to carriers (electrons) injected from the source layer 4 and the number of carriers (holes) injected from the drain region 2 that reach the channel layer 3, set W to an optimal value. must be done.

This can be determined from the carrier injection efficiency from the 29 layer 1 into the drain region 2, the transport efficiency of the injected carriers in the drain region, etc., and the carrier concentration collected in the P' layer 32 and the carriers reaching the 29 layer 3. This is possible by calculating the lateral resistance of the channel layer 3 under the N''' layer 4 of the source layer.
This can be done in the same way as O3FET.

FIG. 4 shows an IGBTIG N-board 2 based on the present invention.
In the example in which C20 is formed, the P0 collector layer 32 and the P1 connection layer 31 formed in the GBT according to the present invention are
This shows that it can be created in the same process as the buried layer 22 and separation layer 23 of the IC 20.

The above explanation was about N-channel IGBT, but
It goes without saying that the present invention is equally applicable to P-channel IGBTs.

[Effects of the Invention] According to the present invention, carriers injected from the drain region are collected in the collector layer formed under the channel layer and connected to the source electrode and having the same conductivity type as the channel layer, thereby reducing the low voltage directly under the source layer. Fewer carriers reach the channel layer with impurity concentration, lowering the potential difference due to lateral resistance and preventing the latching effect. However, the voltage drop in other thick drain regions can be made very small because the latching effect is prevented and the density of carriers injected from the drain electrode can be increased. Overall, the current density can be increased and the voltage drop can be reduced compared to conventional IGBTs.

As a result, the chip area is reduced relative to the desired current and voltage drop, and the economical effects are large, although the manufacturing process is increased somewhat. The increase in manufacturing steps can be eliminated if the IGBT is formed on the same chip as the integrated circuit, and the IGBT according to the present invention is extremely effective as a power device equipped with a control circuit.

[Brief explanation of the drawing]

FIG. 1 is a sectional view of a main part of an IGBT according to an embodiment of the present invention.
Figure 2 is a sectional view of the main parts of a conventional IGBT, and Figure 3 (al.
~(fl is a cross-sectional view sequentially showing the manufacturing process of an IGBT according to an embodiment of the present invention, and FIG. 4 is a cross-sectional view showing another embodiment of the present invention. 1: P+ layer, 2: N- drain Region, 3: Channel layer,
31: P' connection layer, 32: P" collector layer, 4: N' source layer 5: gate insulating film, 6: gate electrode, 7: source electrode, 8 drain electrode. Figure 1 Figure 2 - ~ ~ 1 Figure 3 m Decoy Figure 4

Claims (1)

[Claims] 1) a first conductivity type semiconductor layer in contact with the drain electrode;
a drain region formed of a second conductivity type semiconductor layer provided thereon; a first conductivity type channel layer formed on a part of the surface of the drain region on the side opposite to the drain electrode side; and the channel layer. a source layer of a second conductivity type formed on the surface with a channel formation region left at the end; a gate electrode formed on the channel formation region with a gate insulating film interposed therebetween; In the device having a source electrode in contact with the channel layer, a layer of the first conductivity type having approximately the same extent as the channel layer is formed in the drain region under the channel layer, and the layer and the source electrode are in contact with each other. A gate-insulated bipolar transistor characterized in that the surface thereof is connected to a first conductivity type layer with a high impurity concentration.