JPH01229979A - Impedance measuring apparatus - Google Patents

Abstract

PURPOSE:To make it possible to perform highly accurate measurement, by adding a current whose phase and amplitude are adjusted at the joint side of an IV converter, offsetting a parasitic current, and effectively utilizing a dynamic range. CONSTITUTION:A sine wave having a phase corresponding to the output of a phase accumulator 22 is generated in a first sine wave generating means. The sine wave is supplied to a test specimen 34. The output current of the test specimen 34 is converted into a voltage in an IV converter 37. The converted output is detected in a vector detector 38. Phase adjusting data are added to the output of the accumulator 22 with a phase adjusting means 55. A sine wave having the phase corresponding to the output of the means 55 is generated in a second sine wave generating means. The amplitude of the output sine wave is adjusted in an amplitude adjusting means 61. The result is supplied to the converter 37 and added to the output of the material to be measured. The means 55 and the means 61 are adjusted, and a current corresponding to a parasitic current is generated. The parasitic current is offset with said current by subtraction in the input side of the converter 37. Only the current to be measured is converted into a voltage. The voltage can be supplied to the means 38, and the measuring accuracy is enhanced.

Description

DETAILED DESCRIPTION OF THE INVENTION "Field of Industrial Application" The present invention relates to an impedance measuring device that can expand the measurement dynamic range and measure impedance with high precision.

"Conventional technology" A conventional impedance measuring device is shown in FIG.

The square wave from the square wave oscillator 11 is transmitted to the low-pass 1p wave generator 12.
is passed through to become a sine wave, and the sine wave is passed through amplifier 1.
3 to the object to be measured 14.

The output current of the object to be measured 14 is converted into a voltage by a current-voltage converter 15, and the output voltage is synchronously detected by the output of the square wave oscillator 11 by a synchronous detection circuit 16. The synchronous detection output is integrated by an integrator 17, and the integrated output is converted into a digital signal by an AD converter 18 and displayed on a display 19.

When a parasitic capacitance 21 exists in the measurement circuit, conventionally, the output when the object to be measured 14 is not connected is measured, and this value is subtracted from the measurement result when the object to be measured 14 is connected. However, in this method, the dynamic range of the current-voltage converter 15, synchronous detection circuit 16, integrator 17, and AD converter 18 is limited, so there are limits to the measurement range and analysis accuracy of the impedance of the object to be measured. In other words, parasitic world ft21
When the current flowing through the device under test 14 is smaller than the parasitic current flowing through the current-voltage converter 15 and the synchronous detection circuit 16,
, the integrator 17, and the AD converter 18, the proportion of parasitic currents occupying each dynamic range increases, reducing measurement accuracy.

"Means for Solving the Problem" According to the present invention, a sine wave having a phase corresponding to the output of the phase accumulator is generated by the first sine wave generating means,
The sine wave is supplied to the object to be measured, the output current of the object to be measured is converted to voltage by an IV converter, and the converted output is vector-detected by vector detection means. The phase adjustment data is added to the output of the phase accumulator by the phase adjustment means, a sine wave having a phase corresponding to the output of the phase adjustment means is generated by the second sine wave generation means, and the amplitude of the output sine wave is The sine wave whose amplitude is adjusted by the interval adjustment means is supplied to the IV converter and added to the output of the object to be measured.

With such a configuration, the phase adjustment means and the amplitude adjustment means are adjusted to generate a current corresponding to the parasitic current, and this is subtracted and canceled from the parasitic current on the input side of the IV converter, so that only the current to be measured is generated. can be converted into a voltage and supplied to the vector detection means.

Embodiment In this invention, a phase accumulator 22 is provided. The phase accumulator 22 accumulates the given phase increment data and outputs it to the terminal 23, and also outputs the sum to the terminal 23 every time the internal accumulator overflows.
The output of the 0 oscillator 25, which outputs a pulse at 4, is frequency-divided by m by a variable frequency divider 26, and the frequency-divided output is supplied to the clock terminal of the phase accumulator 22.

The cumulative output of the phase accumulator 22 is supplied as an address to the sine wave memory 27, and the continuous output of the sine wave memory 27 is supplied to the latch circuit 2 using the output clock of the frequency divider 26.
8, and the output of the U-nochi circuit 28 is converted into an analog sine wave by the DA converter 29. That is, the DA converter 29 outputs a sine wave whose phase corresponds to the output of the phase accumulator 22. The low-pass portion of this sine wave is passed through a wave generator 31, further passed through an amplifier 32, and then switched and supplied to an object to be measured 34 and a reference resistance element 35 by a switch 33.

The output current of the object to be measured 34 and the output current of the reference resistance element 35 are switched by a switch 36 and supplied to an IV converter 37, where they are converted into a voltage. The output of the IV converter 37 is supplied to vector detection means 38 and subjected to vector detection.

For example, the output of the terminal 23 of the phase accumulator 22 is supplied as an address to a sine wave memory 39 and a cosine wave memory 41, respectively, and the readout outputs of these memories 39, 41 are latched by the output of the frequency divider 26 into launch circuits 42, 43. Ru. The outputs of the launch circuits 42 and 43 are respectively supplied to multiplication type DA converters 44 and 45, where the digital sine wave and cosine wave are multiplied by the output of the IV transformer 37 and converted into analog signals. .

The outputs of the multiplication type DA converters 44 and 45 are respectively supplied to integrators 48 and 49 through switches 46 and 47, and are integrated over an interval that is an integral multiple of the sine wave period. The output of the AD converter 52 is supplied to a controller (CPU) 53 and displayed on a display 54 as necessary.

The output of the terminal 23 of the phase accumulator 22 is supplied to a phase adjustment means (phase shift adder) 55 and added to the phase adjustment data. The output of the phase adjustment means 55 is supplied as an address to the sine wave memory 56, and the readout output of the sine wave memory 56 is latched by the latch circuit 57 by the output of the frequency divider 26. The output of the launch circuit 57 is converted into an analog signal by a DA converter 58, and the sine wave analog signal is supplied to the reference input of a multiplication type DA converter 61 constituting amplitude adjustment means through a low-pass t-waver 59. be done. Amplitude adjustment data is supplied to the digital input of the multiplication type DA converter 61, and the amplitude of the input sine wave analog signal is adjusted and output. This output is supplied to the input side of the IV converter 37 through an amplifier 62, a resistor 63, and a switch 64.

Output of amplifier 32, output of IV converter 37, amplifier 62
The outputs of are detected by the detection circuits 65, 66 and 67, respectively, and their levels are taken out, and these are sent to the selector switch 51.
The signal is supplied to the AD converter 52 through the A/D converter 52. Is the output pulse of the terminal 24 of the phase accumulator 22 in sequence? The output from the sequence controller 68 controls the switches 46 and 47 and the reset switches 71 and 72 of the integrators 48 and 49.
8.49, integration is performed over an interval that is an integral multiple of the sine wave period. Switches 33, 36, 51 .
64 is controlled, and amplitude adjustment data and phase adjustment data are also controlled.

The measurement procedures in various cases will be explained below. As shown in FIG. 2A, the object to be measured 34 is a capacitive element, and its capacitance C
8 is smaller than the parasitic capacitance Ct of the measurement system, the object to be measured 34 is removed and the switch 33.8 is opened.
36 to the M side, switch 64 is turned on, and integrator 4
The CPU 53 adjusts the phase adjustment data and amplitude adjustment data so that each output V, , V, of 8.49 becomes zero.

As a result, the current vector flowing through the parasitic capacitance Cf is canceled by the output current of the amplifier 62. Therefore, if the object to be measured 34 is connected in this state, only the current flowing through the object to be measured 34 will be converted into voltage by the IV converter 37.

As shown in Fig. 2B, when a parasitic conductance G is connected in parallel to the capacitance C to be evaluated, and G>>ωC (ω is the measurement angular frequency), switch 33 and 36 are set to the C side (reference resistance element 35 side) and turn on the switch 64.
The phase adjustment data and amplitude adjustment data are controlled by the CPU 53 so that the outputs V, , V, of the integrators 48, 49 are both adjusted to zero. In other words, a state in which the angle of the current vector is zero is detected. The phase adjustment data at this time is θ
. , the amplitude adjustment data is Ao.

Next, the switches 33 and 36 are set to the M side (device under test 34 side), and only the amplitude adjustment data A is adjusted by the CPII 53 so that the output (2) of the IV converter 37 becomes sufficiently small. In other words, the current due to the parasitic conductance G component is canceled by the output of the amplifier 62.

Each output V4+V of the integrator 48 and 49 observed at this time,
Therefore, C, , G can be found from the following equation.

■.

CX= Vl　・K　−R,・ω V+'R-・K　　　Z　rA　.

■1 is the output level of the amplifier 32, K is the detection/integral gain,
R1 is the resistance value of the feedback resistor 73 of the IV converter 37, Zl
is the resistance value of the reference resistance element 35. If A is adjusted to minimize {circle around (2)}, the output v4 of the integrator 48 will be almost zero, and Z, AO.

As shown in Fig. 2C, when the parasitic capacitance 1c and the conductance G to be evaluated are connected in parallel, and C8<<ωC, switch 33, 36 is set to the C side, switch 64 is turned on, and the phase adjustment data is output. The CPU 53 adjusts the amplitude adjustment data so that the integrator outputs Va and Vs become zero. In other words, find a state where the angle of the current vector is zero. The phase adjustment data at this time is θ. , the amplitude adjustment data is A. Switches 33 and 36 are set to the M side, and the phase adjustment data is set to θ. Set to +90 degrees. Only the amplitude adjustment data A is adjusted by the CPU 53 to make V sufficiently small.

In other words, the current flowing through the parasitic capacitance 1c is canceled by the output current of the amplifier 64, and from the V4 and VS observed at this time, C8-= ■ 1 ・ R1 ・ K Vl ・ R, ・ K ・ ω
Zr・ωA.

is found.

The number of bits of the phase accumulator 22 is In, the setting value of the phase increment data is n, and the frequency of the input pulse of the phase accumulator 22 is fs (f
lz), then the measured angular frequency ω is ω= −・2πft
(rad/5ec)2m, and by changing nl, the measured angular frequency ω can be changed.9 The number of bits of the phase adjustment data is 02, and the number of bits of the phase adjustment means (phase shift adder) 55 is r. Then, the phase shift θ becomes θ−X 360 (deg) r, and the phase can be adjusted with high resolution and high accuracy.

As shown in FIG. 3, the amplitude value of the current addition vector may be controlled by analog feedback. In other words, the coefficient of voltage conversion is controlled by the output of the detection circuit 66 so that the output is minimized.

"Effects of the Invention" As described above, according to the present invention, the parasitic current is canceled by adding the phase-adjusted and amplitude-adjusted currents on the input side of the IV converter 37. Vessel 3
7. Only the current to be measured is supplied to the vector detection means 38, etc., and its Guinami no clean range can be effectively utilized, allowing highly accurate measurement.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an example of an impedance measuring device according to the present invention, FIG. 2 is a diagram showing various objects to be measured,
FIG. 3 is a block diagram showing a partial modification of the present invention, and FIG.
The figure is a block diagram showing a conventional impedance measuring device.

Claims (1)

[Claims] (1) a phase accumulator; a first sine wave generating means for generating a sine wave with a phase corresponding to the output of the phase accumulator and applying it to the object to be measured; and converting the output current of the object to be measured into a voltage; an IV converter, a vector detection means for vector detection of the output of the IV converter, a phase adjustment means for adding phase adjustment data to the output of the phase accumulator, and a sine whose phase corresponds to the output of the phase adjustment means. a second sine wave generation means for generating a wave; an amplitude adjustment means for adjusting the amplitude of the output sine wave current of the second sine wave generation means with amplitude adjustment data; and an output of the amplitude adjustment means to the IV converter. an impedance measuring device comprising an adding means for supplying the output and adding it to the output of the object to be measured.