JPH01228192A - Hybrid integrated circuit device - Google Patents
Hybrid integrated circuit deviceInfo
- Publication number
- JPH01228192A JPH01228192A JP5359388A JP5359388A JPH01228192A JP H01228192 A JPH01228192 A JP H01228192A JP 5359388 A JP5359388 A JP 5359388A JP 5359388 A JP5359388 A JP 5359388A JP H01228192 A JPH01228192 A JP H01228192A
- Authority
- JP
- Japan
- Prior art keywords
- conductor circuit
- conductor
- board
- circuit
- circuit board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004020 conductor Substances 0.000 claims abstract description 43
- 239000002184 metal Substances 0.000 claims abstract description 8
- 229910052751 metal Inorganic materials 0.000 claims abstract description 8
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 abstract description 5
- 239000010931 gold Substances 0.000 abstract description 5
- 229910052737 gold Inorganic materials 0.000 abstract description 5
- 238000007747 plating Methods 0.000 abstract description 4
- 238000000034 method Methods 0.000 abstract description 3
- 230000003247 decreasing effect Effects 0.000 abstract 1
- 230000002950 deficient Effects 0.000 abstract 1
- 239000000853 adhesive Substances 0.000 description 4
- 230000001070 adhesive effect Effects 0.000 description 4
- 239000000758 substrate Substances 0.000 description 3
- 230000007547 defect Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 239000012778 molding material Substances 0.000 description 2
- 229920003002 synthetic resin Polymers 0.000 description 2
- 239000000057 synthetic resin Substances 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000001721 transfer moulding Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は混成集積回路装置に関し、特にリードフレーム
に回路基板を搭載した構成の混成集積回路装置に関する
。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a hybrid integrated circuit device, and particularly to a hybrid integrated circuit device having a structure in which a circuit board is mounted on a lead frame.
従来、この種の混成集積回路装置は、第２図に示すよう
に、金属製リードフレームｌに回路基板３を接着剤２で
貼り付け、シリコン基板に形成した能動素子５や受動素
子６等を導体ペースト７により回路基板３上に搭載し、
これらの素子９回路基板及びリードフレーム間を金属細
線８で電気接続し、かつ合成樹脂等のモールド材１１で
パッケージ封止する構成となっている。Conventionally, this type of hybrid integrated circuit device, as shown in FIG. 2, has a circuit board 3 attached to a metal lead frame l using an adhesive 2, and active elements 5, passive elements 6, etc. formed on a silicon substrate. Mounted on the circuit board 3 with conductor paste 7,
The circuit board of these elements 9 and the lead frame are electrically connected by thin metal wires 8, and the package is sealed with a molding material 11 such as synthetic resin.
この場合、装置の高密度化、高機能化に応えるために、
回路基板３は絶縁基板３ａの表面及び裏面に夫々導体回
路４ａ、４ｂを形成し、これらをスルーホール４ｃを通
して相互に接続した構成とされている。In this case, in order to meet the demands for higher density and higher functionality of equipment,
The circuit board 3 has conductor circuits 4a and 4b formed on the front and back surfaces of an insulating substrate 3a, respectively, and these are interconnected through through holes 4c.
〔発明が解決しようとする課題］
上述した従来の混成集積回路装置は、リードフレーム１
上に接着固定する回路基板３は、その裏面に導体回路４
ｂが形成されるために裏面が凹凸となり、回路基板３を
リードフレーム１に固定する際の安定性が得られず、装
置のボンディング不良が生じるという問題がある。また
、回路基板３の裏面の導体回路に対しても表面の導体回
路と同様に金メツキを行う必要があるために、コストの
増大を招くという問題もある。[Problems to be Solved by the Invention] The conventional hybrid integrated circuit device described above has a lead frame 1
The circuit board 3 to be adhesively fixed on the top has a conductor circuit 4 on its back side.
Due to the formation of ridges b, the back surface becomes uneven, and stability is not achieved when fixing the circuit board 3 to the lead frame 1, resulting in a problem of bonding failure of the device. Furthermore, since it is necessary to gold plate the conductor circuits on the back side of the circuit board 3 in the same way as the conductor circuits on the front side, there is also the problem of increased costs.
本発明はボンディング不良を改善するとともに低コスト
に製造可能な混成集積回路装置を提供することを目的と
している。SUMMARY OF THE INVENTION An object of the present invention is to provide a hybrid integrated circuit device that can improve bonding defects and can be manufactured at low cost.
（課題を解決するための手段〕
本発明の混成集積回路装置は、絶縁板の表面にのみ導体
回路を形成した回路基板をリードフレームのアイランド
に搭載し、この回路基板には能動素子、受動素子ととも
に表面に所要の導体回路を形成した導体回路チップを固
着し、リードフレーム、導体回路、各素子、及び導体回
路チップを金属細線で相互に電気接続してモールド封止
した構成としている。(Means for Solving the Problems) The hybrid integrated circuit device of the present invention has a circuit board on which a conductor circuit is formed only on the surface of an insulating plate mounted on an island of a lead frame, and this circuit board has active elements and passive elements. At the same time, a conductor circuit chip with a required conductor circuit formed on its surface is fixed, and the lead frame, the conductor circuit, each element, and the conductor circuit chip are electrically connected to each other with thin metal wires and sealed in a mold.
〔作用］
上述した構成では、リードフレームに搭載する回路基板
は裏面に導体回路を設けていないので、裏面の平坦化を
図ってボンディングを改善し、かつ裏面の導体回路に対
する金メツキを不要にして低コスト化を可能とする。[Function] In the above configuration, since the circuit board mounted on the lead frame does not have a conductor circuit on the back side, the back side is flattened to improve bonding, and gold plating on the back side conductor circuit is not required. Enables cost reduction.
次に、本発明を図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図は本発明の一実施例の断面図である。図において
、金属製リードフレームｌは外部接続端子としてのリー
ド部と、素子類を搭載するアイランド部を備えており、
このアイランド部に接着剤２を用いて回路基板３を接着
固定している。この回路基板３は表面にのみ導体回路４
を形成し、裏面には形成していない。そして、この回路
基板３の上には能動素子５や受動素子６を夫々導体ペー
スト７により固着し、金属細線８により、これらの素子
５，６．導体回路４．リードフレームｌを相互接続して
いる。FIG. 1 is a sectional view of an embodiment of the present invention. In the figure, a metal lead frame l has a lead part as an external connection terminal and an island part on which elements are mounted.
A circuit board 3 is adhesively fixed to this island portion using an adhesive 2. This circuit board 3 has a conductor circuit 4 only on the surface.
, but not on the back side. Then, on this circuit board 3, an active element 5 and a passive element 6 are respectively fixed with a conductive paste 7, and these elements 5, 6, . Conductor circuit 4. The lead frames l are interconnected.
また、前記回路基板３には、絶縁板の表面に所要の導体
回路を形成した導体回路チップ９を絶Ｘ（ペースト１０
により接着している。この導体回路チップ９は、特に前
記前記導体回路４と交差する箇所に配設される。そして
、この導体回路チップ９に対して前記素子５．６や導体
回路４を金属細線８で接続し、複雑な回路を構成してい
る。Further, on the circuit board 3, a conductor circuit chip 9 with a required conductor circuit formed on the surface of the insulating plate is removed (paste 10
It is adhered by. This conductor circuit chip 9 is disposed particularly at a location where it intersects with the conductor circuit 4. The element 5.6 and the conductor circuit 4 are connected to this conductor circuit chip 9 with thin metal wires 8 to form a complex circuit.
以上のように形成された構体は、そのリードフレーム１
の周囲の端子部を残してトランスファーモールド方式に
よって合成樹脂等のモールド材１１によりパッケージ封
止する。また、モールド後にリードフレームのフレーム
を切除することは言うまでもない。The structure formed as described above has its lead frame 1
The package is sealed with a molding material 11 made of synthetic resin or the like by a transfer molding method, leaving the terminal portions around the periphery. Furthermore, it goes without saying that the frame of the lead frame is cut out after molding.
この構成によれば、回路基ｖｉ３における導体回路の交
差部は、導体回路子ツブ９を利用して交差配線を行うこ
とができる。このため、回路基板３の裏面に導体回路を
形成する必要はなく、回路基板３の裏面における凹凸を
未然に防止でき、良好なボンディングを実現する。また
、この裏面の導体回路に対する金メツキを施す必要はな
く、低コスト化を達成できる。According to this configuration, the conductor circuit tabs 9 can be used to perform cross wiring at the intersections of the conductor circuits in the circuit board vi3. Therefore, there is no need to form a conductor circuit on the back surface of the circuit board 3, and unevenness on the back surface of the circuit board 3 can be prevented, thereby achieving good bonding. Further, there is no need to apply gold plating to the conductor circuit on the back surface, and cost reduction can be achieved.
以上説明したように本発明は、リードフレームに搭載す
る回路基板は表面に固着した導体回路チップにより交差
配線等の複雑な配線を可能としているので、その裏面に
導体回路を設ける必要はなく、裏面の平坦化を図って安
定な接着固定を可能としてボンディング不良を解消でき
、かつ裏面の導体回路に対する金メツキを不要にして回
路基板の加工費及び資材費を低減し、低コスト化が達成
できる。As explained above, in the present invention, the circuit board mounted on the lead frame allows complex wiring such as cross wiring by the conductor circuit chip fixed to the front surface, so there is no need to provide a conductor circuit on the back side. By flattening the surface of the substrate, stable adhesive fixation can be achieved, thereby eliminating bonding defects, and eliminating the need for gold plating on the conductor circuits on the back side, thereby reducing the processing and material costs of the circuit board, thereby achieving cost reduction.
第１図は本発明の一実施例の断面図、第２図は従来構造
の断面図である。
１・・・リードフレーム、２・・・接着剤、３・・・回
路基板、４．４ａ、４ｂ・・・導体回路、４Ｃ・・・ス
ルーホール、５・・・能動素子、６・・・受動素子、７
・・・導体ペースト、８・・・金属細線、９・・・導体
回路チップ、１０・・・絶縁ペースト、１１・・・モー
ルド材。FIG. 1 is a sectional view of an embodiment of the present invention, and FIG. 2 is a sectional view of a conventional structure. DESCRIPTION OF SYMBOLS 1... Lead frame, 2... Adhesive, 3... Circuit board, 4.4a, 4b... Conductor circuit, 4C... Through hole, 5... Active element, 6... Passive element, 7
... Conductor paste, 8... Metal thin wire, 9... Conductor circuit chip, 10... Insulating paste, 11... Mold material.
Claims (1)
リードフレームのアイランドに搭載し、この回路基板に
は能動素子、受動素子とともに表面に所要の導体回路を
形成した導体回路チップを固着し、前記リードフレーム
、導体回路、各素子、及び導体回路チップを金属細線で
相互に電気接続してモールド封止したことを特徴とする
混成集積回路装置。1. A circuit board with a conductor circuit formed only on the surface of the insulating plate is mounted on the island of the lead frame, and a conductor circuit chip with the required conductor circuit formed on the surface is fixed to this circuit board along with active elements and passive elements. . A hybrid integrated circuit device, characterized in that the lead frame, the conductor circuit, each element, and the conductor circuit chip are electrically connected to each other by thin metal wires and sealed with a mold.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5359388A JPH01228192A (en) | 1988-03-09 | 1988-03-09 | Hybrid integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5359388A JPH01228192A (en) | 1988-03-09 | 1988-03-09 | Hybrid integrated circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01228192A true JPH01228192A (en) | 1989-09-12 |
Family
ID=12947176
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5359388A Pending JPH01228192A (en) | 1988-03-09 | 1988-03-09 | Hybrid integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01228192A (en) |
-
1988
- 1988-03-09 JP JP5359388A patent/JPH01228192A/en active Pending
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