JPH01212179A - Device for generating title picture - Google Patents

Abstract

PURPOSE:To reduce a circuit scale by reading three picture data, whose timings are dislocated only by a prescribed horizontal synchronizing period, from a memory means with three memory control means and overlapping these picture data. CONSTITUTION:The picture data stored in a memory means 13 are read by three memory control means 43-45, whole reading timings are different only by the prescribed horizontal synchronizing period and the respective picture data, which are read by these memory means 43-45, are overlapped. Accordingly, a vertical framing picture signal is obtained. Namely, since the three picture data, which have delay quantity only by the prescribed horizontal synchronizing period, are read from the memory means 13, it is not necessary to use a delay circuit which has the large delay quantity. In comparison with a conventional title picture generating device to need the delay circuit which has the several times of delay quantity (UTh, DTh) of one horizontal synchronizing period (1H), the circuit scale can be made small.

Description

[Detailed description of the invention] The present invention will be explained in the following order.

A. Industrial application field B3 Summary of the invention C9 Prior art 1 Problems to be solved by the invention 89 Means for solving the problems 24 Effects G. Examples (G 1-1) Camera to which the present invention is applied Integrated 8mm
VTR configuration (Figures 2 and 3) (Gl-2) Titler circuit configuration (Figures 1, 4, and 5) (Gl-3) Titler circuit operation (Gl-3-1> Registration operation (Fig. 1, Fig. 6, Fig. 7) (Gl-3-2) Insertion operation (Fig. 1, Fig. 4, Fig. 5, Fig. 8 to Fig. 13) (G2
) Application Example H0 Effects of the Invention A, Industrial Application Field The present invention relates to a title image generation device for forming a title image signal to be inserted into a video signal, and more particularly to a title image generation device used in so-called titlers, captioners, and the like.

B9 Summary of the Invention The present invention provides a title image generation device that stores a plurality of image data formed by digitizing an input video signal in a memory means, and forms a title image signal from the image data read out from the memory means. , three image data whose timings are shifted by a predetermined period that is an integral multiple of the horizontal synchronization period are read out from the memory means by the three memory control means, and by superimposing these image data, a vertical border image signal can be formed. This is what I did.

Further, the present invention forms a right border image signal and a left border image signal using two delay circuits, and superimposes these right border image signals and left border image signals on the vertical border image signal. It is designed to be able to form image signals.

C1 Prior Art Conventionally, there has been a title image generating device such as a so-called titler or telopper that forms a title image signal such as title information or subtitle information according to the content of an image to be reproduced from a video signal and inserts it into the video signal. It is known as a peripheral device for video tape recorders (VTRs).

Furthermore, as a camera-integrated VTR incorporating the above-described title image generating device, one proposed in the specification and drawings of Japanese Patent Application No. 62-094682 is known. That is, this camera-integrated VTR includes an imaging unit that photographs a subject image, and a recording unit that records a video signal formed from the imaging output obtained by the imaging unit, and the image captured by the imaging unit. The device includes a title image generation device that writes image data obtained by digitizing the video signal of 1 to a memory, forms a title image signal from the image data read from the memory, and inserts the generated title image signal into the video signal.

Furthermore, a video signal processing circuit as shown in FIG. 14 is generally known, which delays a video signal to form a vertically bordered image signal.

That is, the video signal processing circuit includes two delay circuits 131, 132, and two NOT circuits 133, 134, 2.
Two NOR circuits 135, 136. One OR circuit 137
The video signal a supplied to the signal input terminal 138 is supplied to the second delay circuit 132 via the first delay circuit 131.

Each of the delay circuits has a delay amount (UTh) corresponding to a predetermined period that is an integral multiple of the horizontal synchronization period based on a clock pulse supplied via the clock input terminal 139.

DTh) is applied to each input signal.

Here, image 1 shown in FIG. 15 is used as the video signal a.
50 in the central vertical direction (α-β) is supplied to the signal input terminal 138.
The delay circuit 131 converts the video signal a into the delay amount U.
The second delay circuit 132 outputs the video signal S delayed by Th, and the second delay circuit 132 outputs the video signal S delayed by the delay amount DT.
A video signal C delayed by h is output.

The video signal a is supplied to one input terminal of the NOR circuit 135 via the N07 circuit 133. Further, the video signal C is supplied to one input terminal of the NOR circuit 136 via the N07 circuit 134. Further, the video signal is connected to each of the NOR circuits 135, 1
36 and is also supplied to the first signal output terminal 140.

The NOR circuit 135 generates an upper edge signal d of the video signal from each input signal, and the OR circuit 135 generates an upper edge signal d of the video signal.
37.

Further, the NOR circuit 136 generates a lower edge signal e of the video signal from each of the input signals, and
The other input terminal of the circuit 137 is supplied. These edge signals d and e are converted into a vertical edge signal r by the OR circuit I37.
and is supplied to the second signal output terminal 141.

Therefore, this video signal processing circuit outputs a video signal that becomes an image 151 shown in FIG. 15 from the first signal output terminal 140, and superimposes images 152 and 153 from the second signal output terminal 141. A vertical edging signal f that becomes the combined image is output. By adding the vertical border signal f to this video signal, a video signal that becomes the image 154 can be generated.

D1 Problem to be Solved by the Invention By the way, in the title image generation device built into the above-mentioned camera-integrated VTR, in order to realize a variety of title images, a title image generation device built in the above-mentioned camera-integrated VTR generates a title from image data written in the above-mentioned memory. It has been considered that an image signal for a title image having a border image is formed by adding a border signal in the vertical direction, horizontal direction, or all around the image signal to the image signal.

However, when attempting to form a vertically bordered image signal using the above video signal processing circuit, delay circuits 131 and 132 having delay amounts (UTh, DTh) corresponding to a predetermined period that is an integral multiple of the horizontal synchronization period are required. Therefore, the circuit scale becomes extremely large, making it difficult to implement.

SUMMARY OF THE INVENTION In view of the above-mentioned problems, the present invention provides a title image generation device having a novel configuration with a small circuit scale, which is capable of forming a vertically bordered image signal, and which is capable of forming a vertically bordered image signal. An object of the present invention is to provide a title image generating device with a novel configuration that can generate vertical and horizontal border image signals and can realize a variety of title images.

88 Means for Solving the Problems In order to solve the above-mentioned problems, the present invention provides means for digitizing an input video signal to form image data, memory means for storing the image data, and the memory means. a first memory control means for reading image data from the memory means; and a second memory for reading image data from the memory means at a timing that is a predetermined period that is an integral multiple of a horizontal synchronization period after the read timing of the first memory control means. a control means; a third memory control means for reading out the image data from the memory means at a timing delayed by a predetermined period that is an integral multiple of a horizontal synchronization period from the read timing of the first memory control means; and the second memory. an image signal of an upper border image obtained by removing an image overlapped with an image based on the image data read out under the control W of the first memory control means from an image based on the image data read out under the control of the control means; an image signal of a lower border image obtained by removing an image overlapping with an image based on the image data read out under the control of the first memory control means from an image based on the image data read out under the control of the memory control means; and means for forming a superimposed vertical border image signal from each of the above image data.

In addition to the above-mentioned means, the present invention also provides an addition circuit that generates an image signal by superimposing the vertical border image signal on the image data read out under the control of the first memory control means; a first delay circuit that provides a predetermined amount of delay to the output image signal of the addition circuit; a second delay circuit that provides a predetermined amount of delay to the output image signal of the first delay circuit;
A left-side border image signal obtained by removing an image overlapping with an image generated by the output image signal of the first delay circuit from the image generated by the output image signal of the addition circuit, and the first image signal from the image generated by the output image signal of the second delay circuit. means for forming a right side border image signal excluding an image overlapping with the image outputted from the output image signal of the delay circuit; and a vertical and horizontal border image obtained by superimposing the vertical border image signal, the left side border image signal, and the right side border image signal. It consists of an adder circuit that generates a signal.

F1 action In the title image generation device according to the present invention, the image data stored in the memory means is read out by three memory control means having different readout timings for a predetermined period that is an integral multiple of the horizontal synchronization period, and these memory control means Each read image data is superimposed to form a vertical border image signal. Further, in the title image generation device according to the present invention,
A right side border image signal and a left side border image signal are formed from the output image signals of the two delay circuits, and are superimposed on the vertical border image signal to generate vertical and horizontal border signals.

G. Examples Examples of the present invention will now be described in detail with reference to the drawings.

(G 1-1) 8 mm integrated camera to which the present invention is applied
Configuration of VTR (Figures 2 and 3) Figures 2 and 3 show the imaging unit 10 that captures the subject image.
and a recording section 20 for recording the video signal obtained by the imaging section 10 in a predetermined format of 8-kaku video are integrally provided in the main body 30 of the NTSC camera with a built-in title image generating device. This shows a VTR.

As shown in the external perspective view of FIG. 3, the apparatus main body 30 is provided with an imaging lens 35 that guides the most imaged light to the solid-state imager 1 of the imaging section 10. An electronic viewfinder 25 and various operation switches 31, 3 for monitoring the image of the subject etc.
2, 33, 34, etc. are provided.

Further, as shown in the block diagram of FIG. It is driven by a CCD drive circuit 3 that operates based on a synchronization signal, and supplies an imaging output of a subject image obtained by the solid-state imager 1 to an imaging signal processing circuit 4.

The imaging signal processing circuit 4 forms a luminance signal (Y) and color difference signals (RY) and (B-Y) representing a subject image from the imaging output from the solid-state imager 1. A luminance signal (Y) and a color difference signal (R
-Y) and (B-Y) are impose circuits 5 and 6, respectively.
．． 7 to an NTSC encoder 8.

The NTSC encoder 8 generates an NTSC encoder that indicates a subject image from the luminance signal (Y), color difference signals (RY), and (B-Y).
Forms a video signal for the SC side. This video signal is
1-bit analog-to-digital (A/D) conversion circuit 11
and the electronic viewfinder 25.
and the recording section 20.

The 1-bit A/D conversion circuit 11 is constituted by a level converter that compares the luminance signal (Y) of the video signal with a predetermined signal level, and the level of the luminance signal (Y) is set to the predetermined signal level. When it is smaller than the level, image data shown as rlJ is formed, and when it is larger, image data shown as "0" is formed. This image data is written into the memory 13 via the titler circuit 12.

The memory 13 is composed of a static RAM that stores the image data, and is supplied with backup power from the lithium battery 4 so that the data will not be lost even if the main power is cut off. There is.

The titler circuit 12 is supplied with a synchronizing signal from the synchronizing signal generating circuit 2, forms write/read address data for the memory 13 from this synchronizing signal, and controls writing/reading of image data to/from the memory 13. conduct. The titler circuit 12 also supplies the three primary color signals (R, G, B) that form the title image to the conversion circuit 15, and also supplies the image data read from the memory 13 and the operation switch 33 and the operation switch 3.
In response to the operation 4, the operations of the respective impose circuits 5, 6, and 7 are controlled.

The conversion circuit 15 converts the three primary color signals (R, G, B) supplied from the titler circuit 12 into a luminance signal (Y) and color difference signals (RY) and (B-Y), The signal is supplied to each impose circuit 5, 6.7.

These impose circuits 5, 6.7 are operated by the luminance signal (Y), color difference signal (RY), (B-) supplied from the conversion circuit 15 under the operation control of the titler circuit 12.
Y) is inserted into the output signal of the imaging signal processing circuit 4.

(G1-2) Configuration of titler circuit (Figure 1, Figure 4, Figure 5) FIG. 1 shows the configuration of the titleer circuit 12.

In FIG. 1, the titler circuit 12 is provided with an image data switching circuit 42 connected to an image data input terminal 41 via a serial/parallel conversion circuit 40.

The image data switching circuit 42 is formed of a parallel data switching circuit, and includes the serial/parallel conversion circuit 40 and three data acquisition circuits 43, 44, and 45.
to the memory I via the image data input/output terminal group 46.
It is designed to selectively connect to 3.

Each of the data acquisition circuits 43, 44, 45 is configured to acquire parallel data supplied to each input terminal at a predetermined timing, and each output terminal thereof is connected to each parallel/serial conversion circuit 47, 48, 49. It is connected to the latch circuit 50 via.

The latch circuit 50 has three output terminals corresponding to the respective parallel-to-serial conversion circuits 47, 48° 49 connected to the input terminals, which are connected to a vertical border generation circuit 51, and a timing pulse input terminal. A predetermined timing pulse is supplied from the timing generation circuit 52.

Two output ends of the vertical border generation circuit 51 are connected to the horizontal border generation circuit 63. Further, this horizontal border generation circuit 63 has one output end connected to a color designation circuit 79 and the other output end connected to a color designation circuit 80 .

Here, the vertical border generation circuit 51 is composed of two NOT circuits 53, 54, two NOR circuits 55, 56, and one OR circuit 57, as shown in FIG.

Among these, the input terminal 58 connected to the output terminal of the latch circuit 50 corresponding to the parallel-serial conversion circuit 47 is connected to one input terminal of the NOR circuit 55 via the N07 circuit 53. There is. Further, an input terminal 60 connected to the output end of the latch circuit 50 corresponding to the parallel-serial conversion circuit 49 is connected to one input end of the NOR circuit 56 via the N07 circuit 54. . Further, an input terminal 59 connected to the output terminal of the latch circuit 50 corresponding to the parallel-serial conversion circuit 48 is connected to each NOR circuit l85.
5 and 56, and the first
is connected to the output terminal 61 of. Furthermore, each NO above
The output terminals of the R circuits 55 and 56 are connected to each input terminal of the OR circuit 57, and the output terminal of this OR circuit 57 is connected to the second
is connected to the output terminal 62 of.

Further, as shown in FIG. 5, the horizontal border generation circuit 63 includes an OR circuit 64, four delay circuits 65°, 66.67.
68. Two NOT circuits 69, 70. Two NOROR
It is composed of a circuit 572 and a three-man OR circuit 73.

Among these, the OR circuit 64 is connected to the input terminal 7 to which the first output terminal 61 of the vertical border generation circuit 51 is connected.
4 and an input terminal 75 to which the second output terminal 62 is connected are connected to each input terminal. In addition, the first
The input terminal of the delay circuit 65 is connected to the input terminal 74. Further, the input terminal of the second delay circuit 66 is connected to the output terminal of the OR circuit 64. This second
The output terminal of the delay circuit 66 is connected to the input terminal of the third delay circuit 67, and the output terminal of the delay circuit 66 is connected to the input terminal of the third delay circuit 67.
1.72. Further, the input terminal of the fourth delay circuit 68 is connected to the input terminal 75. Each of these delay circuits 65, 66, 67, 6
8 is configured such that a predetermined clock pulse is supplied through a clock input terminal 76, and a predetermined amount of delay is given to the input data based on this clock pulse.

Furthermore, in this horizontal bordering circuit 63, the above-mentioned 02 circuit 64
The output terminal of the NOR circuit 71 is connected to the other input terminal of the NOR circuit 71 via the N07 circuit 69. In addition, the third
The output terminal of the delay circuit 67 is connected to the other input terminal of the NOR circuit 72 via the N07 circuit 70.

Further, each output terminal of each of the NOR circuits 71 and 72 and the output terminal of the fourth delay circuit 68 are connected to the three-man powered OR circuit 7.
Connected to 3. Furthermore, this horizontal bordering circuit 6
3, the output terminal of the first delay circuit 65 is connected to the output terminal 7.
The output terminal of the OR circuit 73 is connected to the color specifying circuit 80 via the output terminal 7.

Each of the color designation circuits 79 and 80 is connected to a color designation input terminal connected to a system controller (not shown) to which a third operation switch 33 and a fourth operation switch 34 provided in the device main body 30 are connected. 81 and 82 are connected, and color designation data is supplied through these color designation input terminals 81 and 82, respectively. In each of the color designation circuits 79 and 80, each output terminal of the three primary color signals (R, G, B) designated by the color designation data is connected to the superimposition circuit 83, respectively.

The superposition circuit 83 gives priority to the three primary color signals (R, G, B) supplied from the color designation circuit 79 and outputs the three primary color signals (R, G, B) supplied from the color designation circuit 80.
) superimposed on the three primary color signals (R.

G, B), and these three primary color signals (R, G.

B) is outputted through each output terminal 84R, 84G, and 84B. In addition, the superposition circuit 83
Three primary color signals (R, G.

B) is supplied to the blanking signal generation circuit 104. This blanking signal generation circuit 104 generates a blanking signal (BLK) from the three primary color signals (R, G, B), and outputs the blanking signal (BLK) from the three primary color signals (R, G, B) to each of the impose circuits 5 and 6 through the blanking signal output terminal 105. It is designed to be supplied as an operation control signal.

The titler circuit 12 is also provided with an address data switching circuit 85 for switching the parallel address data provided to the memory 13. This address data switching circuit 85 selects a write address generation circuit 86 formed by a counter of a predetermined bit and an output terminal of a successive address switching circuit 87 to the memory 13 via an address data output terminal group 88. Connect to.

The successive address switching circuit 87 is formed by a parallel data switching circuit, and is formed by a predetermined bit counter using a control signal supplied from a switching timing generation circuit 89 connected to a control signal input terminal. Two successive address generation circuits 90, 91, and 92 are selectively connected to the address data switching circuit 85.

The titler circuit 12 is also provided with a write timing generation circuit 93 that generates write instruction data and a successive timing generation circuit 94 that generates successive instruction data. The write timing generation circuit 93 is connected to a registration operation instruction terminal 95 to which a first operation switch 31 disposed on the device main body 30 is connected, and via a write instruction terminal 96. It is connected to memory 13. Further, the successive timing generation circuit 94 is connected to an insertion operation instruction terminal 97 to which the second operation switch 32 provided on the device main body 30 is connected, and also is connected to the insertion operation instruction terminal 97 via the successive output instruction terminal 98. It is connected to memory 13.

Further, the titler circuit 12 is supplied with a clock input terminal 99 to which a predetermined clock pulse is supplied from a clock generation circuit (not shown), and each synchronization signal is supplied from the synchronization signal generation circuit 2. Horizontal synchronization input terminal 100 and vertical synchronization input terminal 101
is provided, and an input terminal 102 of the drive power source is provided.
A ground terminal 103 and the like are provided.

(Gl-3) Operation of the titler circuit The titler circuit 12 receives clock pulses and clock pulses supplied to the clock input terminal 99 by operating each operation switch 31, 32, 33° 34 provided on the device main body 30. Each circuit constituting this titler circuit 12 is operated based on the synchronization signal supplied to each of the synchronization input terminals 100 and 101, and the registration operation and insertion operation described below are performed.

(C1-3-1) Registration operation (Fig. 1, Fig. 6, Fig. 7)
The first operation switch 3I is an operation designation switch for registration operation.

When the first operation switch 31 is operated while photographing an image 111 as shown in FIG.
connects the serial/parallel conversion circuit 40 and the memory 13 via the image data switching circuit 42, and connects the write address generation circuit 86 and the memory 13 via the address data switching circuit 85. ,
Furthermore, the write timing generation circuit 93 is operated.

At this time, the serial/parallel conversion circuit 40 converts image data of the image 111 being photographed by the imaging section 10, which is supplied from the A/D conversion circuit 11 via the image data input terminal 41, into parallel data. The data is converted into image data a and supplied to the memory 13 at a predetermined timing as shown by A in FIG. Further, the write address generation circuit 86 generates write address data b for the image data a, and stores it in the memory 13 at the same timing as the image data a, as shown by B in FIG. supply In addition, the write timing generation circuit 9
3 generates write instruction data C at a timing corresponding to the write data b, as shown by C in FIG. 7, and supplies it to the memory 13.

Therefore, the image data a is written into the memory 13 at the memory address specified by the write address data b at the timing of the write instruction data C.

It goes without saying that the image data written in the memory 13 may be formed by capturing an image of a landscape, a person's face, etc., in addition to the characters and illustrations drawn on the panel.

(Gl-3-2) Insertion operation (FIGS. 1, 4, 5, and 8 to 13) The second operation switch 32 is an operation designation switch for the insertion operation.

When the titler circuit 12 accepts the operation of the operation switch 32, the titler circuit 12 connects each data acquisition circuit 843.44.45 to the memory 13 via the image data switching circuit 42, and also switches the address data. The successive address switching circuit 87 and the memory 13 are connected through a circuit 85, and the successive timing generation circuit 94 is operated.

In addition, in the titler circuit 12, in this insertion operation, the second successive address generation circuit 91 generates normal address data, and the first successive address generation circuit 90 horizontally synchronizes the normal address data. The third successive address generation circuit 92 generates advance address data advanced by a predetermined period (UTh) that is an integral multiple of the period.
is designed to generate delayed address data that is delayed by a predetermined period (DTh) that is an integral multiple of the horizontal synchronization period. Each address data generated by these successive address generation circuits 90, 91, and 92 is divided into advanced address data, normal address data, and delayed address by switching connection of the successive address switching circuit 87 under the control of the switching timing generation circuit 89. The three address data with the data are one data period (IDT) of the above write address data b.
), and is supplied to the memory 13 via the address data switching circuit 85 as successive address data d shown at A in FIG.

Further, the successive timing generation circuit 94 is shown in FIG.
As shown in , successive instruction data e is generated at a timing corresponding to each data of the successive address data d, and is supplied to the memory 13.

Therefore, from the memory address of the memory 13 specified by the successive address data d, the advance image data read out with the advance address data, the normal image data read out with the normal address data, and the Image data f shown by C in FIG. 8, in which the delayed image data read out using the delayed address data are sequentially arranged, is read out at the timing of the read instruction data e. This image data f is supplied to each of the data acquisition circuits 43, 44, and 45.

The data capture circuit 43 advances as shown by D in FIG. 8 and captures the image data at the timing when the image data is provided, and advances as shown by E in FIG. Parallel/serial conversion circuit 47
The signal is supplied to the latch circuit 50 via the latch circuit 50.

Further, the data capture circuit 44 captures the image data at the timing when the normal image data is provided as shown by F in FIG. 8, and receives the normal image data j as shown by G in FIG. is always supplied to the latch circuit 50 via the parallel-to-serial conversion circuit 48.

Furthermore, the data capture circuit 45 captures the image data at the timing when the delayed image data is provided, as shown in [■] in FIG. ! is always supplied to the latch circuit 50 via the parallel-to-serial conversion circuit 49.

The latch circuit 50 transfers the supplied image data h, j, i to the latch timing generation circuit 5.
The image data n, o, o, which are synchronized with each other in timing are latched at the timing of the timing pulse m shown at J in FIG. Generate p. Note that in FIG. 8, the timing pulse m supplied to the latch circuit 50 and the output image data n, o, p are treated as the image data h, j, l as parallel data. However, the latch circuit 50 outputs serial image data whose timings are synchronized with each other.

Here, the image data 0 is the normal image 1 shown in FIG.
12, the image has the same timing as the image 111. Further, the image data n is the image 1 shown in FIG.
13, the advanced image 11 is shifted upward from the image 112 by a predetermined period (UTh) that is an integral multiple of the horizontal synchronization period.
It becomes 3. Further, the image data p becomes a delayed image 114 that is shifted downward from the image 112 by a predetermined period (DTh) that is an integral multiple of the horizontal synchronization period, as shown in the image 114 shown in FIG. These image data n, o, and p are supplied to respective input terminals 58, 59, and 60 of the vertical border circuit 51.

Here, FIG. 10 is a waveform diagram for explaining signal processing of the vertical border circuit 51. In this FIG. 10, waveforms n, o, p are the image data n'-n
, o, p, each image 113 shown in FIG.
112 and 114, respectively, show waveforms in the vertical direction (α-β) at the center.

In the vertical border circuit 51, the NOR circuit 55
is the logical OR negation data q of the negation data of the image data n formed in the N07 circuit 53 and the image data O.
form. That is, this logical sum negation data q is data that becomes rlJ for a predetermined period (UTh) that is an integral multiple of the upward horizontal synchronization period of the waveform 0, as shown by the waveform q in FIG. Further, the NOR circuit 56 forms logical sum negation data r of the negation data of the image data p formed by the N07 circuit 54 and the image data 0. That is, this logical sum negation data r is data that becomes "1" only for a predetermined period (DTh) that is an integral multiple of the downward horizontal synchronization period of the waveform 0, as shown by waveform r in FIG. Furthermore, the OR circuit 57 forms logical sum data t of the data q and the data r. In other words, this logical sum data t is data that becomes "1" only for a predetermined period (UTh and DTh) that is an integral multiple of the horizontal synchronization period in the vertical direction of the waveform 0, as shown in the waveform diagram in FIG. be. This logical sum data L is supplied to the second output terminal 62. Further, the image data 0 supplied to the input terminal 59 is supplied as image data S to the first output terminal 61 as is.

Therefore, in this vertical edging circuit 51, the image data S that becomes the normal image 115 shown in FIG. 11, which is the same as the normal image 112, is obtained at the first output terminal 61, and
At the second output terminal 62, image data t that becomes the vertically bordered image 116 of the normal image 115 is obtained.

In the horizontal edging circuit 63, the image data S supplied to the input terminal 74 is delayed by a predetermined time (LDL) in the first delay circuit 65, and the image 11 shown by A in FIG.
7, image data 5 (DL) is formed. Further, the OR circuit 64 outputs the image data S and the input terminal 7.
From the image data t supplied to 5, logical sum data U, which becomes an image 118 shown at B in FIG. 12, is formed. The second data U is delayed by the predetermined time (LDL) by the second delay circuit 66, and the image 11 shown by C in FIG.
The image data V becomes 9. Furthermore, this image data V is processed by the third delay circuit 67 for a predetermined time (RDL
) is delayed and becomes image data W, which becomes image 120 shown as D in FIG. Further, the NOR circuit 71 forms image data X, which becomes the image 121 shown at E in FIG. 12, from the negative data of the data U output from the N07 circuit 69 and the data ■. In addition, the above NOR circuit 7
2 forms image data Y, which becomes an image 122 shown in FIG. Furthermore,
The data t is delayed by the predetermined time (LDL) by the fourth delay circuit 6 days, and becomes image data T (DL), which becomes the image 123 indicated by F in FIG. 12. These image data X1 image data Y and image data T (DL)
is the logical OR from the three-man OR circuit 73, and the first
The image data Z becomes the image 124 indicated by G in FIG.

Therefore, in this horizontal edge trimming circuit 63, the image 1 is output from the first delay circuit 65 to the first output terminal 77.
17 image data S (DL) is obtained, and image data Z of an image 124 with a full periphery in the vertical and horizontal directions of the image 117 is obtained at the second output terminal 78.

The image data S (DL) and the image data Z are converted into three primary color signals (R.

G, B) are designated as colors, subjected to superposition processing in the superimposition circuit 83, and output as title image signals from the signal output terminals 84R, 84G, and 84B to the conversion circuit 15.

This title image signal is transmitted to each of the above-mentioned impose circuits 5.6.
．． At step 7, the title image 127 is inserted into the output signal of the image signal processing circuit 4, and as shown in FIG.

(G-2) Application Example The titler circuit 12 may be configured to supply the image data supplied from the A/D conversion circuit 11 to the memory 13 as serial data. Further, the image data may be several-bit image data obtained by converting the luminance signal (Y) into data at a plurality of levels. Furthermore, the presence or absence of the vertically bordered image and the all-periphery bordered image formed by the titler circuit 12 may be selected using an operation switch (not shown) or the like.

Note that in the above embodiment, the N
Although the present invention is applied to a camera-integrated VTR for TSC, the present invention is not limited to the above-mentioned embodiments. The present invention can also be applied to a title image generating device used in a stationary titler, captioner, etc., which generates a title image signal from this image data by synchronizing it with a reproduced video signal of a VTR or other input video signal.

H0 Effects of the Invention In the present invention, the image data stored in the memory means is read out by three memory control means having different readout timings for a predetermined period that is an integral multiple of the horizontal synchronization period, and Each image data is superimposed to form a vertical border image signal.

Therefore, in the title image ordering device according to the present invention, three image data having a delay amount of a predetermined period that is an integral multiple of the horizontal synchronization period are read out from the memory means, so there is no need to use a delay circuit having a large delay amount. , a delay 1t (UTh,
The circuit size can be reduced compared to a conventional title image generation device which requires a delay circuit having a delay circuit (DTh).

Further, in the title image generation device according to the present invention, a right side border image signal and a left side border image signal are formed from the output image signals of the two delay circuits, and are superimposed on the vertical border image signal, thereby easily generating a title image. It is possible to generate image signals with vertical and horizontal borders surrounding the entire circumference.
It is possible to realize a variety of title images.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing the configuration of a titler circuit of a camera-integrated VTR to which the present invention is applied, FIG. 2 is a block diagram showing the configuration of the camera-integrated VTR, and FIG. FIG. 4 is a circuit diagram showing the configuration of a vertical border generation circuit used in the titler circuit, and FIG. 5 is a circuit diagram showing the configuration of a horizontal border generation circuit used in the titler circuit. 6 is a schematic diagram showing an image for explaining the registration operation, and FIG. 7 is a time chart for explaining the operation of the titler circuit in the registration operation,
FIG. 8 is a time chart for explaining the operation of the titler circuit in the insertion operation, FIG. 9 is a schematic diagram showing an image for explaining the operation of the titler circuit in the insertion operation, and FIG. is a waveform diagram for explaining the operation of the vertical border generation circuit, FIG. 11 is a schematic diagram showing an image for explaining the operation of the vertical border generation circuit, and FIG. 12 is a waveform diagram for explaining the operation of the vertical border generation circuit. FIG. 13 is a schematic diagram showing an image for explaining the operation of the circuit, and FIG. 13 is a schematic diagram showing an image for explaining image data of a title image output from the titler circuit. 1st
FIG. 4 is a circuit diagram showing the configuration of the conventional example, and FIG. 15 is a schematic diagram for explaining the operation of the conventional example. 5.6.7...impose circuit 10...imaging section 11...A/D conversion circuit 12...titler circuit 13...memory 51...vertical border generation circuit 63...horizontal Border generation circuit 87...Sequential address switching circuit 90.91.92...Sequential address generation circuit Figure 5 Figure 7 Figure 8

Claims (2)

[Claims] (1) means for digitizing an input video signal to form image data; memory means for storing said image data; first memory control means for reading image data from said memory means; and said first memory control means. From the reading timing of the means
a second memory control means that reads image data from the memory means at a timing that is a predetermined period that is an integral multiple of the horizontal synchronization period;
a third memory control means for reading image data from the memory means at a timing delayed by a predetermined period that is an integral multiple of the horizontal synchronization period; An image signal of an upper border image excluding an image overlapping with the image based on the image data read out under the control of the first memory control means, and an image based on the image data read out under the control of the third memory control means. A vertical border image signal is formed from each of the image data by superimposing the image signal of the lower border image excluding the overlapping image with the image based on the image data read out under the control of the first memory control means. A title image generating device comprising means. (2) an addition circuit that generates an image signal in which the vertical border image signal is superimposed on the image data read out under the control of the first memory control means; and a predetermined delay in the output image signal of the addition circuit. a second delay circuit that applies a predetermined amount of delay to the output image signal of the first delay circuit; and a second delay circuit that applies a predetermined amount of delay to the output image signal of the addition circuit; The left side border image signal excluding the image that overlaps with the image generated by the output image signal of , and the right side image signal excluding the image that overlaps with the image generated by the output image signal of the first delay circuit from the image generated by the output image signal of the second delay circuit. 2. The image forming apparatus according to claim 1, further comprising means for forming a border image signal, and an addition circuit for generating a vertical and horizontal border image signal by superimposing the vertical border image signal, the left border image signal, and the right border image signal. Title image generator.