JPH01207939A - Assembly tape for integrated circuit device - Google Patents
Assembly tape for integrated circuit deviceInfo
- Publication number
- JPH01207939A JPH01207939A JP63033303A JP3330388A JPH01207939A JP H01207939 A JPH01207939 A JP H01207939A JP 63033303 A JP63033303 A JP 63033303A JP 3330388 A JP3330388 A JP 3330388A JP H01207939 A JPH01207939 A JP H01207939A
- Authority
- JP
- Japan
- Prior art keywords
- tape
- leads
- assembly
- integrated circuit
- parts
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 abstract description 8
- 239000011889 copper foil Substances 0.000 abstract description 8
- 239000004642 Polyimide Substances 0.000 abstract description 7
- 229920001721 polyimide Polymers 0.000 abstract description 7
- 230000007547 defect Effects 0.000 abstract description 4
- 238000000034 method Methods 0.000 abstract description 2
- 230000006835 compression Effects 0.000 abstract 1
- 238000007906 compression Methods 0.000 abstract 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は集積回路装置組立テープの導電性膜リー[の構
造に関する。DETAILED DESCRIPTION OF THE INVENTION FIELD OF INDUSTRIAL APPLICATION This invention relates to the structure of a conductive film lee of an integrated circuit device assembly tape.
[従来の技術]
従来、集積回路装置の組立テープ構造は特公昭47 3
206及び第2図に示されている如き構造をとるのが通
例であった。ずなわら、ポリイミド・テープ11の表面
には銅箔IJ−)” l 2か形成され、前記ポリイミ
ド・テープ11の穴部に銅箔リーF l 2が同−It
’さで張り出して成り、その端部がICチップ14のバ
ッド部12及び外部り一トパッド部と融着させるのが通
例であった。[Prior art] Conventionally, the assembly tape structure of integrated circuit devices was developed using the
206 and as shown in FIG. Of course, a copper foil F12 is formed on the surface of the polyimide tape 11, and a copper foil F12 is formed in the hole of the polyimide tape 11.
It was customary for the end portion to be fused to the pad portion 12 of the IC chip 14 and the external pad portion.
[発明が解決しようとする課題]
しかし、ト記従来技術によると、銅箔リートを、上部圧
接治具により圧接する際に、パント部以外に銅箔リード
が圧力印加され、チップを破壊したり、あるいは、圧力
が均一にかからす圧接不良を起こしたりする問題点があ
った。[Problems to be Solved by the Invention] However, according to the prior art mentioned above, when the copper foil lead is pressure-welded using the upper pressure-welding jig, pressure is applied to the copper foil lead other than the punt part, causing damage to the chip. Alternatively, there is a problem in that pressure is applied uniformly, resulting in poor pressure contact.
本発明はかかる従来技術の問題点をなくし、集積回路装
置の組立テープによる組立不良をなくする為の組立テー
プ構造を提供する事を目的とする。SUMMARY OF THE INVENTION An object of the present invention is to eliminate the problems of the prior art and to provide an assembly tape structure for eliminating assembly defects caused by assembly tapes of integrated circuit devices.
F記目的を達成するための本発明の基本的な構成は、集
積回路装置組立テープに関し、絶縁テープ表面に張り付
けた導電性膜リートの前記絶縁テープに開けられた穴部
に張り出した端部の集積回路装置子ノブのパッド部及び
外部リートパッド部と融着させる部分に凸部を形成する
手段をとる事である。The basic structure of the present invention to achieve the object F is related to an integrated circuit device assembly tape, in which an end portion of a conductive film reel pasted on the surface of the insulating tape protrudes into a hole made in the insulating tape. The method is to form a convex portion on a portion of the integrated circuit device child knob to be fused to the pad portion and the external lead pad portion.
[実 施 例〕 以下、実施例により本発明を詳述する。[Example〕 Hereinafter, the present invention will be explained in detail with reference to Examples.
第1図は、本発明の一実施例を示す組立テープの要部の
断面図である。すなわち、ポリイミド・テープ1には銅
箔リード2が張り付けられ、該銅箔リード2の前記ポリ
イミド・テープ1の開口部に張り出した端部に凸部を設
けるべく、半エツチング部3を設けて、前記凸部をIC
チ、プ4のバンド部と圧接させるものである。FIG. 1 is a sectional view of a main part of an assembly tape showing an embodiment of the present invention. That is, a copper foil lead 2 is attached to a polyimide tape 1, and a half-etched part 3 is provided in order to provide a convex part at the end of the copper foil lead 2 that projects into the opening of the polyimide tape 1. The convex portion is IC
It is brought into pressure contact with the band portions of 1 and 4.
尚、凸部は部分メツキ等によって形成しても良い事は云
うまでもない。It goes without saying that the convex portion may be formed by partial plating or the like.
〔発明の効果]
本発明により組立テープの導電性膜リードの圧接圧力が
均一になり、組立不良がなくなる効果がある。[Effects of the Invention] The present invention has the effect of making the contact pressure of the conductive film lead of the assembly tape uniform, and eliminating assembly defects.
第1図は本発明の一実施例を示す要部の断面図、第2図
は従来技術を示す要部の断面図である。
1、】1・・・ポリイミド・テープ
2.12・・・銅箔リード
3・・・・・・半エンチング部
4.14・・・ICチンプ
以 上
出願人 セイコーエプソン株代会社FIG. 1 is a cross-sectional view of a main part showing an embodiment of the present invention, and FIG. 2 is a cross-sectional view of a main part showing a conventional technique. 1. ]1...Polyimide tape 2.12...Copper foil lead 3...Semi-etched part 4.14...IC chimp or above Applicant: Seiko Epson Corporation
Claims (1)
縁テープに開けられた穴部に張り出した端部の集積回路
装置チップのパッド部及び外部リードパッド部と融着さ
せる部分に凸部を形成する事を特徴とした集積回路装置
組立テープ。Forming a convex portion at the end of the conductive film lead attached to the surface of the insulating tape that protrudes into the hole made in the insulating tape and is to be fused to the pad portion of the integrated circuit device chip and the external lead pad portion. An integrated circuit device assembly tape featuring:
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP63033303A JPH01207939A (en) | 1988-02-16 | 1988-02-16 | Assembly tape for integrated circuit device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP63033303A JPH01207939A (en) | 1988-02-16 | 1988-02-16 | Assembly tape for integrated circuit device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH01207939A true JPH01207939A (en) | 1989-08-21 |
Family
ID=12382783
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP63033303A Pending JPH01207939A (en) | 1988-02-16 | 1988-02-16 | Assembly tape for integrated circuit device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH01207939A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5777380A (en) * | 1995-03-17 | 1998-07-07 | Seiko Epson Corporation | Resin sealing type semiconductor device having thin portions formed on the leads |
US6140695A (en) * | 1997-05-15 | 2000-10-31 | Micron Technology, Inc. | Compression layer on the leadframe to reduce stress defects |
JP2007150374A (en) * | 1997-03-21 | 2007-06-14 | Seiko Epson Corp | Semiconductor device, film carrier tape and manufacturing method thereof |
-
1988
- 1988-02-16 JP JP63033303A patent/JPH01207939A/en active Pending
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5777380A (en) * | 1995-03-17 | 1998-07-07 | Seiko Epson Corporation | Resin sealing type semiconductor device having thin portions formed on the leads |
JP2007150374A (en) * | 1997-03-21 | 2007-06-14 | Seiko Epson Corp | Semiconductor device, film carrier tape and manufacturing method thereof |
US6140695A (en) * | 1997-05-15 | 2000-10-31 | Micron Technology, Inc. | Compression layer on the leadframe to reduce stress defects |
US6221695B1 (en) * | 1997-05-15 | 2001-04-24 | Micron Technology, Inc. | Method for fabricating a compression layer on the dead frame to reduce stress defects |
US6486539B1 (en) | 1997-05-15 | 2002-11-26 | Micron Technology, Inc. | Compression layer on the leadframe to reduce stress defects |
US6657288B2 (en) | 1997-05-15 | 2003-12-02 | Micron Technology, Inc. | Compression layer on the lead frame to reduce stress defects |
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