JPH01205468A - Gate electrode of mos type transistor and its manufacture - Google Patents
Gate electrode of mos type transistor and its manufactureInfo
- Publication number
- JPH01205468A JPH01205468A JP3024288A JP3024288A JPH01205468A JP H01205468 A JPH01205468 A JP H01205468A JP 3024288 A JP3024288 A JP 3024288A JP 3024288 A JP3024288 A JP 3024288A JP H01205468 A JPH01205468 A JP H01205468A
- Authority
- JP
- Japan
- Prior art keywords
- film
- polycrystalline silicon
- gate electrode
- silicon film
- melting point
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 38
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 22
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 22
- 229910052751 metal Inorganic materials 0.000 claims abstract description 17
- 239000002184 metal Substances 0.000 claims abstract description 17
- 238000002844 melting Methods 0.000 claims abstract description 15
- 230000008018 melting Effects 0.000 claims abstract description 14
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 10
- 238000005530 etching Methods 0.000 claims abstract description 10
- 239000000758 substrate Substances 0.000 claims abstract description 7
- 238000000059 patterning Methods 0.000 claims abstract description 5
- 238000000034 method Methods 0.000 claims description 8
- 239000004065 semiconductor Substances 0.000 claims description 4
- 238000010438 heat treatment Methods 0.000 abstract description 7
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 abstract description 7
- 229910021342 tungsten silicide Inorganic materials 0.000 abstract description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 5
- 229910052814 silicon oxide Inorganic materials 0.000 abstract description 5
- 230000000694 effects Effects 0.000 abstract description 4
- 239000000203 mixture Substances 0.000 abstract description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 3
- 229910052710 silicon Inorganic materials 0.000 abstract description 3
- 239000010703 silicon Substances 0.000 abstract description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 abstract description 2
- 239000012535 impurity Substances 0.000 abstract description 2
- 229910052698 phosphorus Inorganic materials 0.000 abstract description 2
- 239000011574 phosphorus Substances 0.000 abstract description 2
- 230000001681 protective effect Effects 0.000 description 5
- 239000003870 refractory metal Substances 0.000 description 3
- 238000001947 vapour-phase growth Methods 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 229910021341 titanium silicide Inorganic materials 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、ＭＯＳ型トランジスタのゲート電極およびそ
の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a gate electrode of a MOS transistor and a method of manufacturing the same.
高い集積度をもつＭＯ５型半導体集積回路では、トラン
ジスタはポリサイド構造のゲート電極とし、さらにゲー
ト電極の側面に５ｉ０２もしくはＳｉ３Ｎ４の側壁を設
け、この絶縁膜をイオン注入の際の保護膜としてイオン
注入を行ない、ソース、ゲート領域を形成する技術が一
般的になっている。In MO5 type semiconductor integrated circuits with a high degree of integration, the transistor has a gate electrode with a polycide structure, and side walls of 5i02 or Si3N4 are provided on the sides of the gate electrode, and this insulating film is used as a protective film during ion implantation. Techniques for forming conductor, source, and gate regions have become commonplace.
上記のＭＯ５型トランジスタのゲート電極の従来の製造
方法につき、第３図を参照して説明する。先ず同図（ａ
）に示すように、半導体基板ｌｌ上にゲー］・酸化膜１
２．多結晶シリコン膜１３を成長させた後、さらにその
上に高融点金属シリサイド例えばタングステンシリサイ
ド膜１４を成長させる。そして多結晶シリコン膜１３、
タングステンシリサイド膜１４をパターニングして、同
図（ｂ）に示すようにポリサイド構造のゲート電極１０
を形成する。次に同図（Ｃ）に示すように、ゲート電極
１ｏをおおうようにして基板全面に気相成長法による酸
化膜１５を堆積してから、異方性ドライエツチングによ
り全面をエッチバックし、ゲート電極１゜の側面に、酸
化膜側壁１５′をのこし、側壁を有するゲート電極を形
成する。A conventional method for manufacturing the gate electrode of the MO5 transistor mentioned above will be explained with reference to FIG. First, the same figure (a
), a silicon oxide film 1 is formed on the semiconductor substrate ll.
2. After growing the polycrystalline silicon film 13, a refractory metal silicide, such as a tungsten silicide film 14, is further grown thereon. And polycrystalline silicon film 13,
By patterning the tungsten silicide film 14, a gate electrode 10 having a polycide structure is formed as shown in FIG.
form. Next, as shown in FIG. 1C, an oxide film 15 is deposited on the entire surface of the substrate by vapor phase growth so as to cover the gate electrode 1o, and then the entire surface is etched back by anisotropic dry etching. An oxide film sidewall 15' is left on the side surface of the electrode 1° to form a gate electrode having sidewalls.
前述した従来のゲート電極は、高融点金属シリサイド膜
が最」−膜であるため異方性エツチングのときに直接イ
オンによりダメジを受け、高融点金属シリサイド膜の組
成比がメタルリ・ンチになる。この状態で熱処理を行な
うと、特に酸素雰囲気中では、高融点金属シリサイド膜
が多結晶シリコン膜から剥離するという欠点がある。In the conventional gate electrode described above, since the high melting point metal silicide film is the most negative film, it is directly damaged by ions during anisotropic etching, and the composition ratio of the high melting point metal silicide film becomes metal etch. If heat treatment is performed in this state, there is a drawback that the high melting point metal silicide film will peel off from the polycrystalline silicon film, especially in an oxygen atmosphere.
本発明の目的は、上記の欠点を除去した、ポリサイド構
造のゲート電極の製造方法および、この製造方法による
グーｌ−電極を有するＭＯＳ型トランジスタを提供する
ことにある。SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a gate electrode having a polycide structure, which eliminates the above-mentioned drawbacks, and a MOS transistor having a goo-electrode produced by this manufacturing method.
本発明のゲート電極の製造方法は、半導体基板の一十面
に形成されたゲート醇化膜上に、順次第１多結晶シリコ
ン膜、高融点金属シリサイド膜を形成する工程と、前記
高融点金属シリサイド膜」−に多結晶シリコン膜もしく
は非晶質シリコン膜を形成する工程と、前記第１多結晶
シリコン膜・高融点金属シリサイド膜・多結晶シリコン
膜もしくは非晶質シリコン膜をパターニングしてゲート
電極を形成する工程と、前記ゲート電極をおおい絶縁膜
を形成した後、異方性エンチングにより前記絶縁膜をゲ
ート電極の側壁部分を残し、他の部分を除去する工程と
からなるものである。このゲート電極を形成後、ソース
・トレイン領域形成を行なったＭＯＳ型トランジスタは
、ゲート酸化股上に順次第１多結晶シリコン膜、高融点
金属シリサイド膜、多結晶シリコン膜が積層されてなり
、側壁に絶縁膜を有する。The method for manufacturing a gate electrode of the present invention includes the steps of sequentially forming a polycrystalline silicon film and a high melting point metal silicide film on a gate fused film formed on ten surfaces of a semiconductor substrate, and a step of forming a polycrystalline silicon film or an amorphous silicon film on the film, and patterning the first polycrystalline silicon film, high melting point metal silicide film, polycrystalline silicon film, or amorphous silicon film to form a gate electrode. and a step of forming an insulating film covering the gate electrode, and then removing the insulating film by anisotropic etching, leaving only the sidewall portions of the gate electrode and other portions. After this gate electrode is formed, a source/train region is formed in the MOS transistor, in which a polycrystalline silicon film, a high-melting point metal silicide film, and a polycrystalline silicon film are sequentially laminated on the gate oxide ridge, and the sidewalls are It has an insulating film.
ポリサイド構造の、上層であるシリサイド膜は多結晶シ
リコン膜もしくは非晶質シリコン膜で保護されていて、
異方性エツチングの際、ダメジをうけない。したがって
、その組成は一定であり、後の処理における熱処理によ
り、下層の多結晶シリコン膜から剥離することがない。The upper layer of the polycide structure, the silicide film, is protected by a polycrystalline silicon film or an amorphous silicon film.
No damage occurs during anisotropic etching. Therefore, its composition is constant, and it will not peel off from the underlying polycrystalline silicon film during heat treatment in subsequent processing.
ここで保護膜である多結晶シリコン膜、非晶質シリコン
膜は異方性エツチングに対して、耐性があり、多少その
表面がイオン損傷をうけても、組成の変化はない。Here, the polycrystalline silicon film and the amorphous silicon film that are the protective films are resistant to anisotropic etching, and even if their surfaces are subjected to some ion damage, their compositions do not change.
以下、本発明のゲート電極の製造方法を、実施例につき
説明する。第１図は、第１実施例の主要工程を示す断面
図である。第１図（ａ）に示すように、シリコン基板１
上に、ゲート酸化膜２を３ｏｏｉ形成し、その上に多結
晶シリコン膜３をｚｏｏｏ′Ａ被着した後不純物として
リンを添加する。次に高融点金属シリサイド膜としてタ
ングステンシリサイド膜４を２ｏｏｏ′Ａ被着し、さら
にその上に多結晶シリコン膜５を１０００Ａ被着する。Hereinafter, the method for manufacturing a gate electrode of the present invention will be described with reference to Examples. FIG. 1 is a sectional view showing the main steps of the first embodiment. As shown in FIG. 1(a), a silicon substrate 1
A three-dimensional gate oxide film 2 is formed thereon, a polycrystalline silicon film 3 is deposited thereon, and then phosphorous is added as an impurity. Next, a tungsten silicide film 4 of 200'A is deposited as a high melting point metal silicide film, and a polycrystalline silicon film 5 of 1000A is further deposited thereon.
次に第１図（ｂ）に示すように、パターニングにより、
ゲート電極部を形成する。図で多結晶シリコン膜３′
、タングステンシリサイド膜４′が従来のポリサイド構
造であって、その」二部に多結晶シリコン膜５′が被着
し、保護膜となっている。以下、側壁の形成工程になる
が、第１図（ｃ）に示すように、気相成長法によりシリ
コン酸化膜６を２００ＯＡ堆積してから、第１図（ｄ）
に示すように、異方性エツチングによりゲート電極の側
面にのみ酸化膜側壁６′が残るようにして他の部分を除
去することで、所定のゲート電極が形成される。Next, as shown in FIG. 1(b), by patterning,
Form a gate electrode section. In the figure, polycrystalline silicon film 3'
The tungsten silicide film 4' has a conventional polycide structure, and a polycrystalline silicon film 5' is deposited on two parts of the tungsten silicide film 4' to serve as a protective film. The next step is to form the sidewalls. As shown in FIG. 1(c), a silicon oxide film 6 of 200 OA is deposited by vapor phase growth, and then as shown in FIG. 1(d).
As shown in FIG. 2, a predetermined gate electrode is formed by anisotropic etching so that the oxide film side walls 6' remain only on the side surfaces of the gate electrode, and the other portions are removed.
」１記実施例では、ポリサイド構造の上層はりングステ
ンシリサイドであったが、低抵抗なチタンシリサイドで
も同様にして形成される。第２図（ａ）は、ゲート電極
を形成した状態を示す図で、多結晶シリコン膜３′の厚
さは２０００Ａ、チタンシリサイド膜７′の厚さも２０
００Ａでリンが添加されている。多結晶シリコン膜５′
は５００Ａとしである。次に、全面に気相成長法により
シリコン酸化膜を被着後、異方性エツチングにより、エ
ッヂパックして、第２図（ｂ）に示すように、ゲート電
極側面にのみ酸化膜側壁６′を残して他の部分を除去す
ることで、本発明のゲート電極を得る。In the first embodiment, the upper layer of the polycide structure was made of ringsten silicide, but low-resistance titanium silicide may also be formed in the same manner. FIG. 2(a) is a diagram showing the state in which the gate electrode has been formed, and the thickness of the polycrystalline silicon film 3' is 2000 Å, and the thickness of the titanium silicide film 7' is also 200 Å.
Phosphorus is added at 00A. Polycrystalline silicon film 5'
is 500A. Next, after a silicon oxide film is deposited on the entire surface by vapor phase growth, it is edge-packed by anisotropic etching to form an oxide film sidewall 6' only on the side surface of the gate electrode, as shown in FIG. 2(b). The gate electrode of the present invention is obtained by leaving the remaining portion and removing the other portion.
第１．第２実施例では、異方性エツチングに対する、ポ
リサイド構造の」二層をなす高融点金属のシリサイド膜
の保護膜として多結晶シリコン膜を用いているが、非晶
質シリコン膜でも、同様な効果を与える。1st. In the second embodiment, a polycrystalline silicon film is used as a protective film for the two-layer refractory metal silicide film of the polycide structure against anisotropic etching, but an amorphous silicon film can also have the same effect. give.
次に、このようにして、ゲート電極形成後、イオン注入
を行ない、ソース、ゲート領域を形成するが、前記領域
形成中の熱処理、あるいはその後の熱処理において、高
融点金属シリサイド膜は、多結晶シリコン膜から剥離す
ることがない。したがって、製品渉留が良く、かつ特性
信頼度の高いＭＯＳ型トランジスタを得ることができる
。このＭＯＳ型トランジスタでは、ゲート電極の最」二
層を非晶質シリコン膜とした場合でも熱処理により多結
晶化し、多結晶シリコン膜となっている。Next, in this way, after forming the gate electrode, ion implantation is performed to form the source and gate regions. However, in the heat treatment during the formation of the regions or in the subsequent heat treatment, the high melting point metal silicide film is removed from polycrystalline silicon. It will not peel off from the film. Therefore, it is possible to obtain a MOS transistor with good product soldering properties and high reliability of characteristics. In this MOS transistor, even if the two most layers of the gate electrode are amorphous silicon films, they become polycrystalline through heat treatment and become polycrystalline silicon films.
以−１−説明したように、本発明ではポリサイド構造の
ゲート電極として、従来の」二層が高融点金属のシリサ
イド膜、下層が多結晶シリコン膜の積層の上部に、多結
晶シリコン膜もしくは非晶質シリコン膜の保護膜を形成
しておくことで、ゲート電極側壁を形成する工程におけ
る異方性エツチングでも、高融点金属シリサイド膜はタ
メジをうけない。これによって、従来のように、高融点
金属シリサイド膜がメタルリッチになることがなく、下
層の多結晶シリコン膜との密着は後続する熱処理工程で
も完全に保たれている。このようにしてゲート電極が形
成され、後の工程でトランジスタとして製造されたＭＯ
Ｓ型トランジスタは、極めて特性が安定し信頼性が高い
。As explained below -1-, in the present invention, as a gate electrode with a polycide structure, a polycrystalline silicon film or a non-polycrystalline silicon film is added on top of the conventional two-layer stack of a high melting point metal silicide film and a lower layer as a polycrystalline silicon film. By forming the protective film of the crystalline silicon film, the high melting point metal silicide film will not be damaged even during anisotropic etching in the process of forming the side walls of the gate electrode. This prevents the refractory metal silicide film from becoming metal-rich as in the prior art, and the adhesion to the underlying polycrystalline silicon film is completely maintained even in the subsequent heat treatment process. In this way, a gate electrode is formed, and the MO is manufactured as a transistor in a later process.
S-type transistors have extremely stable characteristics and high reliability.
第１図、第２図は本発明の実施例の主要工程断面図、第
３図は従来例の主要工程断面図である。
１・・・シリコン基板、 ２・・・ゲート酸化膜、
３．３′・・・多結晶シリコン膜、
４．４′・・・タングステンシリサイド膜、５．５′・
・・多結晶シリコン膜、
６・・・シリコン酸化膜、 ６′・・・酸化膜側壁。
特許出願人 日木電気株式会社
代理人 弁理士 内 原 晋区1 and 2 are sectional views of the main steps of the embodiment of the present invention, and FIG. 3 is a sectional view of the main steps of the conventional example. 1... Silicon substrate, 2... Gate oxide film,
3.3'...Polycrystalline silicon film, 4.4'...Tungsten silicide film, 5.5'...
... Polycrystalline silicon film, 6... Silicon oxide film, 6'... Oxide film sidewall. Patent applicant: Hiki Electric Co., Ltd. Agent: Susumu Uchihara, patent attorney
Claims (2)
に、順次第１多結晶シリコン膜、高融点金属シリサイド
膜を形成する工程と、前記高融点金属シリサイド膜上に
多結晶シリコン膜もしくは非晶質シリコン膜を形成する
工程と、前記第１多結晶シリコン膜・高融点金属シリサ
イド膜・多結晶シリコン膜もしくは非晶質シリコン膜を
パターニングしてゲート電極を形成する工程と、前記ゲ
ート電極をおおい絶縁膜を形成した後、異方性エッチン
グにより前記絶縁膜をゲート電極の側壁部分を残し、他
の部分を除去する工程とからなることを特徴とするＭＯ
Ｓ型トランジスタのゲート電極の製造方法。(1) Steps of sequentially forming a polycrystalline silicon film and a high melting point metal silicide film on a gate oxide film formed on one main surface of a semiconductor substrate, and forming a polycrystalline silicon film on the high melting point metal silicide film. Alternatively, a step of forming an amorphous silicon film, a step of patterning the first polycrystalline silicon film, a high melting point metal silicide film, a polycrystalline silicon film, or an amorphous silicon film to form a gate electrode; An MO comprising the steps of: forming an insulating film covering the electrode, and then removing the insulating film by anisotropic etching, leaving only the side wall portion of the gate electrode and removing the other portion.
A method for manufacturing a gate electrode of an S-type transistor.
シリコン膜、高融点金属シリサイド 膜、多結晶シリコン膜が積層されてなるとともに、側壁
に絶縁膜を有することを特徴とするＭＯＳ型トランジス
タ。(2) A MOS type in which the gate electrode is formed by sequentially stacking a polycrystalline silicon film, a high melting point metal silicide film, and a polycrystalline silicon film on a gate oxide film, and has an insulating film on the sidewalls. transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3024288A JPH01205468A (en) | 1988-02-10 | 1988-02-10 | Gate electrode of mos type transistor and its manufacture |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3024288A JPH01205468A (en) | 1988-02-10 | 1988-02-10 | Gate electrode of mos type transistor and its manufacture |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01205468A true JPH01205468A (en) | 1989-08-17 |
Family
ID=12298240
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3024288A Pending JPH01205468A (en) | 1988-02-10 | 1988-02-10 | Gate electrode of mos type transistor and its manufacture |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01205468A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06112503A (en) * | 1992-09-25 | 1994-04-22 | Rohm Co Ltd | Semiconductor storage device and manufacture thereof |
| US5543362A (en) * | 1995-03-28 | 1996-08-06 | Motorola, Inc. | Process for fabricating refractory-metal silicide layers in a semiconductor device |
| US5801427A (en) * | 1995-05-26 | 1998-09-01 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device having a polycide structure |
| US5945719A (en) * | 1997-03-21 | 1999-08-31 | Nec Corporation | Semiconductor device having metal silicide layer |
| US6103606A (en) * | 1996-09-21 | 2000-08-15 | United Microelectronics Corp. | Method of fabricating a word line |
-
1988
- 1988-02-10 JP JP3024288A patent/JPH01205468A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06112503A (en) * | 1992-09-25 | 1994-04-22 | Rohm Co Ltd | Semiconductor storage device and manufacture thereof |
| US5543362A (en) * | 1995-03-28 | 1996-08-06 | Motorola, Inc. | Process for fabricating refractory-metal silicide layers in a semiconductor device |
| US5801427A (en) * | 1995-05-26 | 1998-09-01 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device having a polycide structure |
| US6103606A (en) * | 1996-09-21 | 2000-08-15 | United Microelectronics Corp. | Method of fabricating a word line |
| US5945719A (en) * | 1997-03-21 | 1999-08-31 | Nec Corporation | Semiconductor device having metal silicide layer |
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