JPH01205250A - Method for controlling cache memory - Google Patents

Abstract

PURPOSE:To increase a resident rate to the cache memory of specific information and to execute an efficiency by giving a tag to specific data, making a specific number of ways into ways with tags as to the ways to store the data with the tag, and excluding them from the object of a data rewriting. CONSTITUTION:A cache memory 13 is composed of a CACHE DIRECTORY ARRAY 14 and a CACHE DATA ARRAY 15. Here, the specific data are made into the data with the tag, and the specific number of ways to be simultaneously exist in the ways to store the data with the tag is made into the ways with the tags. At the time of rewriting the data, the way with the tag is handled as the way not to be made into the object of the rewriting in an algorithm, and at the time of rewriting the data with the tag, the way to store the data with the tag is switched as a new way with the tag. Thus, the resident rate of the specific data can be increased, and the cache memory 13 can be efficiently controlled.

Description

[Detailed Description of the Invention] [Summary] A control method for a cache memory composed of a plurality of ways, which uses a predetermined algorithm to determine which way data is to be rewritten. This is a method for controlling a cache memory composed of multiple ways, with the aim of achieving efficient cache memory control with high performance. In the algorithm determined by It is handled as not subject to rewriting in the above algorithm, and when tagged data is rewritten, it is configured to be replaced as a new tagged way that is the way in which this tagged data is stored.

(Industrial Application Field) The present invention relates to a method for controlling a cache memory, and in particular a method for controlling a cache memory composed of a plurality of ways, in which a predetermined algorithm is used to determine which way data is to be rewritten. related to things.

[Conventional technology]

Generally, in an information processing apparatus, as shown in FIG. It is designed to speed up data transfer. The access time of the cache memory 4 is very short compared to the access time of the main storage device 3, and the amount of data that it can hold is very small compared to the amount of data that the main storage device 3 can hold. Therefore, data must be efficiently held in this cache memory 4.

In the figure, reference numeral 5 indicates an I unit, 6 indicates an E unit, and 7 indicates a storage control device (MCTO).

Conventionally, as a control method for such a cache memory, L
RU (Least Recently Used)
method may be adopted. In this LRU method, when the storage capacity of the cache memory becomes full and new data cannot be written, the least recently referenced data is replaced with new data.

In an example where the cache memory is composed of four ways from way 0 to way 3, this is done according to a logical table as shown in FIG. In the figure, Bol, B02, B
03, B12, B13, and B23 indicate which of Ways 0 to 3 was most recently referenced, as shown in FIG. 9, and for example, B. , is way 0 and way l
If way O has been referenced more recently, it will be 1, and conversely, if way 1 has been referenced more recently, it will be 0. This is other B02, B03, B12, B13
, B23, if way 0 is the least recently referenced among all ways, B. □、B
All values of O2 and BO3 are 1. Note that in FIG. 3, the symbol Φ indicates that it does not matter whether the value of the bit is 0 or 1. Also, when the cache is hit, bit B, ..., B2
3 write logic is shown in FIG.
1. Using such a logical table, the least recently referenced way is recognized and the data is rewritten.

[Problem that the invention seeks to solve]

By the way, in addition to user data, such cache memory also stores translation tables, supervisors,
Data such as firmware instructions are mixed.

However, in the cache memory control method using the LRU method described above, data replacement is performed regardless of the nature of the data, so there is a problem that efficient replacement cannot be performed.

SUMMARY OF THE INVENTION An object of the present invention is to provide a cache memory control method that can perform efficient cache memory control by increasing the resident rate of specific data.

[Means for solving problems]

Means for solving the above problems in the present invention are as follows:
In a method for controlling a cache memory composed of multiple ways, which uses a predetermined algorithm to determine which way's data is to be rewritten, specific data is treated as tagged data, and such tagged data is A specific number of stored ways that exist simultaneously are treated as tagged ways, and when data is rewritten, tagged ways are treated as not being rewritten in the above algorithm, and when tagged data is rewritten, this tag is This means replacing the way in which the tagged data is stored as a new tagged way.

[Operation] According to the present invention, a tag is attached to specific data stored in the cache memory, and a specific number of ways storing this tagged data are excluded from data rewriting as tagged ways. becomes. Therefore, it is possible to increase the resident rate of specific information in the cache memory.

〔Example〕

Embodiments of the cache memory control method according to the present invention will be described below with reference to the drawings.

1 to 7 show an embodiment of a cache memory control method according to the present invention. FIG. 1 shows an overall configuration diagram of an apparatus that executes a cache memory control method according to the present invention.

In the figure, 10 is a register that stores a logical address from an unit of the CPU, and 11 is a TLB that converts a predetermined upper address of this logical address into a real address, and has two ways, primary and alternate. The output of this TLBII is then output via the selector 12. In addition, 13 indicates a cache memory,
This cache memory 13 receives the output from the above-mentioned TLB, and has a cache directory array (hereinafter referred to as DIR) 14 that outputs a real address and a cache data array (CHACHE DAT) that outputs the data stored at this real address.
EARREY (hereinafter referred to as CDA) 15, and is divided into four ways (WAYO to WAY3). A directory match register (DMR) 16 is provided in each way of each DIR 14. Then, a selector 17 provided in the CDA 15 receives the above DMR value and selects data corresponding to that address. The data from this selector 17 is I WR (IF WORD
REGISTER) 18 and 0WR (OP WORD
REGISTER) 19.

Further, in the figure, reference numeral 20 denotes a write logic generation section which generates write logic upon receiving the output of the DMR described above, and stores third and fourth logic tables. In the figure, 1 and 0 mean that the bit is rewritten to 1 or 0, and the symbol X means that the bit is not changed (the same applies hereinafter). The third logical table is used when registering untagged data, and as shown in Figure 5, a tag part (2 bits) is added to the first logical table, and
These bits are marked with X. The fourth logical table is used when registering tagged data, and as shown in Figure 6, a value corresponding to the own way number is added to the tag part of the second logical table. be.

In addition, 21 is a cache repress array (RAR: CA
CHE REPLACE ARRAY), which is reference information (6 bits) between each way of the cache memory 13.
The tagged way number and tag way bit (2 bits) are stored. 22 is a decision logic unit that receives the reference information and tagway information of the RAR 21 and the valid information of the DIR 21 and determines the way to be rewritten. In this decision logic unit 22, the fifth
and a first logical table that specifies the way to be rewritten based on the reference information after processing,
The way number indicating the way to be replaced is entered in the repress way number register (RE) through the fifth and first logical tables.
PLACE WAY No REG) is set to 23.

As shown in FIG. 7, this fifth logical table adds information to the reference information based on the way number specified by the tag way bit. For example, if the way indicated by the tag way bit is way 1, SOt is forced to 0, B
12 is forcibly set to 1, and B13 is forcibly set to 1. The symbols FORCEI and FORCEO in the figure mean that each bit is forcibly set to 1 or O, and the symbol X means that no change is made.

Since the first logical table is exactly the same as the logical table shown in FIG. 3 in the description of the prior art, detailed description thereof will be omitted.

These decision logics can be realized by the logic circuit diagram shown in FIG.

Next, the operation of the device according to this embodiment will be explained.

First, we will discuss cache memory access. ■TEAR (T CYCLEEFFE) sent from the unit
CTIVE ADR8) TLBII and D
I R (CACHE DIRECTORY ARRA)
Y) 14 is accessed, the address translated by TLBII and the accessed address in DIR 14 are matched, and if a matching address exists in any way, the DMR( D.I.
RECTORY MATCHREGISTER) 16
Set to ON. In addition, BEAR (B CYCLE EFF
ECTIVE ADR8) 24 “?? Ha, D A
R (CACI (E DATA ARRAY) 15 is being accessed, and the DMR 16 is used as a select signal for the read data. The data selected by the DMR signal is I WR (IF WORD R
EGISTER) 18 and 0WR (OP WORD RE
GISTER) 19 will be sent.

Next, RAR(CAC:HE REPLACE ARR
AY) The operation of 21 will be described. The RAR21 is the same as the above BEAR.
AR (RCYCLE EFFCTIVE ADR3) 25
accessed by The RAR 21 also holds inter-way reference status (6 bits) and tag way bits (2 bits).

The 8-bit write logic of the RAR 21 will be described in detail. The 8-bit write logic is as described above, and the WAY (D
IRMCHWAY) and the above-mentioned BOl・B 0
2. BO31B! l+ Bt: Write to the reference status bit of i・B23 (for example, when way O is referenced, "1" is written to B., B, 2. Bo). Also, when registering data, There are two types of write logic when registering untagged data and when registering tagged data.The former write logic writes only to the reference status bit (6 bits) as described above.The latter write logic writes only to the reference status bit (6 bits). Writing is performed to the reference status bit (6 bits) and the tagway bit (2 bits).The value written to the reference status bit is the same as the former, and the value written to the tagway bit is the TAG sent from the unit. It recognizes that the data is tagged by the signal, and sets the way number (for example, when registering to way 0, both bits are "0") when registering the tagged data in the cache memory to TB, , TB. The decision logic shown in Figure 2 is constructed based on the information written above and the VALID signal of DIR, and the way information to be replaced is REPLACEW.
AY NO, REG Set to 23.

Next, we will discuss the details of decision logic. For the above 6 bits indicating the reference status between ways, if tagged data is registered in way O as shown in the fifth logical table, B. 1. The 3 bits of BO2 and BO3 are forced to “1°”.
', and the other bits are read out with their written values. Similarly, even when tagged data is registered in another way, some bits are forcibly converted to values according to the fifth logic table and read out. If the valid bits of DIR are all 1 from way 0 to way 3, the REPLBOI read as above,
REPL BO2, REPL BO3, REPL B1
2. REPL B13. REPLB23 (REPLAC
The 6 bits of the LRU algorithm (E BIT)
Replacement according to the first logical table) is performed. In other words, if tagged data is registered in way 0, use the above REPLACE BI to make way 0 the latest information.
T is controlled to prevent replacement of way 0. The same thing is done when tagged data is registered in other ways. Note that if there is a way whose valid bit of DIR is not 1, the way with the lowest number among them is selected as the replacement way. Further, if the data newly registered by the replacement algorithm is tagged data, the way number for registering the new tagged data in the cache memory is written to TBo and TB□. Otherwise, TB, TB□ maintain their current values. As a result, one way per line is assigned to tagged data.

(Effects of the Invention) As explained above, according to the present invention, the cache memory control method is implemented by using specific data as tagged data.
Among the ways that store such tagged data, a specific number of ways that exist simultaneously are defined as tagged ways, and when data is rewritten, the tagged ways are treated as not being rewritten in the above algorithm, and the tagged data is When rewriting the tagged data, the way that stored this tagged data is replaced as a new tagged way, so it is possible to increase the resident rate of specific data and perform efficient cache memory control. be effective.

[Brief explanation of the drawing]

FIG. 1 is an overall configuration diagram of a device to which the present invention is applied, FIG. 2 is a diagram showing a logic circuit of the decision logic section of the device shown in FIG. 1, and FIG. 3 is a logic table used in the LRU method. 4, 5, and 6 show the second
FIG. 7 is a diagram showing the fifth logic table stored in the decision logic section, FIG. 8 is a diagram showing a computer to which the present invention is applied, and FIG. 9 is a diagram showing the third and fourth logic tables, respectively. FIG. 2 is a diagram showing the relationship between ways of a cache memory. 11...TLB 13...Cache memory 20...Write logic unit 21...RAR 22...Decision logic unit

Claims (1)

[Claims] A control method for a cache memory composed of a plurality of ways, in which data in which way is to be rewritten is determined using a predetermined algorithm. A specific number of ways that exist simultaneously that store tagged data such as A cache memory control method characterized in that, at the time of rewriting, a way storing this tagged data is replaced as a new tagged way.