JPH01201740A - Microprocessor trace device - Google Patents

Abstract

PURPOSE:To apply a sequential trigger and to change trace conditions during a trace by programming data outputted by a condition generator beforehand. CONSTITUTION:When a microprocessor 1 operates, an upper limit trace address detector 6a and a lower limit trace address detector 6b respectively compare an address value 9 with a value inputted from a ROM 4 and output detection signals 14a and 14b within upper limit and lower limit address range. An AND circuit 7 obtains the AND of the signals 14a and 14b and outputs a trace enable signal 15 to a memory device 3. A trace memory controller 3 stores trace data 10 from the microprocessor 1 into the memory. A trigger address detector 5 compares the address value 9 from the microprocessor 1 with a trigger address value 12 inputted from the ROM 4 and outputs a trigger address detection signal 11.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a microprocessor tracing device used for debugging a microprocessor.

2. Description of the Related Art Conventional microprocessor trace devices include, for example, the following. FIG. 3 shows a block diagram of this conventional microprocessor tracing device, where 1 is a microprocessor, and 2 is a microprocessor l.
It is the main memory connected to 3 is microprocessor 1
9 is an address value output by the microprocessor 1, IO is a trace data value, 16 is a first register that stores and outputs a trigger address, and 17 is a trace address. A second register that stores and outputs the range of . 18 is a trigger address detector which compares the output value of register 16 and the address value of processor 1 and outputs a trigger address detection signal; 19 compares the output value of register 17 with the address value of processor 1 and determines whether the address is within a predetermined address range. This is an address range detector that detects and outputs an address range detection signal. 20 is a trigger address value outputted by register 16, 21 is an address range data value outputted by register 17, 22 is a trigger address detection signal outputted by trigger address detector 18, and 23 is an address range detection signal outputted by address range detector 19. be.

In the conventional microprocessor trace device configured as described above, when the microprocessor 1 executes a program, the trigger address detector 18 and the address range detector 19 input the address value 9 outputted by the microprocessor 1 and determine the trigger address. The detector 18 compares the trigger address value 20 outputted by the register 16 and outputs a trigger address detection signal 22. Address range detector 1
9 is the address range data value 21 output by register 17
The address range detection signal 23 is output. On the other hand, the trace memory control device 3 receives the trigger address detection signal 22
When the address range detector 19 is enabled, the trace data value 10 is stored in the trace memory.

Problems to be Solved by the Invention However, with the above configuration, there was a problem in that it was impossible to set the trigger address at only one point, apply a sequential trigger, or change the trace conditions during tracing. .

In view of the above, an object of the present invention is to provide a microprocessor tracing device capable of performing various trace controls such as applying a sequential trigger and changing trace conditions during tracing. .

Means for Solving the Problems The present invention includes a plurality of detectors for detecting that data output from a microprocessor each satisfies a predetermined condition, and a detector for detecting output from a specific detector among the detectors. a condition generator that inputs a signal and outputs new conditions to each of the detectors; and a trace that stores data of the microprocessor in a trace memory based on the result of a detection signal output from a specific one of the detectors. A microprocessor trace device having a memory control device.

Operation According to the above-described configuration, when the microprocessor executes a program, the plurality of detectors manually compare the data from the microprocessor and the data from the condition generator, and output detection signals. A certain determined signal line among the output signal lines of the detector is connected to a condition generator, and the condition generator changes the value of output data based on the result of the input signal line. On the other hand, the trace memory control device manually inputs trace data from the microprocessor based on the results of the separately determined output signal line of the detector and stores it in the trace memory. By doing the above, by programming the data output from the condition generator in advance, various trace controls such as sequential triggering become possible.

Embodiment FIG. 1 is a block diagram of a microprocessor tracing device according to the present invention. In FIG. 1, 1 is a microprocessor;
2 is a main memory, 3 is a trace memory control device that stores the trace results of the microprocessor 1, 4 is a ROM that outputs trigger conditions and various trace conditions, and 5 is an address value output by the microprocessor 1 and a trigger output from the ROM 4. A trigger address detector 6a detects a trigger point from a condition value, and 6a is an upper limit that outputs a signal indicating that the upper limit of the trace address is not exceeded from the address value output by the microprocessor 1 and the upper limit trace address value output by the ROM 4. Trace address detector, 6b
is the address value output by microprocessor l and the ROM
A lower limit trace address detector 4 outputs a signal indicating that the lower limit trace address value outputted does not exceed the lower limit value of the trace address, and 7 is a trace outputted by the upper limit trace address detector 6a and the lower limit trace address detector 6b. An AND circuit that detects that all signals indicating that a condition is satisfied are enabled; 8 is a trigger address detector 5 and an upper limit trace address detector 6a;
A trace control device includes a lower limit trace address detector 6b and an AND circuit 7 and outputs a signal to the trace memory control device 3 to perform tracing, 9 is an address value output by the microprocessor l, and 10 is a trace to be stored in the trace memory. data, 11 is a trigger address detection signal, 12 is a trigger address value, 13a is an upper limit trace address value, 13b is a lower limit trace address value, 14a is an upper limit address range detection signal, 14b is a lower limit address range detection signal, 15 is a trace enable signal It is.

The operation of this embodiment configured as described above will be explained below.

Data is stored in the ROM 4 as shown in Figure 2, and initially the trigger address A is output to the trigger address detector 5, the upper limit trace address A is output to the upper limit trace address detector 6a, and the lower limit trace address A is output to the lower limit and trace address detector 6b. be done.

When the microprocessor l executes the program, the upper limit trace address detector 6a and the lower limit trace address detector 6b respectively compare the address value 9 from the microprocessor l and the value input from the ROM 4, and output an upper limit address within range detection signal 14a. and outputs the lower limit address range detection signal 14b. The AND circuit 7 performs a logical product of the upper limit address range detection signal 14a and the lower limit address range detection signal 14b, and outputs a trace enable signal 15 to the trace memory control yI device 3. The trace memory control device 3 stores the trace data 10 from the microprocessor 1 in the memory when the trace enable signal 15 is input manually. Further, the trigger address detector 5 compares the address value 9 from the microprocessor 1 with the manually input value from the ROM 4 and outputs a trigger address detection signal 11. When the detection signal 11 is output, the ROM 4 newly stores the trigger address B, upper limit trace address B, and lower limit trace address B.
are output from the trigger address detector 5, upper limit trace address detector 6a, and lower limit trace address detector 6b, respectively.

As described above, according to this embodiment, the ROM 4 outputs a trigger address value, an upper limit trace address value, and a lower limit trace address value, and outputs a new trigger address value, upper limit trace address value, and lower limit trace address value when a trigger address detection signal is input. By providing , the trace data is written to the trace memory until the trigger address A is output from the processor l, and the trace data is written to the lower limit trace address below the L limit trace address A, and the trace data is stored in the trace memory until the trigger address B is output from the processor l. The trace conditions can be changed during tracing, such that trace data below the upper limit trace address B and above the lower limit trace address B is written.

Note that the RAM is
4 Set the upper limit trace address and lower limit trace address values. For example, the value to the upper limit trace address in FIG. 2 is set to a smaller value than the lower limit trace address A, and the value to the upper limit trace address B is similarly set to a smaller value than the lower limit trace address B. Then, tracing by sequential triggering can be realized such that trace data from the trigger address B that appears after the trigger address A to the trigger address C, which is less than the upper limit trace address C and more than the lower limit trace address C, is written in the trace memory.

As described in detail, the present invention enables various trace controls such as changing trace conditions during tracing and applying sequential triggers, and has great practical effects.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a microprocessor tracing device according to an embodiment of the present invention, FIG. 2 is an explanatory diagram illustrating the storage contents of a ROM in the same embodiment, and FIG. 3 is a conventional microprocessor tracing device. FIG. 2 is a block diagram showing the configuration of FIG. l...Microprocessor, 2...Main memory, 3...
・Trace memory control device, 4...ROM, 5.18
...Trigger address detector, 6a... Upper limit trace address detector, 6b... Lower limit trace address detector, 7... AND circuit, 8... Trace control device,
9...Address value, 10...Trace data value, l
l, 22...Trigger address detection signal, 12.20.
...Trigger address value, 13a...Upper limit trace address value, 13b...Lower limit trace address value, 14a...Upper limit address range detection signal, 14b...Lower limit address range detection signal, 15...Trace Enable signal, 16.17...Register, 19...Address range detector, 21...Address range data value, 23...Address range detection signal. Name of agent: Patent attorney Toshio Nakao (1 person) Figure 1

Claims (1)

[Claims] a plurality of detectors each detecting that data output from the microprocessor satisfies predetermined conditions;
a condition generator that inputs a detection signal output from a specific one of the detectors and outputs a new condition to each of the detectors; and a result of the detection signal output from a specific one of the detectors. and a trace memory control device for storing data of the microprocessor in a trace memory.