JPH01194548A - Speed setting system for start-stop synchronizing type data transmission - Google Patents

Abstract

PURPOSE:To reduce labour of speed setting by measuring the prescribed bit width of start-stop data sent from a data sending means and executing the setting of a data transmitting speed. CONSTITUTION:A data sending means 111 executes the sending of the start-stop data and a bit width measuring means 121 measures the bit width of the prescribed bit including a start bit in the start stop data. A speed setting means 131 executes the setting of the data transmitting speed in correspondence to the measured result of the bit width measuring means 121. Thus, since the prescribed bit width of the start stop data sent from the data sending means 111, is measured and the setting of the data transmitting speed is executed, the labour of the speed setting can be reduced.

Description

[Detailed Description of the Invention] [Summary] The object of the present invention is to reduce the time and effort required to set the speed with respect to a speed setting method for asynchronous data transmission in which the receiver analyzes the received start-stop data and sets the transmission speed. data sending means for sending start-stop data; bit width measuring means for measuring the bit width of a predetermined bit including a start bit in the start-stop data sent from the data sending means; and measurement results by the bit width measuring means. and speed setting means for setting the data transmission speed according to the data transmission speed.

[Industrial Application Field] - The present invention relates to a speed setting method for asynchronous data transmission, and in particular, to a speed setting method for asynchronous data transmission in which a receiver analyzes received start-stop data to set the transmission speed. This is related to the setting method.

[Prior Art] Generally, data communication via a line is performed via a modem. There are several types of modems with different communication speeds depending on modulation methods and the like.

For example, CCITT Recommendation (2) 300 bps or less, (2) 22 is 1200 bps, V,22biS is 2400 bps, and V,32 is 9600 bps.

By the way, the mainstream modems these days are those that allow you to select from several modulation methods (communication speeds).
The operator (user) needs to select and use the desired communication speed.

For example, communication is normally performed at a speed of 2400bps,
When the state of the line deteriorates, a case may be considered in which the speed is changed to 1200 bpS and communication is performed.

[Problem to be solved by the invention]

By the way, in the above-mentioned conventional method, when changing the communication speed, the operator has to change the speed setting of each related communication device, which is a problem in that it is time-consuming.

For example, if a modem is connected to the line and communication equipment such as a data terminal equipment (hereinafter referred to as DTE) is connected to the modem, the operator can change the data communication speed of the DTE, and also change the modem and commands from the DTE. To perform recognition, it is necessary to change the communication speed of the modem.

The present invention was created in view of these points, and an object of the present invention is to provide a speed setting method for asynchronous data transmission that can reduce the time and effort required for speed setting.

[Means to solve the problem]

FIG. 1 is a principle block diagram of a speed setting method for asynchronous data transmission according to the present invention.

In the figure, data sending means 111 sends start-stop data.

The bit width measuring means 121 measures the bit width of predetermined bits including the start bit in the start-stop data sent from the data sending means 111.

The speed setting means 131 is the bit width measuring means 12
The data transmission rate is set according to the measurement result by 'l.

Therefore, the overall configuration is such that the data transmission rate is set by measuring a predetermined bit width of the start-stop data.

[For production]

The data sending means 111 sends start-stop data, and the bit width measuring means 121 measures the bit width of predetermined bits including the start bit in the start-stop data. The speed setting means 131 sets the data transmission speed according to the measurement result of the bit width measuring means 121.

In the present invention, by measuring the predetermined bit width of the start-stop data sent from the data sending means 111 and setting the data transmission speed, it is possible to reduce the effort required to set the speed.

[Example] Hereinafter, an example of the present invention will be described in detail based on the drawings.

FIG. 2 shows the configuration of an embodiment to which the speed setting method for asynchronous data transmission of the present invention is applied.

1. Correspondence between the embodiment and FIG. 1 Here, the correspondence between the embodiment of the present invention and FIG. 1 will be shown.

The data sending means 111 corresponds to the DTE 211.

The bit width measuring means 121 is a D-type flip-flop (D
-FF) 221. Orgate 223. counter 225
．． It corresponds to the clock generation section 241.

The speed setting means 131 includes a ROM 231. counter 233
9 communication LSI235. Microprocessor (MPU)
It corresponds to 237.

Examples of the present invention will be described below assuming that the correspondence relationship as described above exists.

(2) Configuration of the Embodiment In FIG. 2, the DTE 211 is connected to a modem 220 that modulates the transmission data from the DTE 211 and sends it to the line side, and also demodulates the signal received from the line side and supplies it to the DTE 211. ing.

The modem 220 has an M which performs overall control of the modem 220.
A PU 237, a modulation/demodulation section 251 that modulates or demodulates communication data, a communication LSI 235 that controls data communication via the modulation/demodulation section 251, a delay circuit 239 for delaying data input from the DTE 211, and a reference. A clock generating section 2 generates a clock signal as follows.
41, two counters 225 and 233, a ROM 231 that stores data regarding communication speed settings, and a D-FF.
221 and an or gate 223.

The data supplied from the DTE 211 to the modem 220 is
Modulation/demodulation section 251. Delay circuit 239. Both are input to the clock terminal CK of the D-FF 221 and one input terminal of the OR gate 223. Data input from the DTE 211 to the delay circuit 239 is input to the communication LSI 235 after being delayed by the delay circuit 239 for a predetermined time. D-FF221
Fixed data ``1''' is input to the input terminal of .

The output terminal Q of the D-FF 221 is connected to the other input terminal of the OR gate 223, and the output terminal of the OR gate 223 is connected to the enable terminal EN of the counter 225. Note that data is supplied to the enable terminal EN of the counter 225 in negative logic.

The clock signal generated by the clock generator 241 is input to the clock terminal CK of the counter 225 and the counter 233.

The binary output terminal of the counter 225 is connected to the ROM 231.
It is connected to the address input terminal of the MPU 237 and the input terminal of the MPU 237. A data output terminal of the ROM 231 is connected to a preset input terminal of the counter 233. Also,
The carry-out terminal CO of the counter 233 is connected to the load terminal of the counter 233 itself and the clock terminal CK of the communication LSI 235.

The communication LSI 235 and the MPU 237 are connected by a bus, and the data output from the binary output terminal of the counter 225 is supplied to this bus.

The MPU 237 and the modulation/demodulation section 251 are connected, and the
The modulation/demodulation speed change instruction from U237 is supplied to the modulation/demodulation section 251 via this connection line.

Further, a setting start pulse is commonly input from the output port PO of the MPU 237 to the D-FF 221 and the clear terminal CLR of the counter 225 (both are negative logic). MPU23
A setting completion signal is supplied from the inverted output terminal d of the D-FF 221 to the input port PI of No. 7.

1- Disaster Management and Combustion Study Next, the operation of the speed setting method for asynchronous data transmission according to the embodiment of the present invention described above will be explained.

(i) Principle of Speed Steps First, the principle of setting the transmission speed based on start-stop data sent from the DTE 211 to the modem 220 will be explained.

Figure 3 shows how to set the speed. Prior to normal data communication, the DTE 211 sends start-stop data for speed setting to the modem 220. FIG. 3(A) shows start-up data for speed setting. A start bit "0", a predetermined number of data bits (for example, 8 bits), and a stop bit "1" are sent in this order.

As shown in FIG. 3(b), when the least significant bit D0 of the data bit is "1", the start bit width L0 is:
This is the time from when the data from the DTE 211 changes from "1" to "0" and then from "OI+" to "1".

Therefore, by finding the reciprocal 1/L0 of the bit width t0, the communication speed of data sent from the DTE 211 can be easily recognized.

In addition, in FIG. 3(C), the least significant bit D0 of the data is “
0'', the second bit from the bottom is l''.

Let tl be the 2-bit width including the start bit and the least significant bit D0 of the data.

By measuring this 2-bit width t1 and finding 2/L, the data transmission speed can be easily recognized.

Incidentally, if the data is expressed in ASCII code, in (b), data A, C, E.

# etc. are used, and in (c) data B, F, J.

& etc. may be used.

(ii) Detailed operation of speed setting Next, detailed operation of communication speed setting in modem 220 shown in FIG. 2 will be explained.

FIG. 4 shows the operation timing of the embodiment. In the figure, "data" indicates start-stop data sent from the DTE 211 for speed setting, and is, for example, data A expressed in ASCII code. In addition, "setting start pulse" is the data output from the output port PO of the MPU 237, "unchi output Q" is the data output from the output terminal Q of the D-FF 221, and "gate output" is the data output from the OR gate 223. The output and "setting end signal" are D-FF22
The data output from the inverted output terminal d of No. 1 are respectively shown.

Moreover, FIG. 5 shows the operating procedure of the MPU 23'7 of the embodiment.

Hereinafter, reference will be made to FIGS. 2 to 5.

First, the MPU 237 sends a setting start pulse to the D-FF 22.
1 and the clear terminal CLH of the counter 225 (step 511).

Next, the MPU 237 enters a waiting state (step 512).

When the setting pulse signal is input to the clear terminal CLR, D
-The output of FF221 is reset.

Therefore, the data “°0pa” is output from the output terminal Q,
The data “0” is input to one input terminal of the OR gate 223.

In addition, fixed data “1” is input to the input terminal of D-FF221.
°” is input, and the start-stop data input from the DTE211 is input to the clock terminal CK, so it is synchronized with the end of the start bit of the start-stop data (synchronized with the switching from data “0” to “1”). ), data "l" is output from the output terminal Q.

The start-stop data from the DTE 211 is also input to the other input terminal of the OR gate 223, so the OR gate 223
The data ladder "0°" is outputted from the output terminal corresponding to the start bit of the start-stop data, and the data "1" is outputted corresponding to other than the start bit.

Since the output of the OR gate 223 is supplied to the enable terminal EN of the counter 225, the counter 225 is enabled only during the time to (to is equal to the start bit width) corresponding to the start bit of the start-stop data. At this time, a clock signal from the clock generator 241 is supplied to the clock terminal CK of the counter 225, and a counting operation is performed in synchronization with the clock signal.

Furthermore, from the inverted output terminal d of the D-FF 221, the MPU 237 outputs the counter 2 in synchronization with the end of the start bit.
25 is taken in (step 513).

Assuming that the period T of the clock signal output from the clock generator 241 is sufficiently faster than the communication speed of start-stop data (for example, 64 times the frequency), the MPU 237 outputs binary data corresponding to the count value "64" from the counter 225. Incorporate.

Next, the MPU 237 outputs the captured binary data “
64" (step 5).
14). The period T of the clock signal output from the clock generator 241 is known in advance, and the communication speed is 1/(6
4T).

Further, the binary data "64" outputted from the counter 225 is inputted to the ROM 231 as address data. The ROM 231 supplies certain data stored at the corresponding address to the counter 233, and the counter 233 outputs an output pulse having a time width corresponding to the supplied data from the carry-out terminal CO.

This output pulse is supplied to the clock terminal CK of the communication LSI 235 and also to the load terminal of the counter 233 itself. When an output pulse is input to the load terminal of the counter 233, an output pulse with a time width corresponding to the data output from the ROM 231 is output again, so the counter 233 functions as a frequency divider according to the data from the ROM 231. I will be working.

Therefore, the data stored in the ROM 231 is set so that the counter 233 outputs an output pulse with a frequency of 1/(64T).

Next, the communication LSI 235 reads the data A delayed by the delay circuit 239 in synchronization with the output pulse output from the counter 233 and outputs it to the MPU 237 . M.P.
The U237 reads the manually input data from the communication LSI 235 (step 515), and determines whether the data is equal to data A predetermined for speed setting (step 516).

When the data input from the communication LSI 235 is equal to data A, the MPU 237 makes an affirmative determination and ends the process. Thereafter, the communication LSI 235 is used as the counter 233.
The modulation/demodulation section 251 performs a modulation/demodulation operation under the control of the MPU 237.

If the determination in step 516 is negative (is the data correct?), the MPU 237 outputs the setting start pulse again from the output port PO, and repeats the communication speed setting operation from step 511 onwards.

■Summary of the Example In this way, the start-stop data for setting the communication speed can be transferred to the DTE21.
1 to the modem 220. The counter 225 of the modem 220 calculates a count value corresponding to the start bit of the start-stop data. The MPU 237 determines the speed of the start-stop data input from the DTE 211 based on the count output from the counter 225. In addition, the counter 23
3 outputs an output pulse corresponding to the speed of the start-stop data input from the DTE 211 to the communication LSI 235 based on the count output from the counter 225 .

Next, the communication LSI 235 reads the start-stop data sent from the DTE 211 in synchronization with the output pulse of the counter 233, and when the data is equal to the predetermined communication speed setting data A, the MPU 237 , the speed setting process ends.

Therefore, by measuring the start bit width of the start-stop data and setting the communication speed, it is possible to reduce the troublesome and erroneous operation when setting the speed.

Furthermore, since the communication speed in the modem 220 can be set simply by supplying start-stop data from the DTE 211 to the modem 220, it is more effective in preventing erroneous operations than when setting the speed by operator operation.

■8 Modifications of the invention In the embodiment of the invention described above, DTE21
Although a delay circuit 239 is provided to check whether the data sent from 1 to the modem 220 matches predetermined data, the delay circuit 239 is not required if confirmation is not necessary.

In addition, in ``correspondence between Examples and Figure 1'',
Although the correspondence between the present invention and the embodiments has been described, those skilled in the art will easily assume that the present invention is not limited to this and that there are various modifications.

〔Effect of the invention〕

As described above, according to the present invention, by measuring the predetermined bit width of the pace data sent from the data sending means and setting the data transmission speed, it is possible to reduce the effort required for speed setting. , which is extremely useful in practice.

[Brief explanation of the drawing]

FIG. 1 is a principle block diagram of the speed setting method for asynchronous data transmission according to the present invention. FIG. 2 is a block diagram of an embodiment to which the speed setting method for asynchronous data transmission according to the present invention is applied. 4 is an operational timing diagram of the embodiment. FIG. 5 is an explanatory diagram of the operation of the MPU of the embodiment. In the figure, 111 is a data sending means, 121 is a bit width measuring means, 131 is a speed setting means, and 211 is a DTE. 220 is a modem, 221 is a D-FF. 223 is an OR gate, 225.233 is a counter, and 231 is a ROM. 235 is a communication LSI. 237 is MPU. 239 is a delay circuit, 241 is a clock generation section, and 251 is a modulation/demodulation section. The book is also clear. 1. ri-mura Figure 1 (c) Electricity T-Cliff Enthusiasm eR1 Shumei Exit Figure 3: : U, Drop o-hee:-''-1--: : Figure 4

Claims (1)

[Claims] (1) Data sending means (11
1), a bit width measuring means (121) for measuring the bit width of a predetermined bit including a start bit in the start-stop data sent from the data sending means (111), and a bit width measuring means (121) Speed setting means (131) for setting the data transmission speed according to the measurement results
), and a speed setting method for asynchronous data transmission.