JPH01191451A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH01191451A JPH01191451A JP63014435A JP1443588A JPH01191451A JP H01191451 A JPH01191451 A JP H01191451A JP 63014435 A JP63014435 A JP 63014435A JP 1443588 A JP1443588 A JP 1443588A JP H01191451 A JPH01191451 A JP H01191451A
- Authority
- JP
- Japan
- Prior art keywords
- film
- contact hole
- ccb
- wafer
- deposited
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 16
- 238000004519 manufacturing process Methods 0.000 title claims description 6
- 238000000034 method Methods 0.000 claims description 9
- 229910001174 tin-lead alloy Inorganic materials 0.000 claims 1
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 10
- 229910000679 solder Inorganic materials 0.000 abstract description 7
- 239000011651 chromium Substances 0.000 abstract description 5
- 239000011521 glass Substances 0.000 abstract description 5
- 239000010931 gold Substances 0.000 abstract description 5
- 239000010949 copper Substances 0.000 abstract description 4
- 229910052718 tin Inorganic materials 0.000 abstract description 4
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 abstract description 3
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 abstract description 3
- 229910052804 chromium Inorganic materials 0.000 abstract description 3
- 229910052737 gold Inorganic materials 0.000 abstract description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 abstract description 2
- 229910052802 copper Inorganic materials 0.000 abstract description 2
- 238000010438 heat treatment Methods 0.000 abstract description 2
- 238000001039 wet etching Methods 0.000 abstract description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 2
- 238000005530 etching Methods 0.000 abstract 2
- 229910052581 Si3N4 Inorganic materials 0.000 abstract 1
- 229910052681 coesite Inorganic materials 0.000 abstract 1
- 229910052906 cristobalite Inorganic materials 0.000 abstract 1
- 239000000377 silicon dioxide Substances 0.000 abstract 1
- 235000012239 silicon dioxide Nutrition 0.000 abstract 1
- 229910052682 stishovite Inorganic materials 0.000 abstract 1
- 229910052905 tridymite Inorganic materials 0.000 abstract 1
- 230000002093 peripheral effect Effects 0.000 description 8
- 230000000694 effects Effects 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 3
- 230000001681 protective effect Effects 0.000 description 3
- 239000008188 pellet Substances 0.000 description 2
- 244000126211 Hericium coralloides Species 0.000 description 1
- 229910005091 Si3N Inorganic materials 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical group [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 239000010410 layer Substances 0.000 description 1
- 229910052745 lead Inorganic materials 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1301—Shape
- H01L2224/13012—Shape in top view
- H01L2224/13015—Shape in top view comprising protrusions or indentations
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1301—Shape
- H01L2224/13016—Shape in side view
- H01L2224/13018—Shape in side view comprising protrusions or indentations
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1302—Disposition
- H01L2224/13022—Disposition the bump connector being at least partially embedded in the surface
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、ＣＣＢバンブを有する半導体装置の製造技術
に関し、ＣＣＢバンプの接続信頼性向上に適用して有効
な技術に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a technology for manufacturing a semiconductor device having a CCB bump, and relates to a technology effective when applied to improving the connection reliability of the CCB bump.
アルミニウム（Ａｌ）電極上に接合されたＣＣＢバンプ
（Ｂｕｍｐ、突起電極）を介して半導体ペレットを実装
基板などにフェイスダウンボンディングする、いわゆる
フリップチップは、半導体装置の高密度実装に好適な実
装方式として注目されている。The so-called flip-chip method, in which semiconductor pellets are face-down bonded to a mounting board through CCB bumps bonded to aluminum (Al) electrodes, is a mounting method suitable for high-density mounting of semiconductor devices. Attention has been paid.
上記ＣＣＢバンプの形成法については、１９７５年、マ
グロウヒル社（ＭｃＧｒａｗ−Ｈｉｌｌ、 Ｉｎｃ ）
発行、「ベーシック・インチグレーティラド・サーキッ
） ・ｘ ７シ＝７ ’Ｊ ン”（ＢＡＳＩＣＩＮＴＥ
ＧＲＡＴＥ［ｌ ＣＩＲＣＩＪ【ＴεＮＧＩＮＥ［１Ｒ
ＩＮＧ） Ｊ Ｐ Ｉ Ｇ ４〜Ｐ１０６に記載があ
る。The method for forming the above CCB bump was described in 1975 by McGraw-Hill, Inc.
Published by ``BASICINTE
GRATE[l CIRCIJ[TεNGINE[1R
ING) JPIG 4 to P106.
その概要は、半導体ウェハ（以下、ウエノ＼という）の
Ａｌ配線を覆っている表面保護膜にコンタクトホールを
形成し、このコンタクトホール内にクロム（Ｃｒ）／銅
（Ｃｕ）／金（Ａｕ）などの金属層からなる下地膜（Ｂ
Ｌ Ｍ ； Ｂｕｍｐ Ｌｉｍｉｔｔｉｎ−ｇ Ｍｅ
ｔａｌｌｕｒｇｙ）を被着形成した後、さらにこの下地
膜の表面にスズ（Ｓｎ）／鉛（ｐｂ）合金などの半田を
選択的に蒸着し、次いで、リフロー炉内でウェットバッ
クを行って球状のＣＣＢバンプを形成するというもので
ある。The outline is that a contact hole is formed in the surface protection film covering the Al wiring of a semiconductor wafer (hereinafter referred to as Ueno), and in this contact hole, chromium (Cr)/copper (Cu)/gold (Au), etc. Base film (B
LM; Bump Limitin-g Me
After depositing a solder such as a tin (Sn)/lead (PB) alloy on the surface of this base film, wet backing is performed in a reflow oven to form a spherical CCB. This is to form a bump.
しかしながら、上記フリップチップにおいては、エレク
トロマイグレーションによるＣＣＢバンプの接続信頼性
の低下、という問題が指摘されている。However, it has been pointed out that the above-mentioned flip chip has a problem in which the connection reliability of the CCB bumps decreases due to electromigration.
すなわち、ＣＣＢバンブ内を大電流が流れると、ＣＣＢ
バンプを構成するＳｎ原子やＰｂ原子が移動する、いわ
ゆるエレクトロマイグレーションが発生するが、ＣＣＢ
バンブ内を流れる電流の密度がＣＣＢバンプの中心部よ
りも周縁部（表層部）でより高くなる傾向があるため、
周縁部のＳｎ原子やＰｂ原子が移動してそこに空隙部が
生じ易くなる。In other words, when a large current flows through the CCB bump, the CCB
So-called electromigration occurs, in which the Sn and Pb atoms that make up the bump move, but CCB
Because the density of the current flowing inside the bump tends to be higher at the periphery (surface layer) than at the center of the CCB bump,
Sn atoms and Pb atoms in the peripheral area move and tend to form voids there.
そして、この空隙部が次第に成長し、ＣＣＢバンプにク
ラックが生じて導通不良を引き起こすなど、ＣＣＢバン
プの接続信頼性が寿命が低下してしまうことになる。Then, this void gradually grows, causing cracks to occur in the CCB bump and causing poor conduction, resulting in a reduction in the connection reliability of the CCB bump over its lifetime.
このような、ＣＣＢバンブの周縁部に発生するエレクト
ロマイグレーションについては、例えば、「昭和５６年
度電子通信学会半導体材料部門全国大会・“大規模マル
チチップモジュールの接続部でのエレクトロマイグレー
ション発生の考察”」などにおいて指摘されているが、
このエレクトロマイグレーションに起因するＣＣＢバン
プの接続信頼性の低下を有効に防止する対策は未だ見出
されていないのが現状である。Regarding electromigration that occurs at the periphery of CCB bumps, see, for example, ``1982 Institute of Electronics and Communication Engineers, Semiconductor Materials Division National Conference, ``Consideration of Electromigration Occurrence at Connections of Large-Scale Multichip Modules.'' Although it has been pointed out in
At present, no countermeasure has yet been found to effectively prevent the reduction in connection reliability of CCB bumps caused by electromigration.
本発明の目的は、上記したエレクトロマイグレーション
に起因するＣＣＢバンブの接続信頼性の低下を有効に防
止することができる技術を提供することにある。An object of the present invention is to provide a technique that can effectively prevent the deterioration in connection reliability of CCB bumps caused by the electromigration described above.
本発明の前記ならびにその他の目的と新規な特徴は、本
明細書の記述および添付図面から明らかになるであろう
。The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.
本願において開示される発明のうち代表的なものの概要
を簡単に説明すれば、次の通りである。A brief overview of typical inventions disclosed in this application is as follows.
すなわち、半導体ウェハの表面保護膜に開口形成された
コンタクトホール内に下地膜を被着形成してその表面に
ＣＣＢバンプを接合するに際し、上記コンタクトホール
をその内周長が長くなるような形状とするものである。That is, when a base film is deposited in a contact hole formed in a surface protection film of a semiconductor wafer and a CCB bump is bonded to the surface of the base film, the contact hole is shaped so that its inner circumference becomes long. It is something to do.
上記した手段によれば、コンタクトホール内の下地膜表
面に接合されるＣＣＢバンブの外周長が長くなるため、
■体積が等しい球状のＣＣＢバンブと比較すると、周縁
部の体積が中心部の体積に比べて相対的に大きくなる。According to the above-described means, since the outer circumference of the CCB bump bonded to the surface of the base film in the contact hole becomes longer,
■Compared with a spherical CCB bump with the same volume, the volume at the periphery is relatively larger than the volume at the center.
■また、コンタクトホール内の面積が等しいＣＣＢバン
ブと比較すると周縁部面積が大きくなる。(2) Also, the area of the periphery is larger than that of the CCB bump, which has the same area within the contact hole.
これにより、■ＣＣＢバンプの周縁部に流れる電流密度
が相対的に低くなるため、周縁部でのエレクトロマイグ
レーションの発生が防止される。As a result, the current density flowing at the peripheral edge of the CCB bump becomes relatively low, so that electromigration can be prevented from occurring at the peripheral edge.
■また、コンタクトホール部の接触抵抗も低い状態に保
存できる。■Also, the contact resistance of the contact hole can be kept low.
第１図（ａ）〜（ｄ）は、本発明の一実施例である半導
体装置の製造方法を工程順に示すものであり、第１図（
ａ）、 （Ｃ）および（６）は、ウェハの要部断面図、
第１図（ｂ）は、コンタクトホールの形状を示すウェハ
の要部拡大斜視図である。FIGS. 1(a) to 1(d) show a method for manufacturing a semiconductor device according to an embodiment of the present invention in order of steps, and FIG.
a), (C) and (6) are sectional views of main parts of the wafer,
FIG. 1(b) is an enlarged perspective view of the main part of the wafer showing the shape of the contact hole.
まず、通常のウェハプロセスに従っテウエハ１の回路形
成領域に所定の集積回路パターン（図示せず）を形成し
、その表面に、例えば、プラズマＣＶＤ法により５ｉｓ
Ｎａ膜２を被着形成する。First, a predetermined integrated circuit pattern (not shown) is formed in the circuit formation area of the wafer 1 according to a normal wafer process, and a 5is pattern is formed on the surface thereof by, for example, plasma CVD.
A Na film 2 is deposited and formed.
次いで、ホトレジスト／ドライエツチングにより、上記
Ｓｉ３Ｎ、膜２の所定個所を穴開けしてＡｌ配線３を露
出させた後、例えば、スパッタリーングにより、ウェハ
１の表面に５ｉｎ２からなるガラス保護膜４を被着形成
する（第１図（ａ））。Next, by photoresist/dry etching, holes are made at predetermined locations in the Si3N film 2 to expose the Al wiring 3, and then, for example, a glass protective film 4 of 5 in 2 is formed on the surface of the wafer 1 by sputtering. Adhesion is formed (FIG. 1(a)).
次いで、上記ガラス保護膜４０表面にホトレジストを被
着形成し、これをマスクとしてウェットエツチングを行
い、コンタクトホール５を形成する。Next, a photoresist is deposited on the surface of the glass protective film 40, and wet etching is performed using this as a mask to form a contact hole 5.
その際、上記ホトレジストのマスクバ５１−”Ｊ’ｆ：
（し歯状とすもことにより、第１図ら）に示すように、
平面形状がクシ歯状をなすコンタクトホール５が得られ
る。At that time, the photoresist mask bar 51-"J'f:
As shown in Fig. 1, etc.,
A contact hole 5 having a comb-like planar shape is obtained.
このようにして得られたコンタクトホール５は、その内
壁に多数の凹凸面が形成されるため、従来のような円形
のコンタクトホールと比較すると、容積が同一であって
も、その内周長が遥かに長いものとなる。The contact hole 5 obtained in this way has many uneven surfaces on its inner wall, so compared to a conventional circular contact hole, even if the volume is the same, the inner circumference length is It will be much longer.
次に、上記コンタクトホール５の内周面に、例えば、ク
ロム（Ｃｒ）／＠ （Ｃｕ）／金（Ａｕ）などの薄い金
属層からなる下地膜６を蒸着形成した後、ウェハ１の表
面にホトレジスト７を被着形成し、エツチングによりコ
ンタクトホール５の上方を開口して下地膜６を露出させ
、その表面にスズ（Ｓｎ）および鉛（Ｐｂ）かろなる半
田膜８を蒸着形成する（第１図（Ｃ））。Next, a base film 6 made of a thin metal layer such as chromium (Cr)/@(Cu)/gold (Au) is formed by vapor deposition on the inner peripheral surface of the contact hole 5, and then the base film 6 is formed on the surface of the wafer 1. A photoresist 7 is deposited and etched to open above the contact hole 5 to expose the base film 6, and a solder film 8 made of tin (Sn) and lead (Pb) is deposited on the surface of the base film 6 (the first Figure (C)).
次いで、上記ホトレジスト７およびその表面に被着した
不要の半田膜８をリフト・オフ法によって除去した後、
ウェハ１をリフロー炉内に搬入して半田膜８を溶融加熱
することにより、ＣＣＢバンプ９が形成される。Next, after removing the photoresist 7 and the unnecessary solder film 8 attached to its surface by a lift-off method,
The CCB bumps 9 are formed by carrying the wafer 1 into a reflow furnace and melting and heating the solder film 8.
このように、コンタクトホール５の平面形状かくし歯状
となったウェハ１をベレットに分割して実装基板などに
搭載することにより、下記のような効果を得ることがで
きる。In this way, the following effects can be obtained by dividing the wafer 1, in which the contact holes 5 have a comb-tooth shape in plan view, into pellets and mounting them on a mounting board or the like.
（１）、平面形状がくし歯状をなすコンタクトホール５
の内部に形成されたＣＣＢバンプ９は、その外周長が長
くなるため、体積が等しい球状のＣＣＢバンプと比較し
た場合、周縁部の体積が中心部の体積に比べて相対的に
大きくなる。(1) Contact hole 5 with a comb-like planar shape
Since the CCB bump 9 formed inside has a longer outer circumference, the volume at the periphery is relatively larger than the volume at the center when compared with a spherical CCB bump having the same volume.
また、コンタクトホール内の面積が等しいＣＣＢバンプ
と比較すると、周縁部面積が大きくなる。Furthermore, the area of the peripheral portion is larger than that of a CCB bump having the same area within the contact hole.
これにより、ＣＣＢバンブ９の内部を電流が流れる際、
その周縁部の電流密度が相対的に低くなるため、周縁部
におけるエレクトロマイグレーションの発生が防止され
る。As a result, when current flows inside the CCB bump 9,
Since the current density at the periphery is relatively low, electromigration is prevented from occurring at the periphery.
（２）、上記（１）により、ＣＣＢバンプの接続信頼性
および寿命が向上し、信頼性の高い半導体装置が得られ
る。(2) According to the above (1), the connection reliability and life of the CCB bump are improved, and a highly reliable semiconductor device can be obtained.
また、コンタクトホール部の接触抵抗も低い状態に保存
できる。Further, the contact resistance of the contact hole portion can also be kept low.
以上、本発明者によってなされた発明を実施例に基づき
具体的に説明したが、本発明は前記実施例に限定される
ものではなく、その要旨を逸脱しない範囲で種々変更可
能であることはいうまでもない。As above, the invention made by the present inventor has been specifically explained based on Examples, but it should be noted that the present invention is not limited to the Examples and can be modified in various ways without departing from the gist thereof. Not even.
例えば、コンタクトホールは、その内周長の長い形状で
あれば、くし歯状のものに限定されるものではなく、そ
れ以外の種々の形状のものが適用可能である。For example, the contact hole is not limited to a comb-like shape as long as its inner circumference is long, and various other shapes are applicable.
例えば、第２図（ａ）、（ｂ）に示すような平面形状を
有するコンタクトホールにおいても、その内周長が球状
のＣＣＢバンプのそれよりも長くなるため、前記実施例
と同様の効果が得られる。For example, even in a contact hole having a planar shape as shown in FIGS. 2(a) and 2(b), the inner circumference is longer than that of a spherical CCB bump, so the same effect as in the above embodiment can be obtained. can get.
本願において開示される発明のうち代表的なものによっ
て得られる効果を簡単に説明すれば、下記の通りである
。A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.
すなわち、半導体ウェハの表面保護膜に開口形成された
コンタクトホール内に下地膜を被着形成してその表面に
ＣＣＢバンプを接合するに際し、上記コンタクトホール
をその内周長が長くなるような形状とすることにより、
このコンタクトホール内に形成されるＣＣＢバンブの外
周長が長くなるため、周縁部の体債が中心部の体積に比
べて相対的に大きいＣＣＢバンブが得られる。That is, when a base film is deposited in a contact hole formed in a surface protection film of a semiconductor wafer and a CCB bump is bonded to the surface of the base film, the contact hole is shaped so that its inner circumference becomes long. By doing so,
Since the outer circumferential length of the CCB bump formed in the contact hole becomes longer, a CCB bump whose peripheral portion has a relatively larger volume than the center portion can be obtained.
その結果、ＣＣＢバンプ内の周縁部に流れる電流密度が
相対的に低くなり、周縁部でのエレクトロマイグレーシ
ョンの発生が防止されることから、ＣＣＢバンプの接続
信頼性が向上する。As a result, the current density flowing in the peripheral portion of the CCB bump becomes relatively low, and electromigration is prevented from occurring in the peripheral portion, thereby improving the connection reliability of the CCB bump.
第１図（ａ）〜（ｄ）は本発明の一実施例である半導体
装置の製造方法を工程順に示すもの、
第１図（ａ）、 （Ｃ）および（社）はウェハの要部断
面図、第１図ら）はコンタクトホールの形状を示すウェ
ハの要部拡大斜視図、
第２図（ａ）、（ｂ）は本発明の他の実施例におけるコ
ンタクトホールの形状を示す平面図である。
１・・・半導体ウェハ、２・・Ｓｉ、Ｎ、膜、３・・・
Ａｌ配線、４・・・ガラス保護膜、５・・・コンタクト
ホール、６・・・下地膜、７・・・ホトレジスト、８・
・・半田膜、９・・・ＣＣＢバンプ。
第２図
（ａ） （ｂ）FIGS. 1(a) to (d) show a method for manufacturing a semiconductor device according to an embodiment of the present invention in order of steps. FIGS. 1 and 2) are enlarged perspective views of essential parts of a wafer showing the shape of contact holes, and FIGS. 2(a) and 2(b) are plan views showing the shapes of contact holes in other embodiments of the present invention. . 1... Semiconductor wafer, 2... Si, N, film, 3...
Al wiring, 4... Glass protective film, 5... Contact hole, 6... Base film, 7... Photoresist, 8...
...Solder film, 9...CCB bump. Figure 2 (a) (b)
Claims (1)
ール内に下地膜を被着形成してその表面にＣＣＢバンプ
を接合するに際し、前記コンタクトホールの内周長を長
くすることを特徴とする半導体装置の製造方法。 ２、ＣＣＢバンプがスズ−鉛合金からなることを特徴と
する特許請求の範囲第１項記載の半導体装置の製造方法
。[Claims] 1. When a base film is deposited in a contact hole formed on the surface of a semiconductor wafer and a CCB bump is bonded to the surface, the inner circumference of the contact hole is lengthened. A method for manufacturing a semiconductor device, characterized by: 2. The method of manufacturing a semiconductor device according to claim 1, wherein the CCB bump is made of a tin-lead alloy.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63014435A JPH01191451A (en) | 1988-01-27 | 1988-01-27 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63014435A JPH01191451A (en) | 1988-01-27 | 1988-01-27 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01191451A true JPH01191451A (en) | 1989-08-01 |
Family
ID=11860938
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63014435A Pending JPH01191451A (en) | 1988-01-27 | 1988-01-27 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01191451A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5576748A (en) * | 1990-02-26 | 1996-11-19 | Canon Kabushiki Kaisha | Recording head with through-hole wiring connection which is disposed within the liquid chamber |
| US7355280B2 (en) | 2000-09-04 | 2008-04-08 | Seiko Epson Corporation | Method for forming a bump, semiconductor device and method of fabricating same, semiconductor chip, circuit board, and electronic instrument |
| JP2013102013A (en) * | 2011-11-08 | 2013-05-23 | Toyota Motor Corp | Manufacturing method of semiconductor device and semiconductor device |
| EP3168872A3 (en) * | 2015-11-12 | 2017-06-07 | MediaTek Inc. | Semiconductor package assembley |
| JP2021190704A (en) * | 2020-05-26 | 2021-12-13 | 株式会社村田製作所 | Electronic component with component interconnect element |
-
1988
- 1988-01-27 JP JP63014435A patent/JPH01191451A/en active Pending
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5576748A (en) * | 1990-02-26 | 1996-11-19 | Canon Kabushiki Kaisha | Recording head with through-hole wiring connection which is disposed within the liquid chamber |
| US7355280B2 (en) | 2000-09-04 | 2008-04-08 | Seiko Epson Corporation | Method for forming a bump, semiconductor device and method of fabricating same, semiconductor chip, circuit board, and electronic instrument |
| US7579692B2 (en) | 2000-09-04 | 2009-08-25 | Seiko Epson Corporation | Method for forming a bump, semiconductor device and method of fabricating same, semiconductor chip, circuit board, and electronic instrument |
| JP2013102013A (en) * | 2011-11-08 | 2013-05-23 | Toyota Motor Corp | Manufacturing method of semiconductor device and semiconductor device |
| EP3168872A3 (en) * | 2015-11-12 | 2017-06-07 | MediaTek Inc. | Semiconductor package assembley |
| JP2021190704A (en) * | 2020-05-26 | 2021-12-13 | 株式会社村田製作所 | Electronic component with component interconnect element |
| US11527497B2 (en) | 2020-05-26 | 2022-12-13 | Murata Manufacturing Co., Ltd. | Electrical component with component interconnection element |
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