JPH01189958A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To miniaturize cell and obtain large capacity, by stacking, on a substrate, via an interlayer insulating film, at least two wiring layers wherein a plurality of lines mutually intersect. CONSTITUTION:Data are stored by depending on whether rectifying contacts directly formed between laminated wiring layers 3, 5, 7 exist. Therefore, as compared with the case, for example, installing P-N junction cells by forming diffusion layers on a semiconductor substrate 1 in accordance with a data pattern, the miniaturization is facilitated. Further it is not necessary to form an insulating film for element isolation on a substrate 1, by utilizing all the deposited films on the substrate 1. Therefore, it is also easy to realize a large capacity ROM. By stacking wiring layers in the manner of multilayer, a memory array can be foremd by arranging MA1 and MA2 in multilayer, that is, 3-dimensional arrangement is facilitated, which largely contributes to the realization of a large capacity ROM. Thereby, the miniaturization of cell is attained by a simple structure, and a mask ROM of large capacity can be obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object 1 of the Invention] (Field of Industrial Application) The present invention relates to a semiconductor memory device, and particularly to a read-only memory (ROM) in which data is written in a fixed manner.

(Prior Art) Conventionally, as this type of ROM, there are mask ROM, in which data is written in the element formation process using a mask forming a diffusion layer, and programmable ROM (FROM), in which data is written electrically after the element is formed. It is being These memory cell structures vary widely. Among these various ROMs,
As a semiconductor ROM having a simple cell structure and suitable for increasing capacity, a semiconductor ROM in which a pn junction diode array is formed on a semiconductor substrate according to a data pattern has been proposed (for example, Japanese Patent Application Laid-Open No. 60-74669). However, in a structure in which a pn junction diode is formed in advance on a semiconductor substrate, fine control of the diffusion region is required, and it is essential to form an element isolation insulating film on the substrate. There is a limit to how large the capacity can be increased.

(Problems to be Solved by the Invention) As described above, conventional semiconductor ROMs have had difficulties in miniaturizing cells and increasing capacity for two people.

It is an object of the present invention to provide a semiconductor ROM which solves these difficulties and enables miniaturization of cells and increase in capacity.

[Structure of the Invention] (Means for Solving the Problems) A ROM according to the present invention has a structure in which at least two interconnection layers, each having a plurality of wiring layers intersecting each other, are laminated on a substrate via an interlayer insulating film. have The adjacent upper wiring layer and lower wiring layer are made of semiconductors of different conductivity types or of different materials. Each intersection between the upper wiring layer and the lower wiring layer is a memory cell, and at each intersection, depending on the data, the upper wiring layer and the lower wiring layer are in direct contact or capacitively coupled via an interlayer insulating film. ,
A rectifying contact is made at the part where there is direct contact.

There are two types of data writing methods. One method is to form an interlayer insulating film on a lower wiring layer, and then form a contact hole in the interlayer insulating film using a mask corresponding to a data pattern to form an upper wiring layer. This is mask R
Similar to the OM method, data is written during the element formation process. The other method is to form an upper wiring layer without making a contact hole in the interlayer insulating film, and then apply a predetermined voltage between the upper wiring layer and the lower wiring layer selected according to the data to electrostatically charge the interlayer insulating film. By breaking, a rectifying contact is made between the upper wiring layer and the lower wiring layer at that part. This is a FROM approach.

In either writing method, a pn junction is not formed in advance as a memory cell by a diffusion method or the like.

That is, in the present invention, rectifying contact is formed between wiring layers only after the formation of the upper wiring layer or subsequent breakdown of the interlayer insulating film. Therefore, it is essential to use different conductivity types or different materials between the upper wiring layer and the lower wiring layer.

(Function) In the ROM of the present invention, data is stored depending on the presence or absence of rectifying contact formed directly between stacked wiring layers. Therefore, compared to, for example, forming a pn junction cell on a semiconductor substrate by forming a diffusion layer in accordance with a data pattern, cell miniaturization is easier. If a film deposited entirely on the substrate is used as the wiring layer, it is not necessary to form an element isolation insulating film on the base. Therefore, according to the present invention, increasing the capacity of the ROM is also an advantage. Furthermore, by stacking wiring layers in multiple layers, it is possible to easily form a memory array in multiple layers, that is, in a three-dimensional arrangement. This also greatly contributes to increasing the capacity of the ROM.

(Example) Embodiments of the present invention will be described below with reference to the drawings.

FIGS. 1(a) to 1(d) show the structure of a ROM of one embodiment for 3×3×2 bits. In this embodiment, two layers of memory arrays MA1 and MA2 are stacked on the substrate, and (a) and (b) are separated for convenience of explanation, and the memory arrays MA1 and MA2 of the first layer, respectively, are separated from each other for convenience of explanation. FIG. 4 is a plan view showing a portion of a second layer memory array MA2. (C) and (d) are AA' and BB' cross-sectional views of (a) and (b). The substrate 1 is, for example, an SL substrate, and a plurality of first-layer wiring layers 3 (3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3.

32,...) are formed. This first layer wiring layer 3
The substrate on which is formed is covered with an interlayer insulating film 4, and contact holes 8 (81, 8
2,...) are arranged in an array to form a plurality of second layer wiring layers 5 (51, 52,...) made of an n-type polycrystalline silicon film.
) is formed. The second wiring layer 5 is arranged in a direction perpendicular to the first wiring layer 3. The first wiring layer 3 and the second wiring layer 5 are in direct contact with each other at the contact hole 8 to form a pn junction. Each intersection of the first wiring layer 3 and the second wiring layer 5 is connected to a memory cell C+ (Ct 1.C
1□.

), the first layer memory array MA is configured. In a portion without a contact hole, for example, in the memory cell C13, the first wiring layer 3 and the second wiring layer 5 are capacitively coupled with the interlayer insulating film 4 interposed therebetween. On the substrate on which the second wiring layer 5 is formed is interlayer insulation It! i6, contact holes 9 (9, 9, 9,
,...) are formed, and a third layer wiring FJ7 (7+, 72, 72,
) is formed. The third wiring layer 7 is arranged in a direction perpendicular to the second wiring layer 5. Between the second wiring layer 5 and the third wiring layer 7, a memory array MA2 in the second layer is constructed, with each intersection being a memory cell c2 (C21, C22, . . . ).

FIGS. 4(a) to 4(d) are sectional views (corresponding to FIG. 1(C)) showing the manufacturing process of the ROM of this embodiment.

To briefly explain the manufacturing process, for example, after forming an insulating film 2 on a p-type St substrate 1 by thermal oxidation etc., a polycrystalline silicon film is deposited, and boron is added at 1×1017 to 5×1o1.
Dope to about 7/c113. This polycrystalline silicon film is then patterned using a photoresist to form a plurality of first wiring layers 3 ((a)). Next, as the interlayer insulating film 4, a silicon oxide film is formed by, for example, 300 people by thermal oxidation or CVD method, and a photoresist φ pattern corresponding to the data pattern is used to form the interlayer insulating film 4.
A contact hole 8 is formed by selectively etching (
b)). After that, a polycrystalline silicon film is deposited on the entire surface, and it is doped with phosphorus at about 1×1020 to 1×1021/cm3 and buttered to form the second wiring layer 5 (
(C)).

At this time, a pn junction diode is formed at each intersection of the first wiring layer 3 and the second wiring layer 5, where the contact holes 8 are located. Thereafter, an interlayer insulating film 6 is further formed, and a photoresist or pattern corresponding to another data pattern is formed thereon, and using this, the interlayer insulating film 6 is selectively etched to form a contact hole 9.

Then, deposit a polycrystalline silicon film and add 1×101 boron.
After doping to about 7 to 5×10 17 /cI 113 , patterning is performed to form the third wiring layer 7 ((d)).

At this time, a pn junction diode is formed at each intersection of the second wiring layer 5 and the third wiring layer 7, where the contact holes 9 are located.

Figure 2 shows Figure 1 (C) of the ROM configured in this way.
This is an equivalent circuit at the cross section of . The first wiring layer 3
The control line Xl (X+ 1.XI 21 . . . ) and the second control line Y (Y 1+Y2+
) are orthogonal to each other, and a first memory array MA1 is configured in which diodes and capacitors are selectively arranged between them. Similarly, the second control line Y formed by the second wiring layer 5
(Y,, Y2...) and the third layer by the third layer wiring layer 7.
Control lines X2 (X21°X22, . . . ) are orthogonal to each other, and a second memory array MA2 is constructed between which diodes and capacitors are selectively arranged.

Figures 3(a) and 3(b) show such a ROM in Figure 1(a).
) (b), the first layer memory array MAl and the second layer memory array MAl correspond to (b).
This is an equivalent circuit shown divided into a layered memory array MA2.

Next, the read operation of this ROM will be explained using this equivalent circuit. FIGS. 3(a) and 3(b) show, for example, the potential relationship of each control line when reading a memory cell surrounded by a broken line in the second layer memory array MA2. As shown in the figure, the second control line Y2 indicating the position corresponding to the memory cell to be read is connected to the OV1V2O3 control line X22.
Apply v. The remaining second control lines are all set to 5V, and the first control line X1 is set to Ov. If the cell selected at this time constitutes a diode as shown in the figure, a current flows between the second control line Y2 and the third control line X22.

If this cell is a capacitor, no current will flow.

In other unselected cells, the diode portion is also zero biased or reverse biased, and no current flows. In this way, it is possible to determine whether the selected cell information is 0 or 1 based on the presence or absence of current.

According to this embodiment, the ROM is constituted by multilayer wiring layers in which the presence or absence of contact holes is made to correspond to data.

Moreover, a pn junction or the like is not formed in advance, and the wiring material is selected so that a rectifying contact is made when the wiring layers come into contact through the contact hole. Furthermore, it is easy to stack the memory array three-dimensionally. As described above, it is possible to miniaturize the cell and increase the capacity of the ROM.

In the above embodiment, all three wiring layers were formed of polycrystalline silicon films, which are semiconductor layers. However, in order to improve the rectification characteristics of the cells in the written state, polycrystalline silicon films were formed using an energy beam. It is effective to crystallize the film. In addition, amorphous silicon or the like can be used as the wiring layer material, and in order to lower the wiring resistance,
W, Mo, etc. or silicides thereof may be laminated on the surface of the wiring layer.

FIGS. 5(a) and 5(b) show FIGS. 1(c) and (d) of an embodiment in which the first wiring layer of the previous embodiment is constituted by a diffusion layer in the substrate.
) is a sectional view corresponding to FIG. An n-type Si substrate is used as the substrate 1, and the first wiring layer 3 is formed in a stripe shape by a p-type diffusion layer. A second wiring layer 5 made of an n-type polycrystalline silicon film and a third wiring layer 7 made of a T)-type polycrystalline silicon film are sequentially laminated thereon, and an interlayer insulating film 4.6 between each wiring layer is used to store data. Forming the contact holes 8 and 9 accordingly is the same as in the previous embodiment. This embodiment also provides the same effects as the previous embodiment.

In the embodiment, a pn junction has been described as an example of a rectifying contact, but a rectifying contact using a Schottky barrier may also be used in combination with metal wiring, for example. Figure 6(a) (
b) is a sectional view corresponding to FIGS. 1(c) and 1(d) of such an embodiment. In this embodiment, the third wiring layer 7 is made of Pt or Au.

Using metal films such as A and e, a Schottky diode is constructed between the metal film and the second wiring layer 5 made of an n-type polycrystalline silicon film. This embodiment also provides the same effects as the previous embodiment.

In the embodiment, the memory array has two layers, but it can be made of only one layer, or three or more layers can be stacked. For example, FIG. 7 shows an embodiment using only the first layer memory array MA of the above embodiment. Figure 8 shows
A fourth wiring layer 10 made of an n-type polycrystalline silicon film and a fifth wiring layer 11 made of a p-type polycrystalline silicon film are formed on the third wiring layer 7 of the previous embodiment by repeating the same process. are sequentially formed to form a four-layer memory array MA.

It is a sectional view of an example in which ~MA4 is laminated. In this way, memory capacity can be easily expanded.

Note that when stacking many wiring layers, it is recommended to flatten the substrate by filling the gaps between the multiple wiring layers in each layer with an insulating film.
d It is preferable in terms of reliability.

The embodiments described above can be said to be a type of mask ROM in that data is written using a mask during the manufacturing process. The present invention can also be applied to a FROM in which data is written by electrically destroying the wiring interlayer insulating film after the device is manufactured. An example thereof will be described next.

FIGS. 9(a) to 9(d) show the state of the ROM in such an embodiment before data is written, that is, before programming, as shown in FIG. 1(a).
) to (d). Components corresponding to those in FIG. 1 are given the same reference numerals and detailed explanations will be omitted.

As is clear from the figure, in this embodiment, the interlayer insulating film 4,
6 without forming a contact hole in the first wiring layer 3.
- The third wiring layer 7 is sequentially laminated. The conductivity types of each wiring layer are interchanged so that when the interlayer insulating film between them is damaged by electrostatic discharge, the upper and lower wiring layers come into direct contact to form a pn junction.
It is chosen to be opposite to L.

To give a specific numerical example, the first wiring layer 3 and the third
The layer wiring layer 7 has a boron concentration of 5×10 16 to 1×10
” /atr3 p-type polycrystalline silicon film, and the second wiring layer 5 has a phosphorus concentration of 1×102° to 1×1021/c1.
An n-type polycrystalline silicon film of about 13 mm is used. Interlayer insulation film 4
, 6 are both made of variable thermal oxide films with a thickness of about 100 mm.

FIG. 10 shows FIG. 9 (c) of FROM before this program.
) is shown corresponding to FIG. 1(c). As shown in the figure, the first layer memory array MA
In both the memory array MA2 and the second layer memory array MA2, before programming, all memory cell portions are capacitors using an interlayer insulating film as a dielectric.

FIGS. 11(a) and 11(b) show the potential relationship of each control line during programming in the memory array MA1 of the first layer. The second layer memory array MA2 is shown below. In these figures, cells indicated by diodes have already been programmed, and the potential relationships shown are as shown in Figure 11(b).
This is the case when writing is performed to the cell surrounded by the broken line.

That is, the selected second control line Y2 and third control line X22
To write to the memory cell at the intersection of
), the second control line Y2 is set to Ov, and a write voltage of 14V is applied to the second control line X22. 14V is applied to all remaining second control lines, and the first control line
All l's are 0■. This causes electrostatic breakdown of the interlayer insulating film in the selected cell, and as a result, a pn junction diode is formed between the second wiring layer 5 and the third wiring layer 7 in this portion.

As for the remaining cells, those with zero bias are naturally not written. For cells with a 14V reverse bias relationship,
As a result of the depletion layer extending to the low concentration p-type interline layer side and sharing a part of the applied voltage of 14 V, the electric field applied to the interlayer insulating film does not reach the breakdown limit value, and no writing is performed.

A cell that has already been written to has a zero bias or a 1 bias.
The reverse bias is 4V, and if the pn junction breakdown voltage is 14V or higher, no current will flow.

In this way, selective electrical writing is performed.

The read operation of the ROM to which data has been written is similar to that of the previous embodiment.

According to this embodiment, a FROM with miniaturized cells and increased capacity can be obtained. In particular, compared to the previous embodiment, the manufacturing process is simplified because a contact hole forming process is not required, and for the same reason, it is possible to form finer cells.

In the FROM of this embodiment, as in the case of the mask ROM described above, a diffusion wiring layer in the first wiring layer substrate is used, and a metal film-semiconductor film that forms a Schottky barrier in a part of the wiring layer is used. Various modifications are possible, such as using a combination of the above, multilayering the wiring layers to three or more layers, etc.

[Effects of the Invention] As described above, according to the present invention, the cell can be miniaturized with a simple structure and the capacity can be increased by the wiring layer stacking process including the contact hole forming process according to the data spacing pattern. The desired mask ROM is obtained.

Further, according to the present invention, it is possible to obtain a FROM that enables further miniaturization of cells and increase in capacity in L1 by utilizing data writing caused by electrostatic breakdown of the interlayer insulating film.

[Brief explanation of the drawing]

FIGS. 1(a) to (d) show the ROM structure of an embodiment of the present invention, in which (a) and (b) show the first layer opening and the second layer opening, respectively.
Plan views showing the memory array of the second layer, (C) and (d)
are AA' and BB' cross-sectional views of (a) and (b), respectively, Figure 2 is an equivalent circuit diagram of the ROM at a cross-section corresponding to Figure 1 (c), and Figure 3 (a). (b) is also the RO
An equivalent circuit diagram of the memory array of the first layer and the second layer of M,
FIGS. 4(a) to 4(d) are cross-sectional views showing the manufacturing process of the ROM, and FIGS. 6(a) and 6(b) are cross-sectional views corresponding to FIGS. 1(c) and (d) of an example in which metal wiring is used as part of the wiring layer. Figure 7 shows an example ROM with a single layer memory array.
FIG. 8 is a cross-sectional view of a ROM of an embodiment in which the memory array has four layers, and FIGS. 9(a) to (d) show the structure of an embodiment in which the present invention is applied to FROM. (a)-(d
), FIG. 10 is an equivalent circuit diagram corresponding to FIG. 2 of the FROM, and FIG. FIG. DESCRIPTION OF SYMBOLS 1...Si substrate, 2...Insulating film, 3...1st layer wiring layer, 4.6... Interlayer insulating film, 5...2nd layer wiring layer, 7...3rd layer Layer wiring layer, 8.9... contact hole,
MAl...first layer memory array, MA2...second layer memory array. Applicant's agent Patent attorney Takehiko Suzue
k

Claims (2)

[Claims] (1) At least two wiring layers each having a plurality of wires crossing each other are laminated on the substrate with an interlayer insulating film interposed therebetween, and the interlayer insulating film is coated in a manner corresponding to the data pattern before forming the upper wiring layer. 1. A semiconductor memory device characterized in that contact holes are arranged in an array, and each contact hole makes rectifying contact between an upper wiring layer and a lower wiring layer. (2) At least two wiring layers each having a plurality of wires crossing each other are laminated on the substrate via an interlayer insulating film, and the interlayer insulating film is connected to an upper wiring layer selected in accordance with write data. A semiconductor memory device characterized in that by applying a predetermined write voltage between lower wiring layers, the semiconductor memory device is destroyed at the crossing position, and a rectifying contact is made between the upper wiring layer and the lower wiring layer at the crossing position.