JPH01187474A - Logic tester - Google Patents

Abstract

PURPOSE:To easily detect a whisker pulse by detecting a pulse signal with less than prescribed width in the logic output signal of a logic circuit element. CONSTITUTION:An input signal (a) is inverted by an inverter 21 and its inverted signal (c) is inputted to the input terminal D of a pulse detecting circuit 1; and the input signal (a) is delayed by a delay circuit 12 and the delayed signal (b) is inputted as a latch signal to the clock terminal CK. Further, a latch 14 inputs the input signal (a) at the input terminal D and also inputs the delay inverted signal (d) which is generated by inverting the delay signal (b) by an inverter 22 at the clock terminal CK. Then, an OR circuit 15 inputs the output signals (e) and (f) of the latches 13 and 14 and sends its output signal to the reset terminals R of the latches 13 and 14. The latch 13, therefore, latches a positive pulse when the inverted signal (c) inputted from the input terminal D is a positive pulse smaller than the delay quantity of the delay circuit 12 and the latch 14 latches a negative pulse when the input signal (a) is the negative pulse smaller than the delay quantity, thereby easily detecting the whisker pulse.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a logic tester, and particularly to a logic tester that can easily detect logic defects in logic circuit elements.

[Conventional technology]

In general, a logic tester for testing logic defects in logic circuit elements made of semiconductors has a function to detect the logic level of the logic circuit element and V, an output pulse detection function, an output high impedance detection function, and a function to detect the high impedance of the output. A memory function for storing the detection results and a reporting function for reporting the detection results to the operator by sound or the like are provided.

[Problem to be solved by the invention]

As mentioned above, conventional logic testers have a function to detect logic levels, etc., but they do not have a function to detect logic defects caused by the generation of whisker-like pulses based on errors in setting the delay amount of internal circuits. This poses a problem in that large scale equipment such as a logic analyzer and a synchroscope must be used to detect the pulse.

An object of the present invention is to eliminate the problems of the prior art, and to provide a logic tester that can easily detect whisker-like pulses.

[Means to solve the problem]

To achieve the above object, the present invention provides a logic tester for detecting a logic defect in an electrical logic circuit element, comprising: a detection circuit for detecting a pulse signal of a predetermined width or less included in a logic output signal of the logic circuit element; A reporting circuit, for example, a display circuit, is provided to report the detection to the operator when the pulse signal is detected by the detection circuit.

[Effect]

In the logic tester, when the detection circuit detects a pulse signal in the logic output signal of the logic circuit element, the reporting circuit reports this to the operator. This allows the operator to detect logic defects such as incorrect setting of the delay amount in the internal circuit of the logic circuit element.

〔Example〕

Hereinafter, one embodiment of the logic tester according to the present invention will be described in detail using the drawings.

FIG. 1 is a diagram showing the overall configuration of the logic tester according to this embodiment, FIG. 2 is a diagram showing the detailed circuit of the pulse detection circuit in FIG. 1, and FIG. 3 is a diagram showing the detailed circuit of the pulse detection circuit in FIG. FIG. 3 is a time chart diagram showing the operation of the circuit.

The logic tester according to this embodiment is as shown in FIG.
A logic level detection circuit 2 having functions such as logic level detection, output pulse detection, and high impedance detection, a pulse detection circuit 1 for detecting the whisker-like pulses described later, and a buffer gate 20 for these circuits 1 and 2. The device is equipped with an input terminal 4 through which an output signal of a logic circuit element is input, and a display circuit 3 which displays a detection result, and a logic signal inputted from the input terminal 4 is tested to detect a defect in the logic signal. In this case, the display circuit 3 displays this fact.

The pulse detection circuit 1 inputs the input signal a to an inverter 21.
A latch 13 inputs an inverted signal C via a delay circuit 12 to an input terminal, and inputs a delayed signal S obtained by delaying the input signal a via a delay circuit 12 to a clock terminal CK as a latch signal; A latch 14 inputs a delayed inverted signal d obtained by inverting the delayed signal S by an inverter 22 to the input terminal CK, and an output signal e from the output terminals Q of the latches 13 and 14.
and f as inputs, and an OR circuit 15 whose output signals are input to the reset terminals R of the latches 13 and 14, respectively. Therefore, the latch 13 latches the positive pulse when the inverted signal C input from the input terminal 1 is a positive pulse smaller than the delay amount by the delay circuit 12, and the latch 14 latches the positive pulse when the input signal a is the delay amount It is configured to latch the negative pulse in case of a smaller negative pulse.

As shown in FIG. 3, the pulse detection circuit 1 configured in this manner operates as follows when the input signal a contains a whisker-like positive pulse P1 and a negative pulse P2.

First, when the first rising pulse of the input signal a is input, the delayed signal applied to the clock terminal CK rises while the inverted signal C is applied to the input terminal of the latch 13 at a low level. , the latch 13 holds the output signal e at low level. Also in the latch 14,
Since the input signal a is at a low level at the time when the delayed inverted signal d rises, the output signal f is held at a low level.

Next, when the whisker-like positive pulse signal P1 is applied, the latch 13 is inverted by the inverter 21. Since the delayed signal S rises when the inverted signal C is at a high level, it is latched and the output signal e is set to high level and outputted via the OR circuit 15. Since this output signal g is input to the reset terminal R of the latch 13, it is output as a pulse signal. At this time, since the input signal a of the latch 14 is at a low level at the time when the delayed inverted signal d rises due to the positive pulse signal P, the output signal f is maintained at a low level. That is, when the pulse detection circuit 1 according to the present embodiment receives the whisker-shaped positive pulse signal P, the latch 13 is latched to detect the whisker-shaped positive pulse signal P.

Next, when the negative pulse signal P2 is input while the input signal a is at a high level, the latch 14 is latched because the input signal a is at a high level at the rising edge of the delayed inverted signal d. Raise the output signal f. This output signal f is outputted via the OR circuit 15 and inputted to the reset terminal R of the latch circuit 14, thereby becoming a pulse-like output signal g. Therefore, the latch 14 can detect the negative pulse signal P2 by latching and outputting it when the negative whisker-like pulse signal P2 is mixed in the input signal a.

As described above, according to this embodiment, when positive and negative whisker-shaped pulse signals are input, the pulse signals are delayed to create a latch signal, and the level of the input signal at the rising edge of the latch signal is latched. By doing so, these whisker-like pulse signals can be easily detected.

〔Effect of the invention〕

As described above, according to the present invention, since the logic tester is provided with a circuit for detecting whisker-like pulses, it is possible to easily detect logic defects due to errors in delay amounts of logic circuit elements.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the overall configuration of an embodiment of a logic tester according to the present invention, FIG. 2 is a diagram showing details of the pulse detection circuit shown in FIG. 1, and FIG. 3 is a diagram showing the circuit shown in FIG. 2. FIG. 2 is a time chart diagram for explaining the operation of FIG. 1: Pulse detection circuit, 2: Logic level detection circuit, 3:
Display circuit, 12: delay circuit, 13 and 14: latch,
15: OR circuit, 20: Buffer gate, 21: Inverter.

Claims (1)

[Claims] In a logic tester that detects a logic defect in an electrical logic circuit element, a detection circuit that detects a pulse signal of a predetermined width or less included in a logic output signal of the logic circuit element;
A logic tester comprising: a reporting circuit that reports the detection to an operator when the pulse signal is detected by the detection circuit.