JPH01181206A - Differential amplifier - Google Patents

Abstract

PURPOSE:To reduce the chip area in case of circuit integration and to save number of switching voltage terminals (pins) by providing a switch circuit to an input terminal of a differential amplifier comprising an FET, superimposing a switching DC bias voltage onto a high frequency signal, switching on/off the resulting voltage, and using the circuit in common. CONSTITUTION:A 1st high frequency signal is inputted to a gate input terminal of a 1st FET1 of the differential constitution and a 2nd high frequency signal is inputted to a gate input terminal of a 2nd FET2. A 1st switch circuit 10 consists of FETs 31, 32 and a gate input terminal of the FET2 is connected to ground in terms of high frequency by applying a switching DC bias voltage to the gate input terminal of the FET1. A 2nd switch circuit 11 consists of FETs 51, 52, a gate input terminal of the FET1 is connected to ground in terms of high frequency by impressing a switching DC bias voltage to the gate input terminal of the FET2. That is, the input is switched by superimposing the switching DC bias voltage onto the 1st high frequency signal, applying the result to the gate input terminal only of the FET1, or by superimposing the switching DC bias voltage onto the 2nd high frequency signal, and impressing the result to the gate input terminal only of the FET2.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a differential amplifier having a V-configuration using FEfT, and particularly to a differential amplifier suitable for integrated circuits used in chainer circuits and the like. be.

[Conventional technology]

There is no suitable example of a fully integrated chainer circuit that amplifies high frequency signals and converts the frequency.As a proportion, there is no suitable example of one configured with FETs, but an example of one configured with S1 bipolar transistors is IE (--) Lansaxin
On Consumer Electronics, CEE5
2, 4 (1986) pp. 725-732 (
Ig) itE, Trans.

Consumer Electrotronics CE
S2, No. 4: 1986) PP725-752
). In this proposed example, high-frequency signals in different reception frequency bands are switched and input to separate high-frequency signal amplification differential amplifiers and frequency converters, respectively.

[Problem to be solved by the invention]

In the above-mentioned proposed example, the differential amplifier for high-frequency signal amplification and the frequency converter are used separately depending on the receiving frequency band, so the circuit regulation IIX increases and the integrated circuit The problem was that the chip area would increase if the It also has a switching signal terminal (bin).

There is also the problem that the number of pins increases when integrated circuits are implemented. Moreover, if the chip area and number of pins increase when integrated circuits are implemented in this way, the package becomes larger, and as a result, it becomes difficult to obtain good high-frequency characteristics.

The purpose of the present invention is to solve the problems of the prior art described above,
It is an object of the present invention to provide a differential amplifier that can reduce the chip area and number of pins and make the package smaller when integrated circuit.

[Means to solve the problem]

In order to achieve the above-mentioned advantages, the present invention provides first and second Fl! of a differential configuration. ! from the gate input terminal of the first FFi 'l'.
A differential amplifier to which a high frequency signal of FFi! is input, and a second high frequency signal is input from the gate input terminal of the second FET, is constituted by FETs, and the first FFi! a first switch circuit that grounds the gate input terminal of the second FET at high frequency by applying a switching DC bias voltage to the gate input terminal of the FET; Connect the switching DC voltage to the gate input terminal of
and a second switch circuit that grounds the gate input terminal of the first FET at high frequency by applying the Iasumi pressure.

[Effect]

In the following configuration as described above, the switching DC bias/1 voltage is superimposed on the first high frequency signal to
When applied only to the gate input terminal of 'l', the switching DC bias voltage causes the first and second Fl'l
A gate bias is applied to the gate input terminal of the second Fl'l', and the first switch circuit grounds the gate input terminal of the second Fl'l', to which the second high frequency signal is inputted, in terms of high frequency. .

Only the first high frequency signal is unbalanced inputted from the gate input terminal of the first FliiT. Furthermore, when the switching DC bias voltage is superimposed on the second high frequency signal and applied only to the gate input terminal of the second Fl'l', the switching DC bias '1 voltage causes the switching DC bias voltage to be applied to the first and second high frequency signals. A gate bias is applied to the gate input terminal of the second l'lil'L', and the second switch circuit
the 10th FIST to which the first high frequency signal is input;
The gate input terminal of the FET is grounded in terms of high frequency, and only the second high frequency signal is sent to the unbalanced input δ from the gate input terminal of the second FET.

In this way, the first and second high-frequency signals can be switched and input, and the differential amplifier can be used for different reception frequency bands, so the circuit can be simplified and there is no need for switching signal input terminals (pins). becomes. Therefore, when integrated into an integrated circuit, the chip area and number of pins do not increase, and the package can be made smaller.

〔Example〕

EMBODIMENT OF THE INVENTION Below, one embodiment of the present invention will be described in detail using the drawings.

The first factor is a circuit diagram showing a differential amplifier as an embodiment of the present invention, in which 1 and 2 are FIiTs for differential amplification whose sources are commonly connected to form a differential pair, and 3 is an FB for constant current source. 'l',
4 and 5 are load resistances, 6 is a constant current source current setting resistor, 1
0 is the first switch circuit, 11 is the second switch circuit,
12 is a bias voltage (10 B) input terminal, 13, 14 is an output terminal, 15, 16 is a high frequency signal input terminal, 17 is a high frequency ground terminal, 18 is a bypass capacitor, and 19 is a bias resistor. Further, the first switch circuit 10 includes a diode 50, F'ET31, PI)T32. Diodes 33, 34, 41. Bias resistance 35~40cm,
The second switch circuit 11 also has the same circuit configuration as the first switch circuit 10, with a diode 50, a FET 51,
FET52, diode 53°54.61. It is composed of bias resistors 55-60. Note that all the FETs in the circuit of FIG. 1 are depletion type GaAs+
It is composed of MES FETs and has a high operating frequency so that it can be used in different receiving frequency bands.

Now, high frequency signals of different frequency bands are input to the high frequency signal input terminals 15 and 16, respectively.

Therefore, first, when a DC voltage, which is a switching voltage, is applied to the high frequency signal input terminal 15 of the first switch circuit 10 in a manner superimposed on the high frequency signal, a bias resistor 38 is applied to the gate of FFi'I'31. , diode 55.54, and resistor 37, the switching voltage is divided by bias resistor 35.40 and a higher voltage is applied, F
ET31 is turned on. This method, diode 30.41
becomes conductive, and a voltage lower than the switching voltage by the threshold voltage of the diode 30 is applied to the gate of the differential amplification FET 1. Furthermore, a voltage is applied to the gate of the differential amplification FET 2 via the bias resistor 19.

At this time, the high frequency signal input terminal 16 of the second switch circuit 11 is not applied with the DC voltage which is the switching voltage.
The diode 5 is open or fixed at zero potential, so the diode 5
0 is off, and the source potential of the FET 51 determined by the bias resistor 58, diodes 53 and 54, and bias resistor 57 is high enough to cut off compared to the grounded gate voltage. Therefore, since the constituent elements of the second switch circuit 11 are FETs, the leakage current on the second switch circuit 11 side is extremely small.
Therefore, if the bias resistor 19t is selected to be somewhat low, approximately Ω, almost the same bias voltage will be applied to the gates of the differential amplification Flil'l' 1.2.

At this time, the source (drain) terminal of the seventh switch circuit 100FET 32 is grounded at high frequency by the bypass capacitor 18, but since the gate bias is at zero potential, it is turned off. FET S1
Since the drain output impedance is also as high as several Ω, the high frequency signal from the high frequency signal input terminal 15 is transmitted to the gate of the differential amplification F'ET 1 with almost no attenuation.

Furthermore, the switching voltage is applied to the FET 52 of the second switch circuit 11 by a bias resistor 56, and the gate gold bypass capacitor of FB'l'2 for differential amplification is turned on at a high frequency. 18 for high frequency grounding. As a result, an unbalanced input differential amplification operation is performed in which one of the input terminals (gates) of the FETs having a differential configuration is grounded.

On the other hand, the DC voltage that is the switching voltage is applied to the high frequency signal input terminal 1.
6 is applied superimposed on the high frequency signal, the same NJJf'11: as in the case where it is applied to the high frequency signal input terminal 15 described above is performed.

Now, in conventional differential amplifiers, two input terminals are switched and used, and when one input terminal is grounded by a bypass capacitor, two input terminals, two high frequency ground terminals, and a switch switching terminal are used. Normally, a total of 5 terminals are required, but in this example, only 3 terminals are required, and when it is integrated into an integrated circuit, the number of pins can be reduced and the package can be made smaller, so good high frequency characteristics can be obtained. be able to.

In addition, by switching the high-frequency signals of all two systems of one differential amplifier and using them in common, the circuit can be simplified, and when integrated, the chip area can be reduced. Furthermore, one input terminal is grounded in terms of high frequency using an FET, and the diode between the gate of the FLIT with a differential configuration and its input terminal is turned off. It also has the effect of being able to attenuate and provide excellent isolation characteristics.

FIG. 2 is a circuit diagram showing a friend Chena circuit equipped with the differential amplifier of FIG. 1.

In FIG. 2, parts having the same functions as those in FIG. 2 are given the same numbers. Additionally, 120 is a frequency conversion circuit, and FETs 80 to 85 form a double balanced mixer configuration. Further, 90 is a VHF band oscillation circuit, 9
1 is a uHF band oscillation circuit, 92 is a coupling circuit for oscillation signals from oscillation circuits 90 and 91, 94 is a balanced amplifier circuit for oscillation signals, 93 is an oscillation switching circuit, 7D is a bias resistor, 95
9 is an IP amplifier circuit, and 96 is a VHF resonant circuit, which is mainly composed of a variable capacitance diode 101 and a resonant coil 102. Further, 97 is a uHF resonant circuit, which is mainly composed of a variable capacitance diode 103 and a resonant line 104, and 98 is an IP tuning circuit, which includes a tuning coil 109.
, a tuning capacitor 108, and a damping resistor 107. ? Reference numeral 9 denotes an oscillation frequency control voltage terminal, which changes the oscillation frequency by changing the capacitance of variable capacitance diodes 101 and 103 of the resonant circuit 96 and 97, respectively, depending on the input control voltage. 100 is the bias voltage (10B
) input terminal, 105 is a bypass capacitor, 106ij
The bias resistor 110 is a coupling capacitor. J20
0 indicates the nine integrated circuit portions of the Chainer circuit. 20 to 25 are terminals connected to the resonant circuit and the oscillation circuit tp, 24.25 are connection terminals of the IF tuning circuit 98, and 26 are I
The P-times signal input terminal and 27 are the IF signal output terminals.

The high frequency signal in the uHF band is input from the input terminal 16, and also from the VHF
The high frequency signals of the bands are inputted from the input terminals 15, respectively. For example, when receiving a VHF band second signal, a switching voltage of 1 is applied to the input terminal 15 in a manner superimposed on a VHF band surface frequency signal. As a result, a high frequency signal in the VHF band is input to the gate of FET 1 by the switch circuit 10, and
F]11T52 of switch circuit 11 is turned on and FET2
The gate 'f: is grounded in terms of frequency, and the diode 5
0 is turned off to block input of the uHF band high frequency signal from the input terminal 16. As a result, the VHF band high frequency signal input to the gate of FR'['1 is transmitted to the differentially configured FE.
The signal is converted into a balanced signal at T1.2 and input to the frequency conversion circuit 120 having a double-balanced mixer configuration.

Further, at this time, the switching voltage is also transmitted to the oscillation switching circuit 93 via the bias resistor 70, thereby causing the oscillation switching circuit 9
5, the VHF band oscillation circuit 90 is supplied with a bias voltage to operate, and the uHF band oscillation circuit 91 is kept stopped without being supplied with bias voltage. As a result, V
The oscillation signal from the 11F band oscillation circuit 9θη is sent to the coupling circuit 92. It becomes a balanced oscillation signal via the balanced amplifier circuit 94.

is input to frequency converter path 120. Frequency converter 12
0, the input oscillation signal and high-frequency signal are mixed and frequency-converted, and then only the IP signal component is extracted by the IIF tuning circuit 98 and connected to the IIF signal via the coupling capacitor 110t.
The signal is amplified by the P amplifier 95 and output as an IF multiplied signal from the output terminal 27.

In FIG. 2, oscillation and frequency conversion in the VHF band and IP amplification operation fF,1- are performed as described above.

On the other hand, when receiving a uHF band signal, a switching voltage tu is similarly applied to the input terminal 16 in a manner superimposed on the high frequency signal of the HF band. As a result, in the switch circuit 11, F1ii'
l'52 is off, diode 50 is on, FET
All high frequency signals in the uHF band are input to the gate of 2, and in the switch circuit 10, the FET 32 is turned on and the FE
The gate of T1 is grounded in terms of high frequency, and the diode 50 is turned off to block the input of high frequency signals in the VHF band.

Further, by setting the bias of the oscillation switching circuit 93 to zero potential, the supply of bias voltage to the oscillation circuit 90 in the VHF band is stopped, and the bias voltage is supplied to the oscillation circuit 91 in the uHF band, and the oscillation operation in the uHF band is stopped. In this way,
Oscillation, frequency conversion, and IF amplification operations are performed in the uHF frequency band.

In the circuit shown in Fig. 2, not only the differential amplifier that amplifies the high-frequency signal but also the frequency converter is used to switch between two signal systems, and the input terminal of the differential amplifier is also switched. In addition, the switching signal t of the oscillation circuit is also obtained from the high-frequency signal input terminal, which simplifies the circuit and reduces the number of switching signal terminals. Therefore, when a single circuit is integrated into an integrated circuit, the chip area is small.

The number of pins can be reduced, the package can be made smaller, and as a result, good high frequency characteristics can be easily obtained.

Although the present invention has a configuration in which a switching circuit is provided at each of the two gate input terminals of the differential amplifier, the same effect can be obtained even if a plurality of switching circuits are provided at one input terminal.

〔Effect of the invention〕

As explained above, according to the present invention, a switch circuit gold film is applied to the input terminal of a differential amplifier constituted by FET.
By superimposing and applying a switching DC bias voltage to a high-frequency signal, the switch circuit is turned on and off to switch the input, and by making the circuit dual-purpose, it can be integrated into an integrated circuit, reducing the chip area and switching. Voltage terminal (pin)
This has the effect of making it possible to reduce the amount of noise, making the package smaller, and making it easier to obtain good high-frequency custom orders.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, and No. 2 (8) is a circuit diagram showing a chainer circuit in which all the differential amplifiers shown in FIG. 1 are mounted. Explanation of symbols 1.2,452.52: FET, 10: Seventh switch circuit, 11; Second switch circuit, 15.16;
High frequency signal input terminal, 17; High frequency ground terminal, 1
8: Bypass capacitor, 90: VHF band oscillation circuit,
91: uHF band oscillation circuit, 9S: oscillation switching circuit,
120; Frequency conversion circuit; 200; Integrated circuit portion of Chainer circuit.

Claims (1)

[Claims] 1. Consisting of at least first and second FETs in a differential configuration, a first high frequency signal is input from the gate input terminal of the first FET, and the gate of the second FET is A differential amplifier to which a second high-frequency signal is input from an input terminal is composed of FETs, and when a switching DC bias voltage is applied to the gate input terminal of the first FET, the second FET is switched. A first switch circuit that grounds the gate input terminal at high frequency, and a FET, and the second
a second switch circuit that grounds the gate input terminal of the first FET at high frequency by applying a switching DC bias voltage to the gate input terminal of the FET; By superimposing the signal on the first high-frequency signal and applying it only to the gate input terminal of the first FET, the gate input terminal of the second FET to which the second high-frequency signal is input is high-frequency ground, and only the first high frequency signal is connected to the first F.
If the unbalanced input is applied from the gate input terminal of the ET, and the switching DC bias voltage is superimposed on the second high frequency signal and applied only to the gate input terminal of the second FET, The gate input terminal of the first FET to which the first high frequency signal is input is grounded in terms of high frequency, and only the second high frequency signal is input to the second FET.
A differential amplifier characterized in that an unbalanced input is made from the gate input terminal of the differential amplifier.