JPH01154656A - Burst linkage processing system - Google Patents

Abstract

PURPOSE:To realize the high speed linkage processing of a burst by storing the storage scheduled page of a consecutive burst in a buffer corresponding to the burst stored in a buffer memory. CONSTITUTION:A burst arrived to a reception data FIFO section 21 of an input path control section 20-1 is written in a memory page address designated by the count of an address counter 23 in a buffer memory 11. Then the storage scheduled page of a consecutive burst in a buffer is stored in said address in a linkage memory 12 and said storage schedule page is loaded in the counter 23. On the other hand, the burst of the memory address designated by the count of the address counter 33 in the buffer memory 11 is read at the transmission and sent via a transmission data FIFO section 31 and the data of said memory page address in the linkage memory 12 is read and loaded to the counter 33.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to a data storage/switching device that exchanges long packets consisting of a plurality of bursts, and particularly relates to a data storage/switching device that exchanges long packets consisting of a plurality of bursts, and in particular, the linkage of each burst constituting the long packet. This paper relates to a burst linkage processing method for maintaining

(Prior Art) Conventionally, data storage and switching equipment divides packets into fixed-length bursts and handles long packets made up of multiple bursts using route information and burst linkage information added to each burst. It has been known. In this type of exchange, a method has generally been adopted in which memory pages corresponding to one bus are chained by list processing. This conventional chaining method requires the operation of a pointer table in order to rewrite the page chaining information that is sequentially assigned to each receiving boat in the memory that forms the list, and a software control mechanism using a microprocessor or the like is essential. Met.

(Problems to be Solved by the Invention) As mentioned above, the conventional method of chaining long packets using list processing has the problem of not being able to perform high-speed processing because it is controlled by software using a microprocessor, etc. was there.

The present invention has been made in view of the above circumstances, and its purpose is to improve the linkage of bursts forming long packets by using a linkage memory for chaining information storage that is accessed by the same control means as the buffer memory for storage and exchange. The object of the present invention is to provide a burst linkage processing method that can perform processing at high speed.

[Structure of the Invention] (Means for Solving the Problems) In the present invention, each time one burst is stored in the buffer memory, a memory page to be used as the storage destination for the next burst to be stored is initialized. A first address counter that generates a write address for the buffer memory based on the above, a second address counter that generates a read address for the buffer memory, and a memory to be set for each memory page initialization to the first address counter. A reserved memory page holding means for holding pages and a linkage memory for storing chaining information including the reserved memory pages held in this holding means are provided. In this linkage memory, a write position is specified by a page specification part of a write address generated by a first address counter, and a read position is specified by a page specification part of a read address generated by a second address counter. The present invention further includes page management means for managing free pages in the buffer memory and outputting one of the free pages to the holding means as a reserved memory page for continuous bursts in response to a request from the reserved memory page holding means; A transmission queue is provided for queuing storage memory pages of the first burst of received packets stored in the memory in burst units. Either the first memory page indicated by the transmission queue or the memory page in the chaining information read from the linkage memory is 0-coded into the second address counter as the next memory page to be read.

(Function) According to the above configuration, in response to the burst stored in the buffer memory, the page (reserved memory page) scheduled to be stored in the buffer memory of the continuous burst is stored in the linkage memory, so that a long packet is configured. Burst linkage can be kept very simple. Also, during transmission, the storage memory page of the first burst of the packet to be taken out from the buffer memory can be known from the first memory page indicated by the transmission queue, and the chaining memory page stored in the linkage area corresponding to this storage memory page can be known. Since the information allows the user to know the storage memory page of the burst to be retrieved next from the buffer memory, there is no fear that the chaining of long packets will be disrupted.

(Embodiment) Hereinafter, an embodiment of the present invention will be described with reference to the drawings, taking as an example a case in which it is applied to a burst packet switching switch for two directions of traffic.

FIG. 1 shows a block configuration of a burst packet exchange switch, and 11 is a buffer memory for storing received data. The area of this buffer memory 11 is managed by being divided into a plurality of pages (memory pages). Each memory page is used to store a burst constituting a packet, and is accessed by a page designation portion of an address (memory address) for the buffer memory 11 (herein, an upper address, referred to as a page address). 12 is a linkage memory designated by the page address and for storing chaining information. This coaching information includes the storage destination memory page (reserved memory page) for a burst that continues from the burst stored in the memory page (in the buffer memory 11) corresponding to the storage destination of the information. In addition, the chaining information includes a bit that indicates whether the burst stored in the memory page (in the buffer memory 11) corresponding to the storage destination of the information is not the final burst of the corresponding packet or is a JIH burst, that is, whether linkage is continued or not. is added. This bit will be described later as linkage pit b2.13
14 is a memory control section that performs write/read control for the buffer memory 11 and linkage memory 12; and 14 is a page management section that performs page management of the buffer memory 11. The page management unit 14 includes a page FIFO (first-in, first-out buffer) 14a for stacking empty memory pages (memory page addresses thereof) of the buffer memory 11 in order to perform page management of the buffer memory 11.

FIG. 2 shows the format of the burst. In this embodiment, each burst consists of header information and data. The header information includes an output line number that specifies output light, a leading burst designation bit b1, and a linkage pit b2. The first burst designation pit b1 indicates whether the corresponding burst is the first burst (in the case of “1”) (“0”).
”), and the linkage pit b2 indicates that there is a burst that follows the corresponding burst (in the case of “1”).
or not (in the case of "O"), that is, whether the corresponding burst is not the final burst or is the final burst. Therefore, the type of burst can be indicated as follows using the two bits bl and b2.

(2) In the case of blb2-10, this indicates that it is the first burst and the last burst of the corresponding packet, that is, it is the only burst constituting the short packet.

(2) In the case of b1b2-11, this indicates a packet consisting of multiple bursts, that is, the first burst of a long packet.

(2) In the case of blb2-01, this indicates that the burst is neither the first burst nor the last burst of the long packet, that is, it is an intermediate burst.

■If blb2=OO Indicates the final burst of a long packet.

Referring again to FIG. 1, reference numerals 20-1 and 20-2 are input path 1IllJI11 sections with the same configuration that are the sources of write requests to the buffer memory 11, and the internal configuration is only for the input path control section 20-1. It is shown. Entry route control unit 20-
1 is a reception data FIFO unit 2 for absorbing the speed difference and phase difference between the reception data cycle and the internal switch clock.
1, and a register 22 that holds the storage destination memory page (memory page address indicating the storage destination) in the buffer memory 11 of the first burst and burst header information for each received packet. The input route control unit 20-1 further includes an address counter 23 that generates a write address for writing the word in the burst being received into the buffer memory 11.
, a register 24 that holds a page address (referred to as a reserved memory page address) indicating a memory page to be written in the continuation burst together with linkage bit b2 in the header information of the preceding burst, and a burst reception control unit that controls reception of input bursts. It has 25.

Reference numerals 30-1 and 30-2 are output route control units having the same configuration that are sources of read requests for the buffer memory 11, and the internal configuration of only the output route control unit 30-1 is shown.

The output path control unit 30-1 includes a transmission data FIFO unit 31 for absorbing the speed difference and phase difference between the transmission data cycle and the internal switch 0, and a transmission data FIFO unit 31 for storing the first burst in the buffer memory 11 for each transmission packet. It has a transmission queue 32 for queuing pages. Output route control section 30
-1 further includes an address counter 33 that generates a read address for reading words in the burst to be transmitted from the buffer memory 11, and a register 34 that holds chaining information read from the linkage memory 12.

The address counter 33 initializes either the memory page address from the transmission queue 32 or the memory page address in the chaining information from the register 34 according to the linkage bit b2 in the chaining information held in the register 34. It looks like this.

41 is the reception data FIFO of the ingress route control unit 20-1 (
21&'3 and the burst reception control section 25), and a reception data line 42 is used for transmitting the word synchronization signal to the input path control section 20-1 (the burst reception control section 25). The signal line 43 provided is also a signal line used to transmit a burst synchronization signal.

44. 45 transfers the shift-in signal and write request inhibit signal generated by the burst reception control unit 25 to the reception data FIFO.
46 is a signal line for transmitting the abort request signal generated by the burst reception control section 25 to the output route control section 30-1 (transmission queue 32 within); This is a data line used for transmitting header information of received bursts.

51 is a write data bus for the buffer memory 11;
Reference numeral 52 denotes a control bus used for transmitting the storage destination memory page of the first burst of the packet received by the ingress route control unit 20-1, 20-2, and the header information of the burst. 5
3 is a write address bus for the memory control unit 13;
4 is used as a write data bus to the linkage memory 12, and the buffer memory 11 for continuous bursts.
chaining information bus indicating the internal storage destination memory page, 5
A signal line 5 is used for transmitting a packet final word write signal outputted from the address counter 23 in a memory write cycle for the final word of the final burst of a packet. 56 is a read data bus from the buffer memory 11, and 57 is a read data bus from the linkage memory 12. 58 is a read address bus for the memory control section 13, and 59 is a signal line for inhibiting a read request from the transmission data FIFO section 31.

61 is the buffer memory 11.61 from the memory control unit 13. A signal line 62 is used for transmitting self-loading/reading signals to and from the buffer memory 11 . This is an address line used for transmitting a memory address (address signal) to the linkage memory 12. 631.83-2 is the entrance route control unit 20-1
．． A signal line 64-1.64-2 is used to transmit a read request signal from 20-2 to the memory control unit 13, and a signal line 64-1.64-2 is an incoming path control unit 20-1.20-2 from the memory control unit 13.
This is a signal line used for transmitting a write permission signal to. 65-1.65-2 is the exit route control section 30-1.3
Signal lines 66-1 and 66-2 are used for transmitting a read request signal from 0-2 to the memory control section 13, and signal lines 66-1 and 66-2 are used for transmitting a read permission signal from the memory control section 13 to the output control section 301 and 30-2. This is a signal line used for transmission.

67 is the entry route control unit 20-1.2 from the page management unit 14.
A data line 68-1.68-2 indicates a usable memory page (reserved memory page) for 0-2 from the ingress path control unit 20-1.20-2 to the page management unit 14.
A memory page request signal line 69-1.69-2 is used to request a reserved memory page from the input path control unit 20-1. This is the response signal line. A signal line 70 is used for transmitting a burst final word read signal output from the address counter 33 in a memory read cycle for the final word in a burst.

FIG. 3 shows a part of the internal configuration of the reception data FIFO section 21 and the burst reception control section 25 shown in FIG. 1. In the figure, 71 is a reception control circuit that extracts header information from a burst input via the reception data line 41 and analyzes it, and 72 is a reception control circuit output from the reception control circuit 71 and used to control reception for the reception data FIFO unit 21. This is a signal line used for transmitting reception control signals. 74 is an AND gate that controls the output of the word synchronization signal on the signal line 42 according to the reception control signal on the signal line 72; 75 is an AND gate that counts the received bursts, detects the final word, and reads the header of the next burst. information) until arrival (from the received data FIFO section 21 to the memory control section 1
3) is a word counter that generates a write request prohibition signal that prohibits a write request from being output.

76 is a receive data FIFO forming the center of the receive data FIFO section 21. This reception data PIF 076 receives the output signal from the AND gate 74 as a shift-in signal through the signal line 44, and shifts the burst input from the reception data line 41 in units of words. 77 is a signal line used to transmit an output ready signal indicating that the received word has arrived at the output end of the received data PIF076, that is, output ready; 78 is an AND gate. AND gate 78 connects signal line 77
The above output ready signal is used to control transmission of the write request signal to the signal line 63-1 in accordance with the write request inhibit signal output from the 9-dot counter 75 to the signal line 45.

Next, the operation of one embodiment of the present invention will be explained.

Now, the received data F of the ingress route control unit 20-1 shown in FIG.
It is assumed that the long packet reaches the IFO section 21 and the burst reception control section 25 via the first burst reception data line 41 of the long packet. A burst synchronization signal synchronized with the burst transmission is guided to the burst reception unit 25 via the signal line 43, and a word synchronization signal synchronized with the transmission of a predetermined number of words (word data) constituting the burst is introduced via the signal line 42. guided by. The burst reception control unit 25 detects the start timing of a burst on the reception data line 41 based on the burst synchronization signal on the signal line 43, performs a word count based on the word synchronization signal on the signal line 42, and adds the header information. Extract. Then, the burst reception control unit 25 analyzes the extracted header information, and according to the analysis result, sends a shift-in signal synchronized with the word synchronization signal to the reception data FIFO through the signal line 44.
It is output to section 21. The burst reception control unit 25 also outputs the extracted header information to the register 22 via the data line 41. The header information on this data line 47 is stored in the memory of the address indicated by the address counter 23 only when the first burst designation pit b1 in the information is "1", that is, when the corresponding burst is the first burst of the received packet. It is loaded into the register 22 together with the page designation part (that is, the storage destination memory page address in the buffer memory 11 of the first burst). Also, data line 4
The linkage bit b2 in the header information above 7 is loaded into the linkage bit field of the register 24 when writing of (the final word of) the corresponding burst to the memory page in the buffer memory 11 is completed. Note that the detailed operation of the burst reception control section 25 will be explained separately.

In the reception data FIFO unit 21, in response to a shift-in signal from the burst reception control unit 25, an operation is performed to sequentially shift and input the bursts on the reception data line 41 in units of words. Eventually, the receive data FIFO section 2
When the received word reaches the output terminal of 1 (received data PIF016 within), if the write request prohibition signal is not output from the burst reception control unit 25 to the signal line 45,
A write request signal is output from the reception data FIFO section 21 to the memory control section 13 via the signal line 63-1. When the memory control unit 13 receives this self-installation request signal, it performs request acceptance IIQ all according to the internal arbitration procedure, and if the request is accepted, it sends a signal line 64- to the input route control unit 20-1. A write permission signal is returned via 1. This write permission signal is sent to the input route control unit 2.
In addition to the received data FIFO unit 21 in 0-1, the data is led to registers 22, 24 and address counter 23.

At the same time as the write enable signal is output, the memory control unit 13 switches the address lines 62 of the buffer memory 11 and linkage memory 12 to the former of the write address bus 53 and read address bus 58, and In contrast, a write signal is output via the signal line 61 at a predetermined timing.

When a write permission signal is returned from the memory control unit 13 to the input route control unit 20 - 1 , the reception data FIFO unit 21 outputs the received word that has reached its output terminal to the write data bus 51 . Further, from the register 22, its contents, that is, the storage destination memory page address in the buffer memory 11 of the first burst and header information are sent to the control bus 5.
2 is output. Furthermore, a write address is written from the address counter 23.

is output to the address bus 53, and from the register 24,
An address (reserved memory page address) indicating the storage destination memory page in the buffer memory 11 for the next burst is output to the chaining information bus 54. The chaining information output to the chaining information bus 54 has a linkage bit b2 added thereto indicating whether or not there is a burst following the burst currently being stored in the buffer memory 11.

Therefore, in a write permission cycle from the memory control unit 13 in response to a write request from the input route control unit 20-1, the write data bus 5 is
The received word outputted at 1 is written to the word position in the buffer memory 11 specified by the write address outputted from the address counter 23. At the same time, register 24
The reserved memory page address with linkage bit b2 (the address of the storage destination memory page for the continuous burst) output from the address counter 23 to the chaining information bus 54 is the memory page designation part (memory page address) of the write address output from the address counter 23. 1 is stored in the area within the linkage memory 12 indicated by ). Then, every write permission cycle, the address counter 23 counts up and indicates the write address of the next received word.

By repeating the above operations, for example, the first burst of the long packet that has reached the input path control unit 20-1 via the reception data line 41 is stored in the buffer memory 11 indicated by the memory page designation part of the address counter 23. Words are written to memory pages sequentially. Furthermore, a reserved memory page address with a linkage bit b2, that is, a linkage bit b2 indicating whether or not there is a burst following the current burst, is added to the area of the linkage memory 12 indicated by the memory page designation part, The address indicating the memory page where the continuous burst is stored is stored.

Now, the address counter 23 indicates the write address of the final word of the burst to be written into the buffer memory 11, and when the final word is written, the reserved memory page address indicated by the register 24 is transferred to the address counter 23. loaded into. As a result, the address counter 23 is set to the continuous burst buffer memory 11.
Indicates the start address of the internal storage destination memory page. When the contents of the register 24 are loaded into the address counter 23,
A memory page request signal is output from the register 24.

This memory page request signal is led to the page management section 14 via the signal line 68-1. In response to the memory page request signal on the signal line 68-1, the page management unit 14 sends the oldest memory page address to the data line 67 from among the memory page addresses of the empty pages of the buffer memory 11 stacked in the page FIFO 14a. It also outputs a response signal to the memory page request on signal line 69-1.

The memory page address output from the page manager 14 to the data line 67 is used as a reserved memory page address for a continuing burst in the reserved memory page address field of the register 24 in response to a response signal on the signal line 69-1. ) is loaded. In addition, beige FI
If nothing is stacked in the FO 14a, that is, if there is no free memory page because the buffer memory 11 is full, the above loading operation is not performed. In this case, the memory page request signal from the register 24 remains output.

The linkage pit b2 in the header information output from the burst reception control unit 25 to the data line 47 is “O”.
In the N state, the address counter 23 indicates the write address of the final word of the burst to be written into the buffer memory 11, and when the writing is performed, the address counter 23 outputs a packet final word write signal. .

This signal is transmitted via the signal line 55 to the output route control unit 3G-
1, led to 30-2. The memory page address and header information output from the register 22 to the control bus 52 are also guided to the output path control units 30-1 and 30-2. The output route control unit 30-1.30-2 determines the route from the output line number of the header information on the control bus 52, and if the packet is addressed to itself, the output route control unit 30-1.30-2 sends the memory page on the control bus 52 to itself. Put it on the queue. If the outbound route control unit 30-1 determines that the packet is addressed to itself, it is written to the memory page from the register 22 in the inbound route control unit 20-1, that is, to the buffer memory 11. The address indicating the storage memory page of the first burst of the packet is stored in the transmission queue 32, and the packet is switched from the incoming route to the outgoing route.

Next, the transmission operation in the output route control section 30-1 will be explained. The transmission operation in the output route control unit 30-1 is as follows:
The address of the memory page in the buffer memory 11 in which the first burst of the packet to be transmitted is stored is set in the address counter 33, and the transmission data FIF
This is performed when the O section 31 is in the input ready state. In this case, first, a read request signal is output from the transmission data FIFO section 31 to the memory control section 13 via the signal line 65-1.

When the memory control unit 13 receives this read request signal,
Acceptance of the request is controlled according to an internal arbitration procedure, and if the request is accepted, a read permission signal is returned to the output path control section 30-1 via the signal line 66-1.

This read permission signal is guided to the address counter 33 and register 34 in addition to the transmission data FIFO section 31 in the output route control section 30-1.

Simultaneously with outputting the read permission signal, the memory control unit 13 switches the address lines 62 of the buffer memory 11 and linkage memory 12 to the read address bus 58 side, and executes a read permission cycle for the buffer memory 11 and linkage memory 12.

When a read permission signal is returned from the memory control unit 13 to the output route control unit 30 - 1 , a read address is output from the address counter 33 to the read address bus 58 . Therefore, in the read permission cycle from the memory control unit 13 in response to the read request from the output path control unit 30-1,
The word data at the specified position of the read address output from the address counter 33 is read out from the buffer memory 11 to the read data bus 56 as a transmission word. Also, from the linkage memory 12, the memory page designation part (memory page address) of the read address is
The data at the position indicated by , that is, the memory page in the buffer memory 11 in which the next burst to be read is stored, and the bit (linkage bit b2) indicating whether there is a burst continuing from the current burst to be read, are read. The data is read out onto the data bus 51.

The word data read onto the continuous data bus 56 is shifted into the transmission data FIFO unit 31, and the memory page address with linkage bit b2 read onto the read data bus 57 is loaded into the register 34. Then, every read permission cycle, the address counter 33 counts up and indicates the read address of the next transmission word.

By repeating the above operations, the buffer memory 1
1, one burst in a long packet distributed and stored in burst units, that is, the burst stored in the memory page in the buffer memory 11 indicated by the memory page designation part of the address counter 33, is sequentially read out in word units.

Now, by the address counter 33, the buffer memory 1
The read address of the final word of the burst to be read from 1 is indicated, and when the final word is read, the oldest stored memory page address (i.e. first memory page address) or register 34
One of the memory page addresses loaded into the register 34 is selectively loaded into the address counter 33 according to the linkage bit b2 added to the memory page address loaded into the register 34. If b2
In the case of −0, since the burst in which the last word was read is the last burst in the packet, that is, there is no continuous burst (in the same packet), the first burst of the next packet is For reading, the memory page address from the transmit queue 32 is loaded into the address counter 33. On the other hand, b2-
In the case of 1, since the burst in which the last word was read is the beginning or middle burst of a long packet, that is, there is a continuous burst (within the same packet), the reading of the continuous burst is not possible. For this purpose, the memory page address from register 34 is loaded into address counter 33.

The address counter 33 indicates the read at and response of the last word of the burst to be read from the buffer memory 11, and when the read is performed,
The address counter 33 outputs a burst final word read signal. This signal is led to the page manager 14 via a signal line 70.

The address indicated by the address counter 33 is also led to the page management unit 14 via the read address bus 58. When the page management unit 14 receives the burst final word read signal from the address counter 33, the page management unit 14 indicates that the memory page indicated by the memory page designation portion of the address on the read address bus 58 has been released (became vacant). Then, the specified part (memory page address) is fetched. The page management unit 14 then uses the read address bus 58.
The memory page address fetched from page FIFO1
Stack on 4a.

Next, the operation centered on the configuration shown in FIG. 3 will be explained.

The reception control circuit 71 detects the start timing of the burst on the reception data line 41 using the burst synchronization signal on the signal line 43, performs word counting based on the word synchronization signal on the signal line 42, and extracts header information. Do this. The reception control circuit 71 then takes in the extracted header information into an internal register (not shown). At the same time, the reception control circuit 71 outputs the reception control signal that the reception control circuit 71 itself outputs onto the signal line 72, that is, the reception state (reception data Register 2 shown in FIG.
Based on the page request signal (that is, the signal indicating the presence or absence of a reserved page) outputted from 4 to the signal line 68-1, and the header information (of the burst to be received) taken into the internal register, the burst to be received is determined. Determine whether or not to receive (non-receive). The reception control circuit 71 determines a new state of the reception control signal on the signal line 72 based on this determination result. That is, when the reception 611 circuit 71 determines that the reception target burst has been received, the reception control signal is set to logic "1".
”, and if non-reception is determined, the signal is set to logic “
The receive control signal on signal line 72 is directed to one input of AND gate 14. The word sync signal on signal line 42 is directed to the other input of AND gate 74. The gate 74 uses the word synchronization signal on the signal line 42 as a shift-in signal to input the received data FIFO only when the reception control signal is logic "1".
The received data of section 21 is output to PIF076. This makes it possible to receive the received data PIF076.

Furthermore, when the intermediate burst of the long packet is not received, the reception control circuit 71 outputs an abort request signal onto the signal line 46 and rewrites the linkage pit b2 in the header information of the corresponding burst to "0". (that is, rewrite the corresponding burst to the final burst) data line 47
Output on top.

Here, the burst reception/non-reception determination by the reception control circuit 71 will be explained.

■In the case of the first burst If the first burst designation bit b1 in the header information of the burst that has arrived at the ingress route control unit 20-1 is “1”, that is, if the arriving burst is the first burst in the packet, then The reception state is excluded from the judgment conditions.

In this case, if there is a reserved memory page (i.e. register 2
Memory controller 1 responds to the memory page request signal from 4.
If there is no reserved memory page (that is, if there is no memory page allocated by the page management unit 14 because the buffer memory 11 is full), reception is determined. It will be judged.

■In the case of an intermediate or final burst If the first burst designation pit b1 in the header information of the arriving burst is "0", that is, if the arriving burst is an intermediate or final burst in the packet, the preceding burst has been received and there is a reserved memory page. Reception is determined only in this case, and non-reception is determined in other cases.

As described above, during the reception of a long packet, the reception control circuit 71 determines that this burst is not to be received if there is no reserved memory page to store the first or intermediate burst. In this case, the reception control circuit 11
outputs an abort request signal on signal line 46 requesting to discard the received burst in the corresponding packet. The reception control circuit 71 then stops outputting the reception control signal to the signal line 72 until a new packet arrives. That is, the reception control circuit 71 does not restart reception until a new packet arrives, and as a result, there is no possibility of receiving an abnormal ending burst starting from the remaining burst in the same packet that follows the received burst.

Next, write request control in the configuration shown in FIG. 3 will be explained. In FIG. 3, word counter 75 loads an initial value each time a burst synchronization signal is introduced to its load terminal LD via signal line 43, that is, each time the first word of a burst arrives. This initial value indicates the number of words that make up each burst. The clock terminal GK of the word counter 75 receives the shift-in signal output from the AND gate 74, and the enable terminal EN receives the linkage bit b2 in the header information output from the reception control circuit 11 onto the data line 47. is guided.

The word counter 75 enters a count enable state when b2-"1" (that is, when a continuous burst exists), and counts down in accordance with the shift-in signal led to the terminal CKk to count the number of received words.

Then, when a counting operation is performed in response to the shift-in signal for shift input of the last word in the burst, that is, when the number of words indicated by the initial value is counted, the signal is A write request inhibit signal is output on line 45. AND gate 18 connects word line 5 to signal line 45
When a write request prohibition signal is output on the received data F
Even if an output ready signal is outputted from the IFO 76 onto the signal line 77, outputting the ready signal as a write request signal onto the signal line 63-1 is prohibited. That is,
According to this embodiment, a write request to the memory control unit 13 is prohibited from the time when the last word in a burst is shifted into the received data PIF 076 until the arrival of the next burst, and during that time, at least the last word is transferred to the received data FIFO 76. left behind. As a result, as described below, even if the line input is slower than the buffering speed of the buffer memory 11, even if the line input is slower than the buffering speed of the buffer memory 11, the received burst The discard process can be performed at least when the final word is written into the buffer memory 11.

Now, by determining in the reception control circuit 71 whether or not the beginning or middle burst has been received, the reception data PIF
It is assumed that the reception operation (shift input operation) of 076 is prohibited, and the continuous bursts after the non-reception determination burst are not received and are discarded. In this state, when (the first burst of) a new packet arrives, if there is a reserved memory page, the reception control circuit 71 outputs a reception control signal, thereby restarting reception. On the other hand, when a new burst synchronization signal arrives, the word counter 75 loads the initial value described above and stops outputting the write inhibit signal.

As a result, the signal line 63
A write request signal is output via -1, and the received data FI
The writing of the word output from the FO section 21 (received data PIF076 therein) to the buffer memory 11 is restarted.

Eventually, the received data P in the received data FIFO section 21 (
When the last word in the burst left in IF07B) and the last word in the burst immediately before the non-reception determination burst is written to buffer 11, the header information of the burst to which the same word belongs is written as described above. Since it has been rewritten to the final burst designation state and output to the data line 47, the last word write signal in the packet is output from the address counter 23 onto the signal line 55. When the last word write signal in the packet is output to the signal line 55, the header information in the information (memory page address and header information of the first burst) on the control bus 52 is output to the output path control unit 30-1. If so, the (first burst) memory page address in the information on the control bus 52 is loaded into the transmission queue 32 as described above. At this time, the abort request signal output from the burst reception control section 25 (the reception control circuit 11 thereof) onto the signal line 46 is added to the memory page address as an abort request bit and is loaded into the transmission queue 32. As a result, if the 7-vote request bit is added to the memory page of the first burst of the next transmission target packet indicated by the transmission queue 32, the output route control unit 30-1 determines that the 7-vote request bit is specified by this memory page. Received bursts starting from the first burst (that is, shifted into the reception data FIFO 76 before determining non-reception and stored in the buffer memory 11
(the first half of the packet written in the burst) can be correctly discarded.

[Effects of the Invention] As detailed above, according to the present invention, a chaining information storage linkage memory accessed by the same control means as the storage/exchange buffer memory is used to handle bursts stored in the buffer memory. Since the pages scheduled to be stored in the buffer of continuous bursts are stored in the linkage memory, linkage processing for maintaining chaining of long packets can be performed easily and at high speed.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a burst packet switching switch to which the present invention is applied, FIG. 2 is a diagram showing the format of bursts constituting packets exchanged by the switch in FIG. 1, and FIG. 2 is a block configuration diagram showing a part of the internal configuration of the reception data FIFO section 21 and the burst reception control section 25 shown in FIG. 1. FIG. DESCRIPTION OF SYMBOLS 11... Buffer memory, 12... Linkage memory, 13-... Memory control unit, 14... Page management unit, 20-1°20-2... Input route control unit, 21...
Reception data FIFO unit, 22, 24.34...Register, 23.33...Address counter, 25...Burst reception control unit, 30-1.30-2...Output route control unit, 31 . . . Transmission data FIFO section, 32 . . . Transmission queue, 71 . . . Reception control circuit, 75 . . . Word counter. Applicant's agent Patent attorney Takehiko Suzue Figure 3

Claims (5)

[Claims] (1) A buffer memory that is managed by being divided into multiple memory pages and stores received packets in burst units, and the bursts to be stored in this buffer memory are captured from the line in word units and output to the buffer memory in the order in which they are captured. In a burst packet switch equipped with a first-in, first-out reception data buffer, each time one burst is stored in the buffer memory, the memory page to be used as the storage destination for the next burst to be stored is initialized, and the memory page is used as the storage destination for the next burst to be stored. a first address counter that generates a write address for the buffer memory; a second address counter that generates a read address for the buffer memory; and a second address counter that generates a read address for the buffer memory; A reserved memory page holding means for holding a target memory page, and a linkage memory provided for storing chaining information including the reserved memory page held in the holding means, the write being generated by the first address counter. The writing position is specified by the page specification part of the address,
managing empty pages of the linkage memory and the buffer memory in which the read position is specified by the page specification part of the read address generated by the second address counter;
page management means for outputting one of the free pages to the reserved memory page holding means as a reserved memory page for continuous bursts in response to a request from the reserved memory page holding means; and the beginning of the received packet stored in the buffer memory in burst units. A transmission queue for queuing burst storage memory pages, and either the first memory page indicated by this transmission queue or the memory page in the chaining information read from the linkage memory, as the next memory page to be read. and means for selectively loading the second address counter, and chaining a plurality of bursts constituting a long packet. (2) The burst linkage processing method according to claim 1, wherein the chaining information includes a linkage bit indicating whether or not a continuous burst exists. (3) if the linkage bit in the chaining information read from the linkage memory indicates the presence of a continuous burst, the memory page in the chaining information is loaded into the second address counter;
If it indicates that there is no continuous burst,
3. The burst linkage processing method according to claim 2, wherein the first memory page indicated by the transmission queue is loaded into the second address counter. (4) Determine reception/non-reception of the continuation burst according to the reception/non-reception of the preceding burst and the presence or absence of a memory page in the reserved memory page holding means, and control the shift input of the reception data buffer according to the result of this determination. 4. The burst linkage processing method according to claim 3, further comprising reception control means for performing the following. (5) A detecting means for detecting that the last word in a burst is shifted into the received data buffer, and from the time of detection by the detecting means until the arrival of the continuous burst, at least the last word of the last word is shifted into the received data buffer. 5. The burst linkage processing method according to claim 4, wherein output of the burst linkage processing method is prohibited.