JPH01136281A - Buffer memory control system - Google Patents

Abstract

PURPOSE:To balance a volume of data between buffer memories at the time of performing frame omission encoding by performing the switching of two buffer memories at a time shifted by a 1/2 unit frame time from the separation of an image frame. CONSTITUTION:Input data from a data input terminal 1 is inputted to first and second buffer memories 2 and 3 connected in parallel alternately. The timing of the write and read of the buffer memories 2 and 3 can be obtained by a clock counter circuit 13. The time counter circuit 13 outputs a switching signal at a point of time shifted by the 1/2 unit frame time from the separation of the frame. The data read out of the buffer memories 2 and 3 are derived via an output data switching circuit 4.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a buffer memory control method for smoothing the amount of encoded data generated within one frame when encoding an image, and particularly relates to a buffer memory control method for smoothing the amount of encoded data generated within one frame when encoding an image. This invention relates to a method for controlling memory switching.

[Conventional technology]

Conventionally, in this type of buffer memory control system, the buffer memory that performs a writing operation is switched in synchronization with the switching of frames of an input image, and data is read from the buffer memory that is not in the writing or writing operation.

[Problem that the invention seeks to solve]

However, in the conventional buffer memory control method described above, the buffer memory is not switched in synchronization with the switching of image frames. The buffer memory to which the received frame was written becomes empty, causing a large imbalance with the amount of data in the other buffer memory, which has the disadvantage that the amount of data cannot be sufficiently smoothed.

[Means for solving problems]

An object of the present invention is to provide a buffer memory control method that solves the above-mentioned drawbacks. For this reason, in the present invention, the two buffer memories are switched not at the frame division of the input image, but at a point shifted by 1/2 unit frame time from the frame division, and the image data for one frame is transferred into two buffer memories. The amount of data is balanced between the buffer memories when frame drop-off encoding is performed by splitting input into the buffer memories.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram illustrating one embodiment of the present invention. In FIG. 1, a circuit using the buffer memory control method of the present invention includes a first buffer memory 2 and a second buffer memory 3 connected in parallel to a data input terminal 1;
An output data switching circuit 4 is connected to the data terminals of these two buffer memories 2 and 3 and switches the data output to the output terminal 5, and generates a write address from the write clock input from the terminal 6 in synchronization with the input data. a write counting circuit 7 which generates a read address from a constant cycle read clock input from the transmission line side to a terminal 9; a first address switching circuit 8 for switching the output of the write counting circuit 7; a second address switching circuit 8 connected to the second buffer memory 3 and switching between the output of the reading counting circuit 10 and the output of the writing counting circuit 7;
The address switching circuit 11 receives from a terminal 12 a clock with a constant period synchronized with data at the beginning of the frame from an encoding unit (not shown) that generates input data, and switches to a time 180 degrees off from the frame break. It consists of a time counting circuit 13 that outputs a signal. This switching signal is applied to the first and second buffer memories 2 and 3, the output data switching circuit 4, the first and second address switching circuits 8 and 11, the write counting circuit 7, and the reading counting circuit lO. The state of the connected circuit is determined by the output level as shown in the table of FIG. 3, for example. Here, the inverter 14 is provided so that the two buffer memory circuits 2.3 are not in the same state.

Next, the operation will be explained with reference to FIG. Figure 2 is the first
3 is a timing chart of the figure. At the same time that input data a is input from terminal 1, a clock %C synchronized with the data is input from terminal 6, and a write address is generated in write counter circuit 7.

Since the output level of the time counting circuit 13 is Low, the input data is written to the second buffer memory 3 from the table of FIG. 3 (FIG. 2e). During this time, the data written in the previous frame unit time T is read from the first buffer memory 2 (FIG. 2 f), and is output from the terminal 5 (FIG. 2 k). One hour after the writing of input data to the second buffer memory 3 starts, or after the start of reading data from the first buffer memory 2, the output level of the time counting circuit 13 is inverted and becomes High.
When h is reached, the input data is written to the first buffer memory 2 (Fig. 2 d), and the input data is written to the second buffer memory 3.
The previously written data is read out from (FIG. 2g).

The problem here is the timing at which the time counting circuit 13 outputs the switching signal; as shown in FIG. 2, the switching signal is output at a time 1/2T time after the frame break in FIG. 2 aa. This phase is given by a delay circuit provided in the time counting circuit 13, but this 1/2T time shift is particularly effective when a frame drop occurs in the encoding section, and the operation at that time will be explained. In FIG. 2a, the shaded area is the part where the frame has been omitted. When a frame drop occurs, no data is supplied from the encoding section, and therefore no write clock C is input.

Here, if the buffer memory is switched at a frame break, no data will be written in the frame where the frame has been dropped, and an imbalance in the amount of data will occur between the two buffer memories 2 and 3, resulting in an increase in the amount of data. This prevents smoothing. Furthermore, generally speaking, if the buffer memory is switched at a point 1/2T time lag from the frame break, such as when a frame is dropped, the data in the frame unit time before and after the frame where the frame was dropped will be written to the buffer memory. less likely, and the imbalance will be smaller. FIG. 2 shows a case where the data supply speed performed within the frame unit time of the first and second half of the frame to be dropped is twice that of other frames. Further, the amount of data supplied from the encoding section is constant for a unit frame time, and the amount is equal to the number that can be read out by a read clock from the transmission line side within a unit frame time. Here, the write counting circuit 7 and the reading counting circuit 10 are reset at the same time as the buffer memory is switched by the reset signal i from the time counting circuit 13. [Effects of the Invention] As described above, the present invention is capable of switching between two buffer memories. By performing this at a point shifted by 1/2 frame time from the image frame separation, the data in one frame can be divided and input into two buffer memories, and even when a frame is dropped in the encoder, the data can be inputted. This has the effect of smoothing out the amount.

[Brief explanation of the drawing]

FIG. 1 is a block diagram explaining one embodiment of the present invention, and FIG.
The figure shows a timing chart explaining the operation of figure 1, and figure 3.
The figure is a table showing the states of each switching circuit and buffer memory according to the output level of the time counting circuit. In Figure 1, 1.6, 9.12... input terminals, 5...
・Output terminal, 2.3...Buffer memory, 4.
...Output data switching circuit, 8, 11...
Address switching circuit, 7...Write counting circuit, 1
0...readout counting circuit, 13...time counting circuit, 14...inverter. Agent Patent Attorney Oto Uchihara ♀ 1 picture = 9 tons ≦ 6 pieces

Claims (1)

[Claims] It has two buffer memories for temporarily storing data whose input speed is not constant and outputting it at a constant speed, and while writing data to one buffer memory, data is read from the other buffer memory, and these write/read operations are performed. In a buffer memory control method that switches at regular intervals, the data is encoded data of an image, and the fixed time is a unit frame time of the image, and the switching of the two buffer memories is performed at a frame break of the image. A buffer memory control method characterized in that the buffer memory control method is performed when there is a 1/2 unit frame time shift from .