JPH01134669A - Multiplyer with accumulator - Google Patents

Abstract

PURPOSE:To execute multiplication with accumulating operation by holding the output of array type multiplier, which equips a multiplying cell to obtain a full-adder as a base in a specified number, and inputted the holding output to the multiplying cell of a bit corresponding to the multiplier. CONSTITUTION:When a control signal CO is '1', Z7-Z1, which are the outputs of an all zeroing circuit 125, wholly go to be '0' and the value of an output Zn goes to be Xn-1XYn-1. When the control signal CO is '0', the Z1-Z3 among the Zn are given to a C-input of multiplying cells 104-106 and the Z4-Z6 are given to a B-input of multiplying cells 107, 111 and 115. Then, the Z6Z5Z4Z3Z2Z1 0 are added to the operation of XnXYn. Further, the Z7 is given to a latch 120 together with a Co-output of the multiplying cell 115 and added to a full- adder 124 after the latch and a value excepting for an LSB (Zo) of the output Zn is added to the multiplication of the XnXYn. Then, an output Zn+7 goes to be XnXYn+Zn. Thus, the multiplication can be executed together with the accumulating operation.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a multiplier, and more particularly to a multiplier with an accumulator.

2. Description of the Related Art In recent years, with the advancement of digital technology, there has been an increase in the number of audio devices in which filters are constructed from digital circuits. These audio devices usually use FIR (finite innocuous response) filters to flatten the phase characteristics of the signal, but since FIR filters have to perform many product-sum operations, they are equipped with multipliers and accumulators. The multiplication results are sequentially accumulated in an accumulator.

An example is shown in FIG. 3, and the operation will be explained.

In FIG. 3, 300 and 301 are latches, and input data xn (for example, audio data), Yn (
For example, the filter coefficients) are latched. 302 is a multiplier that multiplies the data given to the X and Y inputs;
Output from terminal Z.

303 is a latch, and the multiplication result based on the values from latches 300 and 301 is stored here.

An adder 304 adds data applied to input terminals A and B, and outputs the data to output terminals S and l:.

306 is a latch in which the output of the adder 304 is stored. Since the output of the latch 305 is applied to the B input of the adder 304, the latch 306 and the adder 304 perform an accumulation operation.

Problems to be Solved by the Invention However, in the above configuration, separate accumulators (in this case, the adder 304 and the latch 306) are required in addition to the multiplier in order to perform the accumulation operation, which increases the circuit size. There was a problem that the amount of

In view of the above problems, the present invention provides a multiplier with an accumulator that performs multiplication and accumulation without significantly increasing the circuit scale.

Means for Solving the Problems In order to solve the above problems, the multiplier with accumulator according to the present invention comprises an array-type multiplier having a specific number of multiplication cells based on full adders; This device includes a latch that holds the output, and also performs an accumulation operation by inputting the output of the latch to the multiplication cell of the corresponding bit of the multiplier.

Effect As mentioned above, since the multiplier output is returned to the conventionally unused terminal of the multiplication cell of the multiplier, it is possible to add the previous multiplication result while performing the multiplication operation. It is possible to perform multiplication and accumulation processing without adding an adder for an accumulator.

Example The present invention will be explained below based on the drawings.

FIG. 1 shows a multiplier with an accumulator according to a first embodiment of the present invention. In this embodiment, input data xn ("3
"2"1"O) and Yn (y3y2y1y□) are both 0 or positive numbers. In Fig. 1, 100 to 116 are multiplication cells. Input x, Y, B
, C, output S, and the relationship between C0 and Equation (1) and (2)
As shown in the formula.

s = (x, y)■B■C---(1)C0=(
X−Y)・(B+C)+B−C−−−−−−(2) Here, ■ indicates exclusive OR.

Here, input B, for example, multiplication ce/l/100.

Those that do not have C are assumed to have relational expressions whose value is fixed as 0'.

120 is a latch. 121 to 124 are full adders. The relationships between the inputs A, B, C, and the outputs S, C0 are as shown in equations (3) and (4).

S=A■B■Ci ・・・・・・・・・・・・
...(3)C-A-B+B-C1+C1-A...
(4) Here ■ indicates exclusive OR.

Reference numeral 126 denotes an all "0" circuit, which converts the data given to the input terminal A to all "0" and outputs it from the output terminal Y when the control signal Co given to the terminal C becomes "1".

Next, the operation of the circuit shown in FIG. 1 will be explained.

First, assuming that the control signal CO is "1", the outputs 27 to z1 of the O/l/"0" conversion circuit 125 will all be "0", so take into account that there will be a delay of one clock due to the latch 120. Therefore, it is clear that the value of the output Zn is as shown in equation (6).

Zn=xn-1×Yn-1...
When the control signal Co is “0”, z1 to z of the output zn
3 is the multiplication cell/I/C input of 104 to 106, z4 to z
6 is given to the B input of the multiplication cell/I/10a, 111, 115, so z e z s Z 4 z a
Z 2 Z 10 will be added to the xnxYn calculation. Furthermore, z7 is given to the latch 120 together with the C6 output of the multiplication cell/L' 115, and after latching, the full adder 12
4, so L S B (z
o ) will be added at the same time when xnxYn is multiplied. In other words, the value of output Zn+1 is the (6th
), and accumulation is performed along with multiplication.

Zn+1=XnxYn+Zn −・−−−−−
(e) FIG. 2 shows a second embodiment of the present invention.

In this embodiment, input data xn (x3x2x1xo
).

Y, (y3y2y1y□) is two's complement (2's com
The case of an integer (-8 to +7) expressed as pliment is shown. Components having the same functions in FIG. 2 are denoted by the same reference numerals, and explanations in pongagana will be omitted. 200 to 216 are multiplication cells. input
, Y, B, C and the outputs s and c0 are expressed as (
'7) and equation (8).

s = (x-y)■B■C・・・−・・−(7)C0
=(X-Y) ・(B+C)+B-C=...Old(8)
Here ■ indicates exclusive OR.

Note that NX and NY in the multiplication cells 1v203 to 206 and 212 to 214 are obtained by inverting the input signal to obtain equation (7).

This means performing the calculation of equation (8). E. For multiplications such as /I/2oo that do not have inputs B and C, the relational expression is assumed to be such that the value is fixed as "0". 220 is a latch.

Next, the operation of the circuit shown in FIG. 2 will be explained.

First, assuming that the control signal Co is "1", the outputs 26 to z1 of the all "0" conversion circuit 125 are all "0", so the circuit shown in FIG. 2 is a normal two's complement representation. Since the configuration is the same as that of the multiplier, the latch 22
Considering that there is a delay of one clock due to zero, the output Zn
It is clear that the value of is as shown in equation (9).

Zn=xn-1×Yn-1''---(9) Control signal C
When o is "0", z1 to z3 of the output Zn are input to the C inputs of the multiplication cells 2o6 to 2o8, and z4 to z6 are input to the multiplication cells/L.
/204.205.215 is given to the B input, so Z 6 Z 5 Z 4 Z 3 Z 2 zlo
will be added to the calculation of xnxYn. Therefore,
The value of output Zn excluding L S B (zo) is xnxY
They are added simultaneously during multiplication by n. In other words,
The value of the output Zn+1 is as shown in equation (1Q), and multiplication and accumulation are performed.

Z =X xY +Z・・・・・・・・・
...(1o)n+1 n n
nIn addition, in the above embodiment, the scale of the multiplier is 4.
Although the number of bits x 4 bits is used, it goes without saying that it can be constructed with an even larger number of focus points. Also,
The number of bits of the multiplication result being fed back to the multiplication cell for accumulation does not necessarily have to be all the bits of the multiplication result. Although the position of 10 x 1 degree square 120, 220 is assumed to be the front stage of the full adders 121 to 124, it is not limited to this position, and may be connected to the output stage of the full adders 121 to 124, for example. Needless to say.

Effects of the Invention As described above, the present invention includes an array-type multiplier that is based on a full adder and has a specific number of multiplication cells, and a latch that holds the output of the multiplier. By inputting into the multiplication cell of the corresponding pit, the previous multiplication result can be added while performing the multiplication operation.
This has an excellent effect in that an accumulation operation can be performed without adding a new element.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of a multiplier with an accumulator according to the present invention, FIG. 2 is a block diagram showing another embodiment of the multiplier with an accumulator according to the present invention, and FIG. 3 is a block diagram showing a conventional multiplier with an accumulator. FIG. 2 is a block diagram showing an accumulator and a multiplier in the device. 100-115...Multiplication cell, 120...
... Latch, 121-124 ... Full adder, 1
26...oh)v "○" conversion circuit, 200~
216...Multiplication cell, 220...Latch.

Claims (1)

[Claims] An array type multiplier having a specific number of multiplication cells based on a full adder, and a latch that holds the output of the multiplier, and the output of the latch is input to the multiplication cell of the corresponding bit of the multiplier. A multiplier with an accumulator characterized in that it also has an accumulation operation.