JPH01131939A - Cache memory access device - Google Patents

Cache memory access device

Info

Publication number
JPH01131939A
JPH01131939A JP62290220A JP29022087A JPH01131939A JP H01131939 A JPH01131939 A JP H01131939A JP 62290220 A JP62290220 A JP 62290220A JP 29022087 A JP29022087 A JP 29022087A JP H01131939 A JPH01131939 A JP H01131939A
Authority
JP
Japan
Prior art keywords
data
width
cache memory
written
main storage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP62290220A
Other languages
Japanese (ja)
Other versions
JPH0621999B2 (en
Inventor
Masahiro Ito
Original Assignee
Yokogawa Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Yokogawa Electric Corp filed Critical Yokogawa Electric Corp
Priority to JP62290220A priority Critical patent/JPH0621999B2/en
Publication of JPH01131939A publication Critical patent/JPH01131939A/en
Publication of JPH0621999B2 publication Critical patent/JPH0621999B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Abstract

PURPOSE: To easily constitute a device and to improve access efficiency by providing an access control part to output a control signal which makes access with entire data width at the time of reading out data and to output a write indication signal only to a main storage when write data with the data width less than the entire data width is written.
CONSTITUTION: At the time of reading out the data or a program by a central processing unit 1, the data is read out with the entire data width in a hit state, then, only required data width is read out, and in a missed state, the data is read out with the entire data width from the main storage and the valid bit of a write tag part 4 is set as valid in a cache memory. At the time of writing the data by the central processing unit 1, the data is written on the cache memory and the main storage with the entire data width shown by the central processing unit 1 in the hit state, and the data is written on the cache memory and the main storage with the width when the central processing unit 1 writes the data with the entire data width in the missed state, and the data is written only on the main storage when the data is written with the data with less than the entire data width. In such a way, it is possible to obtain a cache memory access device having superior access efficiency with simple constitution.
COPYRIGHT: (C)1989,JPO&Japio
JP62290220A 1987-11-17 1987-11-17 Cache memory access device Expired - Lifetime JPH0621999B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62290220A JPH0621999B2 (en) 1987-11-17 1987-11-17 Cache memory access device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62290220A JPH0621999B2 (en) 1987-11-17 1987-11-17 Cache memory access device

Publications (2)

Publication Number Publication Date
JPH01131939A true JPH01131939A (en) 1989-05-24
JPH0621999B2 JPH0621999B2 (en) 1994-03-23

Family

ID=17753310

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62290220A Expired - Lifetime JPH0621999B2 (en) 1987-11-17 1987-11-17 Cache memory access device

Country Status (1)

Country Link
JP (1) JPH0621999B2 (en)

Also Published As

Publication number Publication date
JPH0621999B2 (en) 1994-03-23

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