JPH01128534A - Mounting method for semiconductor element on transparent substrate - Google Patents

Mounting method for semiconductor element on transparent substrate

Info

Publication number
JPH01128534A
JPH01128534A JP28788087A JP28788087A JPH01128534A JP H01128534 A JPH01128534 A JP H01128534A JP 28788087 A JP28788087 A JP 28788087A JP 28788087 A JP28788087 A JP 28788087A JP H01128534 A JPH01128534 A JP H01128534A
Authority
JP
Japan
Prior art keywords
bump
glass substrate
light shielding
chip
light
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP28788087A
Inventor
Shinichiro Ishihara
Seiichi Nagata
Original Assignee
Matsushita Electric Ind Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Ind Co Ltd filed Critical Matsushita Electric Ind Co Ltd
Priority to JP28788087A priority Critical patent/JPH01128534A/en
Publication of JPH01128534A publication Critical patent/JPH01128534A/en
Application status is Pending legal-status Critical

Links

Abstract

PURPOSE: To shield a light at an IC chip simultaneously during the manufacture of a semiconductor element and to further reduce the stray capacitance due to wirings by forming a light shielding film during manufacturing step of a FET, shielding a light incident from a glass substrate, and setting a distance between a conductive material and the film to a specific value or less.
CONSTITUTION: A light shielding gate electrode 2 is formed of Cr on a glass substrate 1. A light shielding layer 3 of a COG region is held at a ground potential or a predetermined potential. The height 50 of bump for connecting an IC chip 1 to a wiring conductive film 9 by a COG bump 10 is so set that the distance between a wiring conductive film 9 and the chip 11 becomes 1$μm or more. This is because, if a dust is engaged, it might be short-circuited. Further, this is because, when the height 50 of the bump is set 10μm or more, the forming accuracy of the bump itself is deteriorated. In order to complete as a liquid crystal display, an opposite glass substrate containing a color filter, opposite electrode, etc., is disposed on a TFT region isolated at 1mm or more from the chip 11.
COPYRIGHT: (C)1989,JPO&Japio
JP28788087A 1987-11-13 1987-11-13 Mounting method for semiconductor element on transparent substrate Pending JPH01128534A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP28788087A JPH01128534A (en) 1987-11-13 1987-11-13 Mounting method for semiconductor element on transparent substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP28788087A JPH01128534A (en) 1987-11-13 1987-11-13 Mounting method for semiconductor element on transparent substrate

Publications (1)

Publication Number Publication Date
JPH01128534A true JPH01128534A (en) 1989-05-22

Family

ID=17722925

Family Applications (1)

Application Number Title Priority Date Filing Date
JP28788087A Pending JPH01128534A (en) 1987-11-13 1987-11-13 Mounting method for semiconductor element on transparent substrate

Country Status (1)

Country Link
JP (1) JPH01128534A (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0281529U (en) * 1988-12-12 1990-06-22
JPH04242724A (en) * 1990-12-25 1992-08-31 Semiconductor Energy Lab Co Ltd Liquid crystal display device
US5701167A (en) * 1990-12-25 1997-12-23 Semiconductor Energy Laboratory Co., Ltd. LCD having a peripheral circuit with TFTs having the same structure as TFTs in the display region
US5859445A (en) * 1990-11-20 1999-01-12 Semiconductor Energy Laboratory Co., Ltd. Electro-optical device including thin film transistors having spoiling impurities added thereto
US7123323B2 (en) 2000-04-11 2006-10-17 Nec Corporation Liquid crystal display device with conductive light shielding film and contact holes
US7148529B2 (en) * 2001-03-30 2006-12-12 Kabushiki Kaisha Toshiba Semiconductor package
KR100870002B1 (en) * 2001-12-17 2008-11-21 삼성전자주식회사 Liquid crystal display

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0281529U (en) * 1988-12-12 1990-06-22
US5859445A (en) * 1990-11-20 1999-01-12 Semiconductor Energy Laboratory Co., Ltd. Electro-optical device including thin film transistors having spoiling impurities added thereto
US6011277A (en) * 1990-11-20 2000-01-04 Semiconductor Energy Laboratory Co., Ltd. Gate insulated field effect transistors and method of manufacturing the same
JPH04242724A (en) * 1990-12-25 1992-08-31 Semiconductor Energy Lab Co Ltd Liquid crystal display device
US5701167A (en) * 1990-12-25 1997-12-23 Semiconductor Energy Laboratory Co., Ltd. LCD having a peripheral circuit with TFTs having the same structure as TFTs in the display region
US7123323B2 (en) 2000-04-11 2006-10-17 Nec Corporation Liquid crystal display device with conductive light shielding film and contact holes
US7148529B2 (en) * 2001-03-30 2006-12-12 Kabushiki Kaisha Toshiba Semiconductor package
KR100870002B1 (en) * 2001-12-17 2008-11-21 삼성전자주식회사 Liquid crystal display

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