JPH01120819A - Aligner - Google Patents

Aligner

Info

Publication number
JPH01120819A
JPH01120819A JP62278706A JP27870687A JPH01120819A JP H01120819 A JPH01120819 A JP H01120819A JP 62278706 A JP62278706 A JP 62278706A JP 27870687 A JP27870687 A JP 27870687A JP H01120819 A JPH01120819 A JP H01120819A
Authority
JP
Japan
Prior art keywords
reticle
error
pattern
mark
alignment
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP62278706A
Other languages
Japanese (ja)
Other versions
JPH0650715B2 (en
Inventor
Masao Kosugi
Hideo Haneda
Masao Totsuka
Makoto Torigoe
Original Assignee
Canon Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Canon Inc filed Critical Canon Inc
Priority to JP62278706A priority Critical patent/JPH0650715B2/en
Publication of JPH01120819A publication Critical patent/JPH01120819A/en
Publication of JPH0650715B2 publication Critical patent/JPH0650715B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Abstract

PURPOSE: To correct a system error created when a pattern on the surface of a 1st object is aligned and transcripted onto the surface of a 2nd object satisfactorily and maintain highly accurate alignment by a method wherein the image focusing status of the image of an alignment pattern formed on a 3rd object is detected to obtain the system error.
CONSTITUTION: A light beam from a lighting system 4 is applied to a reticle 2 which is a 1st object held by a platen 6. The pattern of an electronic circuit or the like formed on the surface of the reticle 2 is projected and transcripted onto the surface of a wafer 3 which is a 2nd object by a projection lens 1. A reticle microscope 7 for aligning the reticle 2 with a reticle reference mark 5 is provided on the side of the reticle 2 opposite to the side of the wafer 3. The relative position error between a reticle setting mark formed on the reticle 2 and the reticle reference mark 5 is read by the reticle microscope 7 and the reticle 2 and the platen 6 are driven by a reticle stage 8 so as to make the relative position error close to zero to achieve the reticle alignment.
COPYRIGHT: (C)1989,JPO&Japio
JP62278706A 1987-11-04 1987-11-04 Exposure method and device manufacturing method using the same Expired - Fee Related JPH0650715B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62278706A JPH0650715B2 (en) 1987-11-04 1987-11-04 Exposure method and device manufacturing method using the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62278706A JPH0650715B2 (en) 1987-11-04 1987-11-04 Exposure method and device manufacturing method using the same

Publications (2)

Publication Number Publication Date
JPH01120819A true JPH01120819A (en) 1989-05-12
JPH0650715B2 JPH0650715B2 (en) 1994-06-29

Family

ID=17601056

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62278706A Expired - Fee Related JPH0650715B2 (en) 1987-11-04 1987-11-04 Exposure method and device manufacturing method using the same

Country Status (1)

Country Link
JP (1) JPH0650715B2 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03219615A (en) * 1990-01-25 1991-09-27 Canon Inc Dummy wafer for aligner
US5993043A (en) * 1996-11-29 1999-11-30 Nec Corporation Lithography processing apparatus for manufacturing semiconductor devices
US6826743B2 (en) 2001-10-11 2004-11-30 Samsung Electronics Co., Ltd. Method for automatically correcting overlay alignment of a semiconductor wafer

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03219615A (en) * 1990-01-25 1991-09-27 Canon Inc Dummy wafer for aligner
US5993043A (en) * 1996-11-29 1999-11-30 Nec Corporation Lithography processing apparatus for manufacturing semiconductor devices
US6826743B2 (en) 2001-10-11 2004-11-30 Samsung Electronics Co., Ltd. Method for automatically correcting overlay alignment of a semiconductor wafer

Also Published As

Publication number Publication date
JPH0650715B2 (en) 1994-06-29

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Legal Events

Date Code Title Description
LAPS Cancellation because of no payment of annual fees