JPH01119110A - Solid-state power amplifier - Google Patents

Abstract

PURPOSE:To prevent an amplifier at a succeeding stage from being overdriven by comparing the output level of the amplifier part at a preceding stage with a reference level, and controlling a bias voltage in a direction to lower the gain of the amplifier part at the preceding stage when a detected level exceeds the reference level. CONSTITUTION:The output of an excitation amplifier part 4 is distributed to a high output amplifier part 5 and a detector 7 by a power, distributor 6, and a detected voltage VA obtained by detection by the detector 7 is inputted to a bias voltage control circuit 8. The bias voltage control circuit 8 controls the bias voltage of a transistor so as to lower the gain of an amplifier 3A when the detected voltage VA exceeds a reference voltage VR. In such a way, by deciding the reference voltage VR so as not to set the input level of the high output amplifier part 5 at an over driving level, it is possible to prevent the input level of the high output amplifier part 5 from being overdriven even when the over driving level is inputted to a solid-state power amplifier.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a solid-state power amplifier, particularly to a solid-state power amplifier for use on a satellite.

[Prior Art] Solid-state power amplifiers tend to be widely used as high-power amplifiers onboard satellites because they are small, lightweight, and highly reliable. FIG. 3 is a block diagram showing a conventional solid-state power amplifier. As shown in the figure, a signal input from an RF input terminal 1 is amplified by an excitation amplification section 4 to an input level required for a high output amplifier 5. The signal amplified by the excitation amplification section 4 is amplified to a desired output power by the high output amplification section 5 and output from the RF output terminal 2.

[Problem that the invention seeks to solve]

When the solid-state power amplifier described above is used onboard a satellite, a level higher than the normal input level (overdrive level) may suddenly be input due to various factors. When an overdrive level is input to the solid-state power amplifier, the transistor used in the first-stage amplifier 3E of the high-output amplification section 5 enters an excessive input state.
In the aAsFET, this causes deterioration of the transistor such as an increase in gate leakage current.

However, the above-mentioned conventional solid-state power amplifier does not have any countermeasures against the input of the 20 overdrive level, so there is a problem that the transistor is easily deteriorated and the reliability for use on a satellite is reduced.

An object of the present invention is to provide a solid-state power amplifier with improved reliability by taking measures against overdrive levels.

[Means for Solving the Problems] The solid-state power amplifier of the present invention includes a power divider for distributing the output of a preceding stage of a plurality of amplifier parts connected in series, and a power divider for distributing the output of the preceding stage amplifier part, and and a bias voltage control circuit that controls the bias voltage of the preamplifier based on the detection level of the detector, and the bias voltage control circuit uses the detection level as a reference. The configuration is such that when the detected level exceeds the reference level, the bias voltage is controlled in such a direction as to reduce the gain of the front-stage amplifier section, thereby preventing overdrive.

〔Example] Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention, and the same parts as in the conventional example of FIG. 3 are designated by the same reference numerals.

In this figure, numeral 1 is an RF input terminal, and 2 is an RF output terminal. The solid-state power amplifier is roughly divided into an excitation amplification section 4 and a high-output amplification section 5, each consisting of a plurality of amplifiers. Here, the excitation amplification section 4 includes four amplifiers 3A to 3D.
The high output amplifying section 5 is composed of two amplifiers 3E and 3F.

A power divider 6 is connected to the output side of the excitation amplification section 4, and a part of the signal output from the excitation amplification section 4 to the high output amplification section 5 is extracted. A detector 7 is connected to the power divider 6 to detect the output as a voltage. Furthermore, a bias voltage control circuit 8 is connected to this detector 7, and this bias voltage control circuit 8 receives the output voltage of the detector 7, and a bias voltage is supplied to a bias supply terminal 9, and A reference voltage is supplied to the reference voltage supply terminal 10. After comparing the detected voltage with a reference voltage, the bias voltage supplied to the bias supply terminal 9 is controlled, and the bias voltage is outputted to the bias supply line 11. This bias supply line 11 is
It is connected to the bias supply terminal of the amplifier 3A, which is used as a linear amplifier at a low level among the amplifiers in the excitation amplification section 4.

Therefore, according to this configuration, the output of the excitation amplifier section 4 is distributed by the power divider 6 to the high output amplifier section 5 and the detector 7, and the detected voltage 1 obtained by detection by the detector 7 is applied to the bias voltage control circuit. 8 is input. The bias voltage control circuit 8 controls the bias voltage of the transistor so as to reduce the gain of the amplifier 3A when the detected voltage (1) becomes equal to or higher than the reference voltage v7. Therefore, if the reference voltage (6) is determined so that the input level of the high-output amplifier section 5 does not reach the overdrive level, even if the overdrive level is input to the solid-state power amplifier, the input level of the high-output amplifier section 5 It is possible to prevent the input level from becoming overdrive.

FIG. 2 is a graph showing the characteristics of the input level of the present embodiment and the conventional solid-state power amplifier versus the input level of the high-output amplifier. As can be seen from this figure, in the configuration of FIG. 1, even if an overdrive level is input to the solid-state power amplifier, the input level of the high output amplifier section 5 does not become overdrive.

In this embodiment, the power distribution circuit 6 is connected between the excitation amplification section 4 and the high output amplification section 5, but it goes without saying that the same effect can be obtained even if the power distribution circuit 6 is connected at another location.

Furthermore, when the bias voltage control circuit 8 is connected to the bias supply lines of two or more amplifiers, for example, the amplifiers 3A and 3B, it is obvious that the range corresponding to overdrive becomes wider.

[Effects of the Invention] As described above, the present invention allows a bias voltage control circuit to control the bias voltage of the preceding amplifier section among a plurality of amplifier sections connected in series, and this bias voltage control circuit: The output level of the preamplifier is compared with the reference level, and when the detection level exceeds the reference level, the bias voltage is controlled in the direction of reducing the gain of the preamplifier, so if an overdrive level is input. However, the subsequent amplifier section does not become overdriven, which prevents transistor deterioration and improves the reliability of the amplifier. This is very useful when the solid-state power amplifier of the present invention is used onboard a satellite, since high reliability can be obtained.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing one embodiment of the solid-state power amplifier of the present invention, and Fig. 2 shows the characteristics of the input level of the present embodiment and the conventional solid-state power amplifier versus the input level of the high-output amplification section. The graph shown in FIG. 3 is a block diagram showing a conventional solid-state power amplifier. 1...RF input terminal, 2...RF output terminal, 3A~
3F...Amplifier, 4...Excitation amplifier, 5...High output amplifier, 6...Power divider, 7...Detector, 8...
...Bias voltage control circuit, 9...Bias supply terminal, 10...Reference voltage supply terminal, 11...Bias supply line, V...Detection voltage, ■ and...Reference voltage.

Claims (1)

[Claims] (1) In a solid-state power amplifier in which multiple amplifier sections are connected in series, there is a power divider that distributes the output of the preceding stage amplifier section, a detector that detects the output level extracted from this power divider, and and a bias voltage control circuit that controls the bias voltage of the preamplifier based on the detection level of the wave detector, and the bias voltage control circuit compares the detection level with a reference level and determines that the detection level exceeds the reference level. 1. A solid-state power amplifier characterized in that the bias voltage can be controlled in a direction that sometimes lowers the gain of a preamplifier.