JPH01119059A - Manufacture of thin-film transistor matrix - Google Patents

Abstract

PURPOSE:To decrease the number of masks for patterning of each constitution element, to simplify fabrication process, and to improve yield by forming a contact hole for connecting the drain electrode to the gate buss line using the side etching and lift-off method. CONSTITUTION:After a transparent conductive film 22, an n<+> type hydrogen amorphous silicon film 23, and a chrome film 24 are coated on an insulation transparent substrate 21, source electrode, drain electrode, and resist pattern for forming display electrode are formed, the above three layers are subject to patterning, and then the chrome film 24 which was subject to patterning is side-etched. Then, a semiconductor layer 25 of oxygen amorphous silicon and a gate insulation film 26 of nitriding silicon are coated on the surface of entire substrate and lift-off by etching the chrome film is performed to form a contact hole 27. Then, an aluminum film 28 is coated on the surface of the entire substrate, resist pattern for forming gate electrode is formed, patterning is performed, and then a gate buss line 35 and a gate electrode 36 are formed. At the same time, A TFT 37 is formed for each display transparent electrode 34 to constitute TFT matrix.

Description

[Detailed Description of the Invention] [Summary] Regarding a method for manufacturing a thin film transistor matrix configured in a liquid crystal display panel, etc. using an active matrix drive method, a mask for patterning each component by streamlining the formation process of the thin film transistor matrix is provided. In order to reduce the number of steps and thereby reduce manufacturing costs, a transparent conductive film and an n-conductivity type hydrogenated amorphous silicon film and a first metal film are sequentially coated on an insulating transparent substrate. After arriving,
A step of forming a resist pattern for forming a source electrode, a drain electrode, and a display electrode on the first metal film, patterning the three-layer film using the pattern as a mask, and side etching the patterned first metal film. a step of sequentially depositing a semiconductor layer and a gate insulating film on the entire substrate surface including the first metal film, and then performing lift-off using the first metal film as a mask to form a contact hole; After depositing the second metal film on the entire surface including the holes, a resist pattern for forming a gate electrode is formed, and using that pattern as a mask, the second metal film, the gate insulating film, the semiconductor layer, and the n-conductivity type are formed. A gate electrode is formed by patterning the hydrogenated amorphous silicon film.

[Industrial application field]

The present invention relates to a method of manufacturing a thin film transistor matrix configured in a liquid crystal display panel or the like using an active matrix driving method.

A thin film transistor (Thin Film T) is used for each pixel.
An active matrix drive type liquid crystal display panel that uses a ran-sister (hereinafter referred to as TPT) as an active element can drive a large number of pixels independently, so as the display capacity increases, the screen speed increases. Even if the number of campus lines, data bus lines, etc. increases, the advantage is that there is no problem such as a decrease in drive duty ratio, which causes a decrease in contrast or a decrease in viewing angle, unlike in simple matrix drive LCD panels. There is.

In addition, because the panel configuration is flat, low power consumption, and clear full-color display can be achieved, it is suitable for use in small TVs and various office automation equipment.
Research and development is currently underway for use in display terminals.

There is a need for a method that has a high manufacturing yield and can be manufactured at low cost for the TPT matrix constructed in such a liquid crystal display panel.

[Conventional technology]

Conventionally, as a TPT matrix that eliminates short-circuit defects caused by intersecting pass lines and improves manufacturing yield, scan path lines are placed on one insulating transparent substrate and data bus lines are placed on the opposite insulating transparent substrate. A crossover between these scan path lines and data bus lines is provided.

A gate-connected opposed matrix system without a bar has already been proposed.

To form such a TPT matrix,
Main part plan view in Fig. 5(a) and AA' in Fig. 5(b)
As shown in the cross-sectional view, ITO (Indium Tin), which is a transparent electrode material, is placed on an insulating transparent substrate 1 such as a glass plate.
A transparent conductive film 2 made of a material such as 0xide) and an n1 conductivity type hydrogenated amorphous silicon film (hereinafter referred to as n"-a-Si:H film) 3 for ohmic contact are deposited, and the n"-a-St: A source electrode (not shown) on the H film 3,
A resist pattern for forming a drain electrode and a display electrode is formed, and using the pattern as a mask, the n''-a-Si
: By selectively etching and removing the H film 3 and the transparent conductive film 2, the scan path line 11 and the drain electrode 1 are formed.
2. Patterning the source electrode 13 and the display transparent electrode 14.

Next, the main part plan view of Figure 6 (a) and A of Figure 6 (b)
-A” patterned n+-a as shown in the cross-sectional view
After depositing an active semiconductor layer 4 made of hydrogenated amorphous silicon (a-3i:H) and a gate insulating film 5 made of silicon nitride (SiJ4) on the insulating transparent substrate 1 including the -5i:H film 3, A drain electrode 1 is formed on the gate insulating film 5.
2 and the gate pass line 16, a resist pattern (not shown) for forming a contact hole is formed,
By selectively etching and removing the gate insulating film 5, the active semiconductor layer 4, and the n''-a-St:H film 3 using the pattern as a mask, a contact hole 15 through which the transparent conductive film 2 is exposed is formed. .

After that, the main part plan view of FIG. 7(a) and FIG. 7(b)
As shown in the A-A'' cross-sectional view, an aluminum (^2) film 7 is deposited on the insulating transparent substrate 1 including the contact hole 15, and a resist pattern for forming a gate electrode ( ), and using the resist pattern as a mask, the AjJg 17, the gate insulating film 5, the active semiconductor layer 4, and the n''-a-St:H film 3 are selectively etched away, thereby forming the gate electrode 17. , the gate pass line 16 is patterned as shown by the grid shape in the figure, and a TF is formed for each display transparent electrode 14 whose surface is exposed.
It forms T18.

[Problem that the invention seeks to solve]

By the way, as mentioned above, in the conventional process of forming a TPT matrix, since masks are made to correspond to each other in order to pattern each component, the number of masks (three masks in the conventional example) increases, and the number of steps increases. There were problems such as an increase in manufacturing costs and a decrease in yield.

In view of the above-mentioned conventional situation, the present invention aims to streamline the TPT matrix formation process, reduce the number of masks for patterning each component, reduce the number of steps, and thereby reduce manufacturing costs. The object of the present invention is to provide a method for manufacturing a matrix.

[Means for solving problems]

In order to achieve the above-mentioned object, the present invention sequentially deposits a transparent conductive film and an n-conductivity type hydrogenated amorphous silicon film and chromium film on an insulating transparent substrate made of a glass plate or the like, and then A resist pattern for forming a source electrode, a drain electrode, and a display electrode is formed on the chromium film, and the three layers are patterned using the pattern as a mask. At the same time, the patterned chromium film is side-etched.

Next, a semiconductor layer made of hydrogenated amorphous silicon and a gate insulating film made of silicon nitride are sequentially deposited on the entire substrate surface including the chromium film, and then the chromium film is lifted off by etching to form a contact hole. do.

Next, after depositing an aluminum film on the entire surface of the substrate including the contact hole, a resist pattern for forming a gate electrode is formed, and using this pattern as a mask, the aluminum film, gate insulating film, semiconductor layer and n-conductor are formed. By performing a step of patterning a conductive hydrogenated amorphous silicon film, a gate pass line and a gate electrode are patterned, and a TPT is formed for each display transparent electrode whose surface is exposed to form a TPT matrix.

[For production]

In the method for manufacturing the TPT matrix of the present invention described above,
By applying side etching and lift-off methods to form contact holes for connecting the drain electrode and gate pass line, without using conventional masks for forming contact holes, the number of masks for patterning each component can be reduced. The number of steps can be reduced, and the number of mask alignments can also be reduced. As a result, high precision and high yield can be achieved, and costs can be reduced.

〔Example〕

An embodiment of the method for manufacturing a TPT matrix of the present invention will be described in detail below with reference to the drawings.

First, the main part plan view in Figure 1(a) and A- in Figure 1Cb)
As shown in the A-plane view, I
A transparent conductive film 22 made of O (Indium Tin Oxide) or the like is deposited to a thickness of 300 mm, and an ohmic contact film 22 is deposited on its surface by plasma CVD.
3 conductivity type hydrogenated amorphous silicon film (hereinafter referred to as n”-a
-5i:H film) 23 is deposited to a thickness of 200 nm, and a first metal film, for example, a chromium (Cr) film 24 is deposited on the n+-a-Si:H film 23 by electron beam evaporation or the like. was deposited to a thickness of 1 μm.

Next, a resist pattern (not shown) for forming a source electrode, a drain electrode, and a display electrode is formed on the Cr film 24, and using the pattern as a mask, the three-layer film 24.
．． After patterning the scan path line 31, the drain electrode 32, the source electrode 33, and the display transparent electrode 34 by selectively etching away the Cr film 24, side etching of the patterned Cr film 24 is simultaneously performed.

At this time, portions of the Cr film 24 on, for example, the drain electrode 32 pattern and the source electrode 33 pattern that are below a certain width are etched away, and the Cr film 24 after side etching is
It remains in the shaded area shown in FIG. 1(a).

Next, the main part plan view of Figure 2 (a) and A of Figure 2 (with)
As shown in the -A° cross-sectional view, hydrogenated amorphous silicon (a-Si:H) with a thickness of 800 mm is deposited on the fully insulating transparent substrate 21 including the Cr film 24 by plasma CVD.
A semiconductor layer 25 consisting of 30
A gate insulating film 26 made of silicon nitride (SiJ4) having a thickness of 0.00 mm is sequentially deposited.

After that, the main part plan view of Figure 3 (a) and A of
As shown in the -A' cross-sectional view, by selectively removing only the Cr film 24 using an etching solution containing, for example, ceric ammonium nitrate as a main component, the semiconductor on the Cr film 24 is removed. The contact hole 27 is formed by performing so-called lift-off, in which the layer 25 and the gate insulating film 26 are also removed. At this time, Cr on the display transparent electrode 34
The film 24, gate insulating film 26, and semiconductor 125 are also removed.

Subsequently, the fully insulating transparent substrate 2 including the contact hole 27
A second metal film, for example 5, is deposited on 1 by electron beam evaporation.
An aluminum (i) film 28 having a thickness of 1,000 mm is deposited.

Next, the main part plan view of Fig. 4(a) and A- of Fig. 4(b).
As shown in the A'' cross-sectional view, a resist pattern (not shown) for forming a gate electrode is formed on the Af film 28, and using that pattern as a mask, the AN film 28 and the gate insulating film 2 are formed.
6. By selectively etching and removing the semiconductor layer 25 and the n'''-a-5i:H film 23, the gate pass line 35 and gate electrode 36 shown in a mesh shape in the figure are patterned, and the surface is Exposed display transparent electrode 34
A TFT matrix can be formed by forming a TFT 37 for each.

〔Effect of the invention〕

As is clear from the above description, according to the method for manufacturing a thin film transistor matrix according to the present invention, the side etching and lift-off methods are used without using a mask in the process of forming a contact hole for connecting the drain electrode and the gate pass line. By applying this, the number of patterning masks for each component can be reduced from the conventional three to two, and the number of mask alignments is also reduced, simplifying the manufacturing process and improving pattern accuracy and yield. However, it has practical effects such as cost reduction.

[Brief explanation of the drawing]

1(a), (b) to FIG. 4(a), (b) are diagrams illustrating an embodiment of the method for manufacturing a thin film transistor matrix according to the present invention in the order of steps, and each diagram (a) shows the main points. Part plan view, each figure [available]) is
5(a), (b) to FIG. 7(a), (b) show an example of a conventional thin film transistor matrix manufacturing method. These figures are for explaining in order, each figure (a) is a plan view of the main part, each figure (b) is each figure (a)
FIG. 2 is a sectional view of a main part taken along the line AA' shown in FIG. Figure 1 (a), (b) to Figure 4 (a), Cb''H
':-Oite, 21 is an insulating transparent substrate, 22 is a transparent conductive film, 23 is an n''-a-5t:H film, 24 is a Cr film, 25
is a semiconductor layer, 26 is a gate insulating film, 27 is a contact hole, 28 is an Al film, 31 is a scan path line, 32 is a drain electrode, 33 is a source electrode, 34 is a display transparent electrode,
35 is a gate pass line, 36 is a gate electrode, 37 is a T
PT is shown respectively. 23n + - α - 5j: H Ken ≧ Tome 5g IL ^ “Leii g゛ Coco γ → => r / lr Ne Shikatsu A-A” 1st page Octopus 1
Fig. fQ) Fig. 1 (b) Unexploded eel, Tsukasukata Benisha's A-A' vinegar convex m Fig. 2 (Qn Fig. 2 (b) 4 Kangzuki Ako) ri7) Ti-Al)lJ! -Month 5F (
Energy f diagram Bar A'r - Medium i [m Figure 3 I
QI Figure 3 (b) 44g Kameri 1'-1
- Look after '! to the shape of A〉2￥Figure A
-4' Rih cup tag Figure 4 (Q) Figure 4 [
b) Lutanso 2,5iJlnfflV7->fifl
'rnei figure, 1l-A'l'ili mouth 1 sword figure 5 (Ql
Figure 5 (b) Tlh > 77riCr
ff'rFS:, Lt'ZrflJ
A-A'17mrMFigure 6+a) Figure 6+b) Valley ε4 gate fMIy9->Mff'jF
Also 'Isu1 Figure A-A'! l
j664 Figure 7 (Q) Figure 7 (b)

Claims (1)

[Claims] A transparent conductive film (22) on an insulating transparent substrate (21) and an n
^+ After sequentially depositing the conductive type hydrogenated amorphous silicon film (23) and the first metal film (24), a source electrode (33) and a drain electrode (32) are deposited on the first metal film (24).
) and a display electrode (34), and using the pattern as a mask, the three-layer film (22,
23, 24), and side-etching the patterned first metal film (24) to form a semiconductor layer (25) and a gate insulating film on the entire substrate surface including the first metal film (24). (26) and then lift-off using the first metal film (24) as a mask to form a contact hole (27); After depositing the second metal film (28), a resist pattern for forming the gate electrode (36) is formed, and using this pattern as a mask, the second metal film (28), the gate insulating film (26), and the semiconductor layer ( 25) A method for manufacturing a thin film transistor matrix, characterized in that a gate electrode (36) is formed by patterning an n^+ conductivity type hydrogenated amorphous silicon film (23).