JPH01113336U - - Google Patents

Info

Publication number
JPH01113336U
JPH01113336U JP851088U JP851088U JPH01113336U JP H01113336 U JPH01113336 U JP H01113336U JP 851088 U JP851088 U JP 851088U JP 851088 U JP851088 U JP 851088U JP H01113336 U JPH01113336 U JP H01113336U
Authority
JP
Japan
Prior art keywords
chip
evaluation
connects
utility
scope
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP851088U
Other languages
English (en)
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP851088U priority Critical patent/JPH01113336U/ja
Publication of JPH01113336U publication Critical patent/JPH01113336U/ja
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0555Shape
    • H01L2224/05552Shape in top view
    • H01L2224/05554Shape in top view being square

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Wire Bonding (AREA)
JP851088U 1988-01-26 1988-01-26 Pending JPH01113336U (US20030157025A1-20030821-C00018.png)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP851088U JPH01113336U (US20030157025A1-20030821-C00018.png) 1988-01-26 1988-01-26

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP851088U JPH01113336U (US20030157025A1-20030821-C00018.png) 1988-01-26 1988-01-26

Publications (1)

Publication Number Publication Date
JPH01113336U true JPH01113336U (US20030157025A1-20030821-C00018.png) 1989-07-31

Family

ID=31214449

Family Applications (1)

Application Number Title Priority Date Filing Date
JP851088U Pending JPH01113336U (US20030157025A1-20030821-C00018.png) 1988-01-26 1988-01-26

Country Status (1)

Country Link
JP (1) JPH01113336U (US20030157025A1-20030821-C00018.png)

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