JPH01112177A - Test circuit - Google Patents

Abstract

PURPOSE:To improve controllability and observableness by inputting and outputting data in series and accessing registers in a digital circuit optionally. CONSTITUTION:Addresses of respective shift registers in a shift register group 1 are stored in a 3-bit shift register 2 from an input terminal in synchronism with a shift clock 3. A 3-bit decoder 4 enters an enables state through an enable terminal 5 has seven kinds of decoded values. When the decoder is disabled, the output of the decoder 4 controls the opening/closing states of seven switches 6 to close only switches corresponding to specified addresses, and data are inputted to the registers of the desired addresses from the input terminal in series in synchronism with the shift clock 7. An AND gate 8 supplies the shift clock to the respective registers in the form of the product of the output of the decoder 4 and shift clock 7.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a test circuit for facilitating the testing of digital circuits.

2. Description of the Related Art In a conventional test circuit, as shown in FIG.
In order to set a desired value in a register in a digital circuit (ensure controllability) or read the contents of a register (ensure observability), a shift register function is added to registers 51 to 67. Moreover, by connecting all the registers in the digital circuit in series, data can be written to and read from all the registers, thereby improving the tenutability of the digital circuit.

Problems to be Solved by the Invention In such a conventional test circuit, registers 61 to 67
Since the write or read data is shifted by connecting the registers in series, as the number of bits and the number of registers 51 to 57 increase, it takes a considerable amount of time to shift the data, resulting in a long tenuto time. Furthermore, if there is a defect in even one place in the chain of @ registers 51 to 67, there is a drawback that data cannot be written to subsequent registers or the contents of previous registers cannot be read.

In the present invention, the registers 61 to 57 are arbitrarily selected.
It is an object of the present invention to provide a test circuit capable of writing and reading selective data.

Means for Solving the Problems The technical means of the present invention for solving the above problems consists of a shift register into which register addresses are input in series, a decoder which decodes the addresses, and an output from the decoder which is deactivated when disabled. Set everything to O++
It consists of a glue circuit and a switch which connects the input (output) of the register to a single external input (output) terminal and whose opening/closing is controlled by the output of the decoder 〇.

According to the above-described structure, the present invention serially inputs the address of the register to be accessed for writing or reading, enables the decoder to decode the address, and uses the output of the decoder to access the desired register. By closing a switch connecting a single input or output terminal, it is possible to serially write (read) data in a register from a single input (output) terminal.

Embodiment FIG. 1 is a block diagram showing a first embodiment of the test circuit of the present invention. In FIG. 1, reference numeral 1 denotes a group of registers having a shift register function, and the address of each register is stored in a 3-bit shift register (address register) 2 from an input terminal in synchronization with a shift clock (5HCKA) 3. The 3-bit decoder 4 has an enable terminal 5.
becomes enabled by (001) to (111)
It has seven types of decode values. At the time of denuple, the output of the 3-bit decoder 4 becomes (000).

The output of the 3-bit decoder 4 is sent to seven switches 6.
The switch corresponding to the specified address is closed and the shift clock (5HCK) is output from the input terminal.
B) Data can be serially input to a register at a desired address in synchronization with 7. A shift clock is supplied to each register by an AND gate 8 in the form of the product of the output of the 3-bit decoder 4 and the shift clock.

FIG. 2 is a timing diagram of five henos for explaining the first embodiment of the present invention. In Figure 2, 3 in the period ■
An address (001) is set in the bit address register 2, and a value (01° ool) is written in the register specified by the address (in this case, 5 bits t) during the period (3). Next, the address (01o) is set in the period ■, and the value (11o1oo) is written in the 6-bit register in the period ■.

FIG. 3 shows a second embodiment of the present invention, in which the address of each register is stored in an address register 2 from an input terminal (SIN) 9 in synchronization with a shift clock 3. The 3-bit decoder 4 decodes the stored address, the switch 6 corresponding to the address is closed, and the contents of the desired register are read out to the output terminal in synchronization with the shift clock 7.

FIG. 4 is a timing diagram for explaining the second embodiment of the present invention. In FIG. 4, the address is set during the periods 2 and 2, and the contents of the register are read during the periods 2 and 3.

In the embodiment of the present invention, the same effect can be achieved even if the register group 1 has a plurality of register modules at the same address.

Effects of the Invention The present invention improves controllability and observability by making registers in a digital circuit arbitrarily accessible. Since data input (output) is performed in series, the number of external terminals required for testing is small, and data can be input and output to and from a desired register with a small number of clocks, reducing test time. Furthermore, even if a register at a certain address is defective, registers at other addresses can be read and written without any problem.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a test circuit in the first embodiment of the present invention, FIG. 2 is a timing diagram of the same embodiment, and FIG.
FIG. 4 is a block diagram showing a test circuit according to a second embodiment of the present invention, FIG. 4 is a timing diagram of the second embodiment, and FIG. 5 is a block diagram of a conventional test circuit. 1...Register group, 2...Address register, 4...3-bit decoder, 6...
···switch.

Claims (2)

[Claims] (1) A shift register of arbitrary bit length that allows serial data input, a decoder with an enable function that decodes the data stored in the shift register, a plurality of switches controlled by the output of the decoder, and the switch. A test circuit comprising a group of shift registers connected by groups to a single input terminal. (2) The test circuit according to claim 1, comprising a shift register group connected to a single output terminal by a switch group.