JPH01103096U - - Google Patents

Description

[Brief explanation of the drawing]

Figures 1 and 2 are EE according to the present invention, respectively.
A configuration diagram and a circuit diagram showing the main parts of an embodiment of PROM, FIG. 3 shows a MOS that constitutes a pseudo memory cell and an nMOS FET that constitutes a part of a current detection circuit.
A schematic plan view showing the main parts of the conventional EE.
FIG. 2 is a cross-sectional view showing a PROM memory cell. DESCRIPTION OF SYMBOLS 1... Memory cell, 2... MOS constituting the memory cell, 2F... Floating gate of MOS2, 11... Program/erase control circuit, 12... Pseudo memory cell, 13... Program/erase end detection circuit, 16
...MOS forming the pseudo memory cell, 16F...M
OS16 floating gate.

Claims (1)

[Claims for Utility Model Registration] In an electrically erasable and writable semiconductor nonvolatile memory comprising a memory cell made of an insulated gate field effect transistor having a floating gate, a write/erase method for controlling writing or erasing to the memory cell. a control means; a pseudo memory cell having the same structure as the memory cell and to which writing or erasing is performed simultaneously with the memory cell; and a controller for controlling the programming or erasing state of the pseudo memory cell to the end of writing or erasing in the memory cell; write/erase end detection means for detecting a write end detection signal or an erase end detection signal to the write/erase control means, wherein the write/erase control means receives the write end detection signal from the write/erase end detector Alternatively, an electrically erasable and writable semiconductor nonvolatile memory characterized in that when the erasure completion detection signal is supplied, writing or erasing to the memory cell is completed.