JP7585350B2 - ウエハ搬送用基板 - Google Patents

ウエハ搬送用基板 Download PDF

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Publication number
JP7585350B2
JP7585350B2 JP2022566741A JP2022566741A JP7585350B2 JP 7585350 B2 JP7585350 B2 JP 7585350B2 JP 2022566741 A JP2022566741 A JP 2022566741A JP 2022566741 A JP2022566741 A JP 2022566741A JP 7585350 B2 JP7585350 B2 JP 7585350B2
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JP
Japan
Prior art keywords
semiconductor wafer
transport substrate
wafer transport
wafer
probe contact
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2022566741A
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English (en)
Japanese (ja)
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JPWO2022118468A1 (https=
Inventor
詔子 辰己
允洋 名田
泰彦 中西
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NTT Inc
NTT Inc USA
Original Assignee
Nippon Telegraph and Telephone Corp
NTT Inc USA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp, NTT Inc USA filed Critical Nippon Telegraph and Telephone Corp
Publication of JPWO2022118468A1 publication Critical patent/JPWO2022118468A1/ja
Application granted granted Critical
Publication of JP7585350B2 publication Critical patent/JP7585350B2/ja
Active legal-status Critical Current
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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/30—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for conveying, e.g. between different workstations
    • H10P72/32—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for conveying, e.g. between different workstations between different workstations
    • H10P72/3218—Conveying cassettes, containers or carriers
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/26—Testing of individual semiconductor devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/06—Apparatus for monitoring, sorting, marking, testing or measuring
    • H10P72/0606—Position monitoring, e.g. misposition detection or presence detection
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/50—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for positioning, orientation or alignment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/50—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for positioning, orientation or alignment
    • H10P72/53—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for positioning, orientation or alignment using optical controlling means
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/78—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using vacuum or suction, e.g. Bernoulli chucks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P74/00—Testing or measuring during manufacture or treatment of wafers, substrates or devices

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
  • Testing Of Individual Semiconductor Devices (AREA)
JP2022566741A 2020-12-04 2020-12-04 ウエハ搬送用基板 Active JP7585350B2 (ja)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2020/045274 WO2022118468A1 (ja) 2020-12-04 2020-12-04 ウエハ搬送用基板

Publications (2)

Publication Number Publication Date
JPWO2022118468A1 JPWO2022118468A1 (https=) 2022-06-09
JP7585350B2 true JP7585350B2 (ja) 2024-11-18

Family

ID=81854079

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2022566741A Active JP7585350B2 (ja) 2020-12-04 2020-12-04 ウエハ搬送用基板

Country Status (3)

Country Link
US (1) US12543531B2 (https=)
JP (1) JP7585350B2 (https=)
WO (1) WO2022118468A1 (https=)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US12327770B2 (en) * 2021-11-29 2025-06-10 International Business Machines Corporation Probe pad with built-in interconnect structure

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001332490A (ja) 2000-03-14 2001-11-30 Nikon Corp 位置合わせ方法、露光方法、露光装置、及びデバイス製造方法
JP2003234392A (ja) 2001-12-03 2003-08-22 Nitto Denko Corp 半導体ウエハ搬送方法およびこれを用いた半導体ウエハ搬送装置
JP2009170730A (ja) 2008-01-17 2009-07-30 Fujifilm Corp 裏面照射型固体撮像素子の検査装置
JP2010062405A (ja) 2008-09-05 2010-03-18 Covalent Materials Corp 半導体ウエハ用真空ピンセット
JP2018013806A (ja) 2006-01-19 2018-01-25 株式会社ニコン 露光装置及び露光方法、並びにデバイス製造方法

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3949295A (en) * 1974-03-20 1976-04-06 Western Electric Company, Inc. Apparatus for retaining articles in an array for testing
JPS5911619A (ja) * 1982-07-12 1984-01-21 Nec Corp 半導体装置の非接触試験方法
US4861162A (en) 1985-05-16 1989-08-29 Canon Kabushiki Kaisha Alignment of an object
JPS61263123A (ja) * 1985-05-16 1986-11-21 Canon Inc ステップアンドリピート露光方法
JP3614003B2 (ja) 1998-11-11 2005-01-26 松下電器産業株式会社 プローブカードの位置決め機構
US6541989B1 (en) * 2000-09-29 2003-04-01 Motorola, Inc. Testing device for semiconductor components and a method of using the device
JP4740405B2 (ja) 2000-11-09 2011-08-03 東京エレクトロン株式会社 位置合わせ方法及びプログラム記録媒体
US7442476B2 (en) * 2004-12-27 2008-10-28 Asml Netherlands B.V. Method and system for 3D alignment in wafer scale integration
TWI478272B (zh) * 2007-08-15 2015-03-21 尼康股份有限公司 A positioning device, a bonding device, a laminated substrate manufacturing device, an exposure device, and a positioning method
US10213842B2 (en) * 2017-02-10 2019-02-26 Spy Eye, Llc Method for achieving length accuracy of diamond turned parts
US11009798B2 (en) * 2018-09-05 2021-05-18 Micron Technology, Inc. Wafer alignment markers, systems, and related methods

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001332490A (ja) 2000-03-14 2001-11-30 Nikon Corp 位置合わせ方法、露光方法、露光装置、及びデバイス製造方法
JP2003234392A (ja) 2001-12-03 2003-08-22 Nitto Denko Corp 半導体ウエハ搬送方法およびこれを用いた半導体ウエハ搬送装置
JP2018013806A (ja) 2006-01-19 2018-01-25 株式会社ニコン 露光装置及び露光方法、並びにデバイス製造方法
JP2009170730A (ja) 2008-01-17 2009-07-30 Fujifilm Corp 裏面照射型固体撮像素子の検査装置
JP2010062405A (ja) 2008-09-05 2010-03-18 Covalent Materials Corp 半導体ウエハ用真空ピンセット

Also Published As

Publication number Publication date
JPWO2022118468A1 (https=) 2022-06-09
WO2022118468A1 (ja) 2022-06-09
US20240096675A1 (en) 2024-03-21
US12543531B2 (en) 2026-02-03

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