JP7320427B2 - switching power supply - Google Patents

Description

The present invention relates to a switching power supply device as a DC/DC converter using a transformer and a photocoupler.

FIG. 18 shows a circuit of this type of conventional switching power supply (Patent Document 1). A transformer 60 includes a primary winding L11, a first auxiliary winding L12, a secondary winding L13, and a second auxiliary winding L14. MN11 is an NMOS switching transistor, and 70 is a photocoupler having a photodiode PD2 and a phototransistor PT2. R11 to R19 are resistors, Rs2 is a sense resistor for detecting the drain current of the switching transistor MN11, and C11 to C15 are capacitors.

In this switching power supply, when the voltage obtained by dividing the output voltage Vout by the resistors R18 and R19 is higher than the reference voltage Vref11 of the voltage source VB11, the output voltage of the operational amplifier OP11 decreases according to the difference voltage. When the output voltage of the operational amplifier OP11 is below a predetermined value, current flows through the photodiode PD2 of the photocoupler 70 according to the value of the output voltage, and the internal resistance of the phototransistor PT2 is determined according to the amount of light emitted there.

When the power supply voltage Vin is applied, the exciting current flowing through the first auxiliary winding L12 through the resistors R11 and R13 charges the capacitor C13 so that the resistor R13 side becomes positive. When the voltage at the common connection point of the capacitor C13 and the resistor R13 reaches the threshold voltage of the switching transistor MN11, the switching transistor MN11 is turned on.

As a result, when a current begins to flow through the primary winding L11 to which the switching transistor MN11 is connected by the DC voltage Vin, induced electromotive forces are generated in the windings L12, L13, and L14 of the transformer 60, and energy is accumulated in the transformer 60. be done. The induced voltage (positive on the black circle side) generated in the first auxiliary winding L12 is superimposed on the voltage of the capacitor C13, so that the gate voltage of the switching transistor MN11 is maintained at its threshold voltage or higher, and the ON state is continued.

At this time, the drain current of the switching transistor MN11 flows through the sense resistor Rs2, and the sense voltage generated there charges the capacitor C12 via the resistor R15. Since the excitation current flowing through the primary winding L11 increases almost linearly with time after the switching transistor MN11 is turned ON, the voltage of the capacitor C12 also increases accordingly.

After that, when the voltage of the capacitor C12 reaches the threshold voltage of the transistor Q11, the transistor Q11 is turned on, and the switching transistor MN11 is turned off when the gate voltage drops below the threshold voltage.

When the current flowing through the primary winding L11 is interrupted by turning off the switching transistor MN11, a flyback voltage is generated in each of the windings L11 to L14. At this time, the flyback voltage generated in the secondary winding L13 is rectified and smoothed by the diode D11 and the capacitor C14 and output as the output voltage Vout.

On the other hand, the flyback voltage generated in the first auxiliary winding L12 is proportional to the flyback voltage generated in the secondary winding L13. ), the capacitor C13 is charged via the resistors R12 and R13 so that the resistor R13 side becomes positive, and the run-up for turning on the switching transistor MN11 proceeds.

After the switching transistor MN11 is turned off, the current in the primary winding L11 is cut off, so the voltage generated across the sense resistor Rs2 is zero, and the output voltage Vout is low, so the phototransistor PT2 is in operation. Therefore, the voltage on capacitor C12 continues to be discharged through resistors R15 and Rs2 and drops. As a result, when the voltage of the capacitor C12 becomes equal to or lower than the threshold voltage of the transistor Q11, the transistor Q11 is turned off.

By the way, since the base-collector portion of the transistor Q11 acts as an equivalent diode, the capacitor C13 consists of the sense resistor Rs2, the resistor R15, the base of the transistor Q11 to the collector, the resistor The current flowing through R13 also charges the resistor R13 so that the side of the resistor R13 becomes positive.

After the discharge of the electrical energy stored in the secondary winding L13 by flyback is completed, the voltage of the primary winding L11 changes from the parasitic capacitance of the switching transistor MN11, the stray capacitance in the primary winding L11, and the primary winding L11. Due to the inductance of the winding L11, it starts to oscillate freely around the input voltage Vin, and its polarity is reversed along with the voltage drop.

The voltage on the capacitor C13 side of the first auxiliary winding L12, which oscillates in proportion to the free oscillation of the voltage of the primary winding L11, also changes in the same manner. It acts as a forward voltage on the gate of the transistor MN11. Also, since the voltage of the capacitor C13 that has been charged so far is added to this voltage, when the total voltage exceeds the threshold voltage of the switching transistor MN11, the switching transistor MN11 is turned ON again. In this manner, a series of self-excited oscillation operations are repeated.

Until now, the output voltage Vout has been low and the photocoupler 70 has not operated. Therefore, the phototransistor PT2 does not affect the gate voltage of the switching transistor MN11, and the switching transistor MN11 is turned on during the maximum ON period determined by the resistance value of the sense resistor Rs2. Operate. After that, the output voltage Vout rises each time oscillation repeats, and when it exceeds the set voltage corresponding to the reference voltage Vref11, the comparison operation by the operational amplifier OP11 is started, and the photocoupler 70 is shifted to normal operation.

In this normal operation, when the output voltage Vout is higher than the set voltage, the voltage of the capacitor C12 is charged by the current flowing through the phototransistor PT2 of the photocoupler 70 in addition to the voltage generated in the sense resistor Rs2. Therefore, the higher the output voltage Vout, the earlier the turn-on timing of the transistor Q11, and the earlier the turn-off timing of the switching transistor MN11. That is, the ON period of the switching transistor MN11 is shortened.

When the switching transistor MN11 turns off, the switching transistor MN11 continues to turn off until the voltage on the resistor R13 side of the capacitor C13 charged by the flyback voltage of the first auxiliary winding L12 reaches the threshold voltage of the switching transistor MN11.

In this switching power supply device, when the voltage obtained by dividing the input voltage Vin by the resistors R11 and R12 is less than a predetermined value, the bias voltage of the switching transistor MN11 becomes low and the switching transistor MN11 does not turn ON/OFF.

JP 2005-027412 A

However, the switching power supply device of FIG. 18 specifically requires the second auxiliary winding L14 in order to obtain the photocoupler current.

Also, since the voltage on the resistor R13 side of the capacitor C13 controls the gate of the switching transistor MN11, there is a problem that the ON timing of the switching transistor MN11 is affected by variations in the threshold value of the switching transistor MN11. Also, since the switching transistor MN11 is turned off when the charging voltage of the capacitor C12 reaches the threshold of the transistor Q11, there is a problem that the timing of turning off the switching transistor MN11 is affected by variations in the threshold of the transistor Q11.

Furthermore, when the load current increases, there is only means for suppressing the drain peak current of the switching transistor MN11 by the operation of the resistor Rs2 and the transistor Q11, and the current limiting function is insufficient. There is a risk that the power supply will malfunction or be damaged due to factors such as overheating. There is also no means to set the current limit behavior to protect against power supply failure during output short circuits.

An object of the present invention is to eliminate the need for a second auxiliary winding for obtaining a photocoupler current, to prevent the ON/OFF of the switching transistor from being affected by variations in the threshold value of the switching transistor, and to provide a high load current when the load current increases. An object of the present invention is to provide a switching power supply device having a current limiting function capable of arbitrarily setting operating characteristics.

In order to achieve the above object, a switching power supply device according to claim 1 of the present invention comprises a switching transistor that is ON/OFF controlled, a sense resistor that generates a sense voltage when the switching transistor is turned ON, and the switching transistor. A transformer having a primary winding to which an input voltage is applied by turning ON, a secondary winding to supply an output voltage to a load, and an auxiliary winding to detect the output voltage; a current limiting feedback circuit for generating first, second and third feedback currents inversely proportional to said output voltage according to the voltage of said auxiliary winding; said sense voltage; 1 photocoupler current, an ON period control circuit that takes in the first feedback current and generates an OFF timing signal for the switching transistor, and a constant current or a differential current between the constant current and the third feedback current, and an OFF period control circuit that takes in the voltage of a fourth capacitor discharged when turned ON, the second feedback current, and the second photocoupler current to generate an ON timing signal for the switching transistor, wherein the current limiting feedback circuit generates said first, second and third feedback currents when said output voltage is less than or equal to a second output voltage which is lower than said first output voltage; and when said output voltage exceeds said first output voltage. causes the ON period control circuit to receive the sense voltage and the first photocoupler current, and causes the OFF period control circuit to receive the voltage of the fourth capacitor charged with the constant current and the second photocoupler current, When the output voltage becomes lower than the second output voltage, the ON period control circuit takes in the sense voltage and the first feedback current, and the OFF period control circuit receives the constant current and the third feedback current. It is characterized in that the voltage of a fourth capacitor charged with the differential current of the feedback current and the second feedback current are incorporated.

The invention according to claim 2 is the switching power supply device according to claim 1, wherein the current limiting feedback circuit is controlled to be enabled when the output voltage becomes lower than the second output voltage. Characterized by

The invention according to claim 3 is the switching power supply device according to claim 1 or 2, wherein the first, second and third feedback currents of the current limiting feedback circuit are independent of each other, and the first and third feedback currents of the photocoupler are independent of each other. The second photocoupler currents are characterized by being independent of each other.

The invention according to claim 4 is the switching power supply device according to any one of claims 1 to 3, further comprising a first resistor connected between the auxiliary winding and the current limiting feedback circuit, The 1st, 2nd and 3rd feedback currents are the inverse of the voltage generated in the auxiliary winding that is inversely proportional to the current flowing in the first resistor due to the voltage generated in the auxiliary winding during the OFF period of the switching transistor. It is characterized by being a current held at timing.

The invention according to claim 5 is the switching power supply device according to any one of claims 1 to 4, wherein the ON period control circuit controls the OFF timing signal of the switching transistor as the first photocoupler current increases. , the larger the first feedback current and the larger the sense voltage, the earlier the timing is generated. The larger the second feedback current and the larger the third feedback current, the later the timing is generated.

The invention according to claim 6 is the switching power supply device according to any one of claims 1 to 5, wherein the ON period control circuit controls the first photocoupler current or the When a second resistor inserted in the path through which the first feedback current flows and a second voltage generated on the introduction side of the first photocoupler current or the first feedback current of the second resistor become the same voltage as the sense voltage and a first comparator that generates the OFF timing signal.

The invention according to claim 7 is the switching power supply device according to any one of claims 1 to 5, wherein the OFF period control circuit converts the voltage of the fourth capacitor to the second photocoupler current or the second feedback current. a third resistor inserted so as to cause a voltage drop due to current; 2 comparators.

The invention according to claim 8 is the switching power supply device according to claim 5 or 7, wherein the ON timing signal of the OFF period control circuit is retimed at the inversion timing of the voltage generated in the auxiliary winding. Characterized by

The invention according to claim 9 is the switching power supply device according to claim 1, wherein the current limiting feedback circuit turns off the switching transistor when the output voltage becomes equal to or lower than a second output voltage which is lower than the first output voltage. A signal inversely proportional to the output voltage is sampled at a point in time when the switching transistor is controlled to turn off the first and second A current hold circuit for holding the second and third feedback currents is provided.

According to a tenth aspect of the present invention, in the switching power supply device of the ninth aspect, the current hold circuit operates when the output voltage becomes equal to or lower than a predetermined voltage lower than the second output voltage. and third feedback currents are released, and the first, second and third feedback currents are output in inverse proportion to the output voltage.

According to the present invention, since the first and second photocoupler currents are used as sink currents, no auxiliary winding is required as a power source for the phototransistor, and only one auxiliary winding is required. In addition, since ON/OFF of the switching transistor is controlled by the ON timing signal and the OFF timing signal, the ON/OFF timing of the switching transistor is not affected by variations in the threshold value of the switching transistor. When the output voltage drops below the second output voltage, the first to third feedback currents are used to control ON and OFF of the switching transistor. protection can be achieved. Further, the current limiting feedback circuit separately generates a first feedback current taken into the ON period control circuit and a second feedback current taken into the OFF period control circuit, and also generates a third feedback current for discharging the fourth capacitor from the first feedback current. and the second feedback current, the current limiting characteristics can be changed. By adjusting the current flowing through the auxiliary winding and the value of the fourth capacitor, it is possible to realize arbitrary current limiting characteristics such as a fold-back type, a vertical type, and a drooping type.

1 is a block diagram of a switching power supply device according to one embodiment of the present invention; FIG. 2 is a circuit diagram of an ON period control circuit of the switching power supply device of FIG. 1; FIG. 2 is a circuit diagram of an OFF period control circuit of the switching power supply device of FIG. 1; FIG. 2 is a circuit diagram of a current limiting feedback circuit of the switching power supply device of FIG. 1; FIG. 5 is a circuit diagram of a current hold circuit of the current limit feedback circuit of FIG. 4; FIG. 2 is a circuit diagram of an Ipc distribution circuit of the switching power supply device of FIG. 1; FIG. (a) to (c) are characteristic diagrams of the current limiting operation of the switching power supply device of FIG. 2 is a timing chart of transition from current limiting operation 1 to current limiting operation 2 of the switching power supply device of FIG. 1; 2 is a timing chart of transition from current limiting operation 2 to current limiting operation 3 of the switching power supply device of FIG. 1; 2 is a circuit diagram of a current limiting feedback circuit of a first modified example of the switching power supply device of FIG. 1; FIG. 11 is a circuit diagram of a current hold circuit of the current limit feedback circuit of FIG. 10; FIG. FIG. 11 is a characteristic diagram of current limiting operation when the current limiting feedback circuit of FIG. 10 is used; 11 is a timing chart of transition from current limiting operation 1 to current limiting operation 2 when the current limiting feedback circuit of FIG. 10 is used; 2 is a circuit diagram of a current limiting feedback circuit of a second modification of the switching power supply device of FIG. 1; FIG. 3 is a circuit diagram of a current limiting feedback circuit of a third modification of the switching power supply device of FIG. 1; FIG. 16 is a circuit diagram of a current hold circuit of the current limit feedback circuit of FIG. 15; FIG. FIG. 11 is a circuit diagram of a current limiting feedback circuit of a fourth modification of the switching power supply device of FIG. 1; 1 is a circuit diagram of a conventional switching power supply; FIG.

FIG. 1 shows the configuration of a switching power supply device according to an embodiment of the present invention. A transformer 10 has a primary winding L1, a secondary winding L2, and an auxiliary winding L3. An input DC voltage Vin stabilized by a capacitor C1 is input to the primary winding L1, and the excitation energy generated by the ON/OFF operation of the NMOS switching transistor MN1 is applied to the secondary winding L2 and the auxiliary winding L3. inform. A rectifying/smoothing circuit including a diode D1 and a capacitor C2 is connected to the secondary winding L2, and the output DC voltage Vout is taken out from the rectifying/smoothing circuit. A rectifying/smoothing circuit including a diode D2 and a capacitor C3 is connected to the auxiliary winding L3, and the power supply voltage VDD is generated from the rectifying/smoothing circuit.

A control circuit 20 controls ON/OFF of the switching transistor MN1. In the control circuit 20, an ON period control circuit 21 controls the time during which the switching transistor MN1 continues to be ON and outputs an OFF timing voltage Voff, and 22 controls the time during which the switching transistor MN1 continues to be OFF. is an OFF period control circuit for outputting an ON timing voltage Von. The OFF period control circuit 22 has an external capacitor C4.

Reference numeral 23 denotes an SRFF circuit, which is reset when the OFF timing voltage Voff output from the ON period control circuit 21 becomes "H" to set the driving voltage Vdrv output from the Q terminal to "L". Also, it is set when the ON timing voltage Von output from the OFF period control circuit 22 becomes "H", and the drive voltage Vdrv output from the Q terminal is set to "H".

A drive circuit 24 receives the drive voltage Vdrv output from the Q terminal of the SRFF circuit 23 and generates a gate voltage Vg for ON/OFF-controlling the switching transistor MN1. is set to "H" to turn on the switching transistor MN1, and when the driving voltage Vdrv is "L", the gate voltage Vg is set to "L" to turn off the switching transistor MN1.

A charging circuit 25 supplies a constant charging current Ioff to the external capacitor C4.

Reference numeral 26 denotes an inversion detection circuit, which takes in the pulsating current voltage Vrise generated in the auxiliary winding L3 via a resistor R1 and generates a waveform-shaped pulse signal voltage Vp indicating the inversion (zero crossing) timing of the pulsating current voltage Vrise. , is output to the OFF period control circuit 22 for retiming.

Reference numeral 27 denotes a current limiting feedback circuit for detecting a drop in the output voltage Vout, and feedback currents Ifb1 and Ifb2 that are inversely proportional to the negative voltage component of the pulsating current voltage Vrise generated in the auxiliary winding L3 when the current Ia flows. , Ifb3. These three feedback currents Ifb1 to Ifb3 are currents that exhibit larger values as the output voltage Vout is lower than a predetermined voltage. Feedback current Ifb1 draws current from ON period control circuit 21, feedback current Ifb2 draws current from OFF period control circuit 22, and feedback current Ifb3 draws current discharged from capacitor C4.

Reference numeral 28 denotes an Ipc distribution circuit for distributing a photocoupler current Ipc flowing through a phototransistor PT1 of a photocoupler 40, which will be described later. Ipc distribution circuit 28 sinks current Ipc1 from ON period control circuit 21 and current Ipc2 from OFF period control circuit 22 .

An internal power supply circuit 29 receives the voltage VDD obtained by rectifying and smoothing the pulsating voltage Vrise through a rectifying/smoothing circuit composed of a diode D2 and a capacitor C3 to generate a stabilized internal power supply voltage Vreg.

Reference numeral 30 denotes an output voltage feedback circuit for detecting the output voltage Vout, which is similar to the circuit including the operational amplifier OP11, voltage source VB11, capacitor C15, resistors R16, R17, R18 and R19 described in FIG. When the output voltage Vout exceeds the target value, the output voltage feedback circuit 30 increases the current flowing through the photodiode PD1 of the photocoupler 40 as the output voltage Vout increases.

The photocoupler 40 is composed of a photodiode PD1 and a phototransistor PT1. The phototransistor PT1 generates a photocoupler current Ipc proportional to the amount of light emitted from the photodiode PD1, that is, the value of the output voltage Vout.

FIG. 2 shows a specific circuit diagram of the ON period control circuit 21. As shown in FIG. The ON-period control circuit 21 includes a voltage source VB1 of a reference voltage Vref1, a buffer BF1 for impedance conversion, a resistor R2, and a resistor R2. , a buffer BF2 that converts the impedance of the sense voltage Vs1 generated across the sense resistor Rs1 by the current flowing through the switching transistor MN1, a voltage Vr2 dropped across the resistor R2 due to the flow of the photocoupler current Ipc1 or the feedback current Ifb1, and the sense voltage Vr2. and a comparator CP1 for comparing the voltage Vs1.

When the switching transistor MN1 is OFF, the switch SW1 is OFF, so the voltage Vr2 of the inverting input terminal of the comparator CP1 is Vref1, and the OFF timing voltage Voff, which is the output of the comparator CP1, is "L". ing. However, when the switch SW1 is turned on, the photocoupler current Ipc1 or the feedback current Ifb1 flows through the resistor R2, so the voltage Vr2 of the inverting input terminal of the comparator CP1 drops to "Vref1−R2×(Ipc1 or Ifb1)". Then, when the sense voltage Vs1 becomes higher than the voltage Vr2, the OFF timing voltage Voff output from the comparator CP1 changes from "L" to "H".

In this manner, the ON period control circuit 21 adjusts the timing of changing the OFF timing voltage Voff from "L" to "H" as the photocoupler current Ipc1 increases, the feedback current Ifb1 increases, and the sense voltage Vs1 increases. Then, the ON time of the switching transistor MN1 is controlled to be shortened.

FIG. 3 shows a specific circuit diagram of the OFF period control circuit 22. As shown in FIG. The OFF period control circuit 22 includes a switch SW2 that is turned ON when the drive voltage Vdrv is "H", a buffer BF3 for impedance conversion, a resistor R3, and a comparator whose inverting input terminal is set to the reference voltage Vref2 of the voltage source VB2. CP2, and a latchable logic circuit 221 such as a DFF circuit for retiming the output voltage of the comparator CP2 with the output pulse signal voltage Vp of the inversion detection circuit 26 to generate the ON timing voltage Von. Note that this logic circuit 221 can be omitted. The external capacitor C4 is charged with the differential current between the constant current Ioff of the charging circuit 25 and the feedback current Ifb3 when the switch SW2 is OFF.

In the OFF period control circuit 22, when the drive voltage Vdrv becomes "L", the switch SW2 is turned OFF, and the capacitor C4 is charged by the differential current between the constant current Ioff and the feedback current Ifb3, resulting in the voltage Vc4. A photocoupler current Ipc2 or a feedback current Ifb2 flows through the resistor R3. Therefore, the voltage Vr3 at the common connection point between the resistor R3 and the non-inverting input terminal of the comparator CP2 decreases as the photocoupler current Ipc2 or the feedback current Ifb2 increases, and increases as the differential current between the constant current Ioff and the feedback current Ifb3 increases. . When the voltage Vr3 exceeds the reference voltage Vref2, the output voltage Vcp2 of the comparator CP2 changes from "L" to "H". The output voltage Vcp2 of the comparator CP2 is retimed in the logic circuit 221 at the rise of the pulse signal voltage Vp output from the inversion detection circuit 26, and the ON timing voltage Von becomes "H". After retiming, when the voltage Vdrv becomes "H", the ON-timing voltage Von returns to the state "L" before retiming.

In this way, the ON-timing voltage Von (=“H”) is generated when the photocoupler current Ipc2 is larger, the feedback current Ifb2 is larger, and the differential current between the constant current Ioff and the feedback current Ifb3 is smaller (feedback current The larger Ifb3), the longer the OFF period of the switching transistor MN1.

FIG. 4 shows a specific circuit diagram of the inversion detection circuit 26 and the current limiting feedback circuit 27. As shown in FIG. The inversion detection circuit 26 includes a comparator CP3 whose inverting input terminal is set to a reference voltage Vref3 by a voltage source VB3, a diode-connected NPN transistor Q1 whose collector is connected to an auxiliary winding L3 via a resistor R1, an auxiliary It has a transistor Q2 whose emitter is connected to the winding L3 via a resistor R1, and a voltage source VB4 that applies a reference voltage Vref4 to the base of the transistor Q2.

The transistor Q1 constitutes a maximum voltage regulation circuit, and when a voltage Vrise is generated in the auxiliary winding L3 in which the ● side is positive, that is, when the switching transistor MN1 is ON, the maximum voltage at the non-inverting input terminal of the comparator CP3 is to Vbe(Q1). Vbe(Q1) is the base-emitter voltage of transistor Q1. A resistor may be connected instead of the transistor Q1, and the voltage obtained by dividing the voltage Vrise by the resistor and the resistor R1 may be input to the non-inverting input terminal of the comparator CP3 as the maximum voltage. The transistor Q2 constitutes a minimum voltage regulation circuit, and when a voltage Vrise (=VL3) is generated in the auxiliary winding L3, the negative side of which is on the ● side, that is, when the switching transistor MN1 is OFF, the non-inverting input of the comparator CP3. The minimum voltage of the terminal is limited to "Vref4-Vbe(Q2)". Vbe(Q2) is the base-emitter voltage of transistor Q2. The comparator CP3 outputs a signal of "H" if the voltage of the non-inverting input terminal exceeds the reference voltage Vref3, and a signal of "L" if it is less than the reference voltage Vref3, as the pulse signal voltage Vp.

The inversion detection circuit 26 retiming the output voltage Vcp2 of the comparator CP2 of the OFF period control circuit 22 with the pulse signal voltage Vp whose waveform is shaped at the timing of reversing the pulsating voltage Vrise of the auxiliary winding L3 from the negative electrode to the positive electrode. Since the switching transistor MN1 can be turned on at the bottom of the free oscillation of the drain voltage to perform a quasi-resonant operation, the influence of variations in the threshold value of the switching transistor MN1 during the quasi-resonant operation can be eliminated.

The current limiting feedback circuit 27 converts the current Ia flowing through the auxiliary winding L3 when the ● side of the auxiliary winding L3 is negative, that is, when the switching transistor MN1 is off, into a current Ib multiplied by m and outputs the current Ib. A first current mirror circuit 271, a current source 273 of a constant current Ic, a second current mirror circuit 272 that inputs a current Id (=Ic−Ib), converts it into a current Ie multiplied by n, and outputs the current Equipped with a current hold circuit 274 that inputs Ie and absorbs three feedback currents Ifb1, Ifb2, and Ifb3 that are proportional to the current Ie, and a timing generation circuit 275 that provides the current hold circuit 274 with a hold (sample) timing voltage Vsp. . The timing generation circuit 275 makes the voltage Vsp "H" for a predetermined time after the ● side of the auxiliary winding L3 becomes negative. The current hold circuit 274 samples the current Ie when the voltage Vsp changes from "H" to "L" and stores the corresponding voltage in the capacitor C5. The feedback currents Ifb1 to Ifb3 corresponding to the voltage held by the capacitor C5 are output during the period Th until the time when it becomes "H" (when the ● side of the auxiliary winding L3 becomes negative).

FIG. 5 shows a specific circuit configuration of the current hold circuit 274. As shown in FIG. The current hold circuit 274 is configured by NMOS transistors MN2, MN3, MN4, and MN5 to form a current mirror that inputs the current Ie and outputs three feedback currents Ifb1, Ifb2, and Ifb3, and a switch SW3 for sampling. A capacitor C5 is inserted between the gate of transistor MN2 and the gates of transistors MN3-MN5. When the voltage Vsp is in the "H" state, the switch SW3 is turned ON to output feedback currents Ifb1 to Ifb3 proportional to the current Ie, and when the voltage Vsp changes from "H" to "L", the switch SW3 is turned ON. to OFF, and a hold operation is performed. In this way, since the gate voltage of the transistor MN2 corresponding to the current Ie is held by the capacitor C5, the feedback currents Ifb1 to Ifb3 are directly proportional to the current Ie immediately before the switch SW3 is switched from ON to OFF. keep doing

The current Ic of the current source 273 has a current value of Ib=Ic when the output voltage Vout drops to a voltage Vout2 (Vout2a, Vout2b, Vout2c to be described later), and a current value of Ib>Ic when the voltage is higher than the voltage Vout2. is set to be As described above, the current Id does not flow in the range of the current value Ib≧Ic, and none of the feedback currents Ifb1 to Ifb3 flow at this time. Current Ic of current source 273 is set so that feedback currents Ifb1-Ifb3 flow only when output voltage Vout does not exceed Vout2. That is, the current source 273 constitutes a detection circuit for the output voltage Vout.

FIG. 6 shows a specific circuit diagram of the Ipc distribution circuit 28. As shown in FIG. The Ipc distribution circuit 28 is composed of current-mirror-connected PMOS transistors MP1 and MP2 to which the photocoupler current Ipc is input, and current-mirror-connected NMOS transistors MN6, MN7, and MN8 to which the drain current of the transistor MP2 is input. Transistor MN7 sinks photocoupler current Ipc1, and transistor MN8 sinks photocoupler current Ipc2.

<Normal operation>
In normal operation, the switching power supply is under constant voltage control so that the output voltage Vout becomes the target voltage Vout1, as shown in FIG. 7(a). During this constant voltage control, the absolute value of the negative voltage of the voltage Vrise generated in the auxiliary winding L3 is large, and the output current Iout is smaller than the maximum output current Ioutmax. During this constant voltage operation, when the ● side of the auxiliary winding L3 becomes the negative pole, the current Ia input to the current limiting feedback circuit 27 increases, so that the current value becomes Ib>Ic. Therefore, the currents Id and Ie become zero, and the feedback currents Ifb1 to Ifb3 also become zero. Therefore, in this normal operation, the ON period obtained by the ON period control circuit 21 and the OFF period obtained by the OFF period control circuit 22 are controlled exclusively by the photocoupler currents Ipc1 and Ipc2.

That is, when the output voltage Vout is higher than the target value Vout1, the photocoupler current Ipc1 increases and the voltage Vr2 of the ON period control circuit 21 is controlled to be low. Therefore, the OFF timing voltage Voff output from the comparator CP1 becomes "H" at an early timing, shortening the ON period. Further, the photocoupler current Ipc2 also increases, the voltage Vr3 of the OFF period control circuit 22 is controlled to be low, the ON timing voltage Von output from the comparator CP2 becomes "H" at a later timing, and the OFF period becomes longer. For these reasons, the output voltage Vout is controlled to be low.

When the output voltage Vout is lower than the target value Vout1, the operation is reversed. That is, the ON period control circuit 21 outputs the OFF timing voltage Voff at a late timing, and the OFF control circuit 22 outputs the ON timing voltage Von at an early timing, so that the output voltage Vout is controlled to be high.

<Current limit operation 1>
This current limiting operation 1 is the period of the current limiting operation 1 in the timing chart of FIG. When the output current Iout increases and reaches the maximum value Ioutmax in FIG. 7(a), the output voltage Vout begins to decrease, and when the photodiode PD1 of the photocoupler 40 stops emitting light, the photocoupler current Ipc stops flowing. Although the output voltage Vout at this time is lower than the voltage Vout1, the current Ia of the auxiliary winding L3 when the switching transistor MN1 is off is large, so the current value of the current limiting feedback circuit 27 becomes Ib>Ic. . Therefore, the currents Id and Ie do not flow, and the feedback currents Ifb1 to Ifb3 do not flow either.

At this time, in the ON period control circuit 21, since the photocoupler current Ipc1 and the first feedback current Ifb1 are zero, no voltage drop occurs across the resistor R2, the voltage Vr2=Vref1, and the time until the voltage Vr2 becomes equal to the sense voltage Vs1. is maximum, and the ON period is maximum.

Further, in the OFF period control circuit 22, the photocoupler current Ipc2 and the second feedback current Ifb2 are zero, so that the voltage Vr3 becomes equal to the charging voltage Vc4 of the capacitor C4 (Vr3=Vc4). It is compared with Vref2.

Therefore, the OFF period is determined by the charging time of the capacitor C4 with the constant current Ioff and the retiming in the logic circuit 221 . At this time, the ON period is maximized, and the input energy during the ON period is limited to a constant value, so the output power is also limited, and the increase in the output current Iout is suppressed to limit the current. , the output voltage Vout drops from the target voltage Vout1.

When the output voltage Vout further decreases, the conduction time of the diode D1 on the secondary side becomes longer, the ON duty decreases, the OFF time becomes longer, and the charging voltage Vc4 of the capacitor C4 charged with the constant current Ioff. However, since the time from when the switch SW2 is turned off until it reaches the voltage Vref2 is constant regardless of the output voltage Vout, the switching transistor MN1 is turned on only by retiming in the logic circuit 221. FIG.

When the charging time of the capacitor C4 (the value of the capacitor C4 and the value of the current Ioff) is set so that the critical mode operation is started when the current limiting operation is started, as the output voltage Vout decreases, Since the conduction time of the secondary diode D1 is longer than the constant charging time of the capacitor C4, the logic circuit 221 is retimed at the end of the conduction of the secondary diode D1 to turn on the switching transistor MN1. This results in current limiting in critical mode operation.

<Current limit operation 2>
This current limiting operation is the period of current limiting operation 2 in the timing charts of FIGS. When the output voltage Vout drops to the voltage Vout2a as shown in FIG. 7A, the switching transistor MN1 is turned off and the voltage VL3 becomes smaller when the - side of the auxiliary winding L3 becomes negative. The current Ia flowing through the current limiting feedback circuit 27 becomes smaller, and the currents Ib and Ic of the current limiting feedback circuit 27 become Ib=Ic. Further, when the output voltage Vout becomes lower than the voltage Vout2a, Ib<Ic, so that the feedback currents Ifb1 to Ifb3 flowing into the current hold circuit 274 are generated as currents inversely proportional to the current Ia.

As a result, the feedback current Ifb1 flows through the ON period control circuit 21 instead of the photocoupler current Ipc1, and the feedback current Ifb2 flows through the OFF period control circuit 22 instead of the photocoupler current Ipc2. The charging current of the capacitor C4 of the OFF period control circuit 22 is "Ioff-Ifb3".

At this time, in the ON period control circuit 21, the voltage Vr2 is generated by the first feedback current Ifb1 flowing through the resistor R2. Since the voltage becomes low, the timing at which the OFF timing voltage Voff output from the comparator OP1 becomes "H" is advanced, and the ON period is shortened. As a result, the input energy during the ON period is reduced and the output power is also reduced.

In the OFF period control circuit 22, since the second feedback current Ifb2 increases, the time required for the voltage Vr3 of the resistor R3 to rise to the voltage Vref2 increases, and the charging current of the capacitor C4 decreases. The time required for the output to be inverted from "L" to "H" is delayed.

In the current limiting operation 2, the conduction period of the secondary diode D1 is longer than the time until the output of the comparator CP2 is inverted. It becomes a critical mode operation in which the switching transistor MN1 is turned on by retiming. This is a current limiting operation that reduces the output power by shortening the ON period, and has the characteristic that the output current Iout decreases more than the current limiting operation 1 as the output voltage Vout decreases.

On the other hand, if the current limiting operation 1 is an operation in which the output transistor MN1 is turned on at the timing of free oscillation instead of the critical mode operation determining the charging time of the capacitor C4, the output voltage becomes lower than the voltage Vout2a. , to current limiting operation 3, which will be described next.

<Current limit operation 3>
This current limiting operation is the period of the current limiting operation 3 in the timing chart of FIG. When the output voltage Vout drops due to the current limiting operation and the current Ib of the current limiting feedback circuit 27 becomes even smaller than the current Ic, the current Ie increases, the feedback currents Ifb1 to Ifb3 increase, and the output of the comparator CP2 is inverted. Immediately after that, the logic circuit 221 is retimed when the conduction of the diode D1 on the secondary side ends, and the switching transistor MN1 turns on, and the output voltage Vout drops to the output voltage Vout3 in FIG. 7(a). Further, when the output voltage Vout becomes lower than the output voltage Vout3, the charging current (Ioff-Ifb3) of the capacitor C4 decreases due to the increase of the feedback current Ifb3, and the charging time becomes longer. Inversely, the switching transistor MN1 is turned on at the zero cross timing of the free oscillation. As in current limiting operation 2, the ON period is shortened by an increase in the first feedback current Ifb1, and the OFF period is lengthened by the second feedback current Ifb2 and the charging time of the capacitor C4, thereby increasing the ON duty. As a result, the output current Iout decreases.

When the output voltage Vout approaches 0 V, the value of the resistor R1 is large, and the current value of the current limiting feedback circuit 27 has a relationship of Ib<<Ic, the current Id becomes Id≈Ic, and the feedback currents Ifb1 to Ifb3 are It becomes the maximum, the ON time is the minimum, and the OFF time is the maximum. When the output voltage Vout further decreases in this state, the ON time is constant at a minimum and the input energy is constant at a minimum, so the output current Iout gradually increases. This characteristic is the characteristic below the output voltage Vout4 in FIG. 7(a).

The above is the basic current limiting operation of the present invention. The values of the output voltages Vout2a, Vout3, and Vout4 of the current limiting characteristics in FIG. Adjustable. Also, if the output voltage Vout2 at which the current value of the current limiting feedback circuit 27 becomes Ib=Ic is lowered, that is, if the output voltage to be detected is set to a low value like Vout2b, then the letter V shown in FIG. current limit characteristics. Conversely, if the output voltage Vout2 at which the current value becomes Ib=Ic is increased, that is, if the output voltage to be detected is set to a value higher than Vout2c, a drooping characteristic as shown in FIG. 7C is obtained. The characteristic of FIG. 7(b) can be realized by reducing the value of the resistor R1 and increasing the value of the capacitor C4 compared to the characteristic of FIG. 7(a). This can be achieved by increasing the value of R1 and decreasing the value of capacitor C4. Thus, by changing the proportional relationship of the feedback currents Ifb1 to Ifb3 and the values of the resistor R1 and the capacitor C4, it is possible to change the output voltage Vout2 at which the feedback currents Ifb1 to Ifb3 flow, thereby realizing a desired current limiting characteristic. can be done.

<First modification (27A) of current limiting feedback circuit 27>
FIG. 10 shows a current limiting feedback circuit 27A of a first modified example which includes means for detecting the output voltage Vout and enabling control of the current hold circuit 274A. In the current limiting feedback circuit 27A of FIG. 10, the first current mirror circuit 271A draws out a current If proportional to the current Ia, and the current If is converted to a voltage Vr4 by a resistor R4 to obtain the reference voltage Vref5 of the voltage source VB5 and the comparator CP4. to generate an enable signal Ven. Thus, even if the current value is Ib<Ic, the current hold circuit 274A is enabled by the enable signal Ven only when it detects that the output voltage Vout is lower than the voltage Vout2d shown in FIG. This makes it possible to stabilize the generation start timing of the feedback currents Ifb1, Ifb2, and Ifb3, that is, the switching timing from the current limiting operation 1 to the current limiting operation 2. FIG.

In the state of the current limiting operation 1 during the period in which the switching transistor MN1 is OFF, the output voltage Vout does not drop so much that the current Ia is not small, and the current If proportional to the current Ia flows through the resistor R4, generating the voltage Vr4. is greater than the reference voltage Vref5, the output of the comparator CP4 becomes "H". That is, when the output voltage Vout is higher than the voltage Vout2d, the output of the comparator CP4 becomes "H". During the period in which the switching transistor MN1 is ON, neither the current Ia nor the current If flows, so the output of the comparator CP4 is "L".

When the output of the comparator CP4 is "H", the logic circuit 276 sets the signal Ven to "H" when the signal Vdrv (="H") for turning on the switching transistor MN1 is input. Further, when a signal Vdrv (="L") for turning off the switching transistor MN1 is input, the signal Ven is set to "L" if the output voltage Vout is higher than the voltage Vout2d and the output of the comparator CP4 is "H". At this time, even if the current value of the current limiting feedback circuit 27A is Ib<Ic, the current hold circuit 274A does not operate.

When the output voltage Vout drops below the voltage Vout2d, the current If also decreases in accordance with the decrease in the current Ia, and the voltage Vr4 generated across the resistor R4 becomes lower than the voltage Vref5. Therefore, the output of the comparator CP4 remains "L", the reset operation is stopped, the signal Ven remains "H", and the current hold circuit 274A remains enabled.

FIG. 11 shows a circuit diagram of the current hold circuit 274A of the current limit feedback circuit of FIG. Switches SW4 and SW5 are added to the current hold circuit 274 described in FIG. 4 so as to correspond to the signal Ven. When the signal Ven becomes "H", the switch SW4 is turned on, the switch SW5 is turned off, the current mirror circuit operates, and the current hold circuit 274A operates.

As described above, if the voltage Vref5 is set such that the output voltage Vout when the signal Ven is held at "H" is the voltage Vout2d which is lower than the output voltage when the current value is Ib<Ic. , as in the current limiting characteristics of FIG. 12, when the output voltage Vout becomes lower than the voltage Vout2d, the operation is switched to the current limiting operation 2 to rapidly limit the current. If the proportional relationship of the feedback currents Ifb1 to Ifb3 of the current limiting feedback circuit 274 and the values of the resistor R1 and the capacitor C4 are the same in the case of the current limiting characteristics of FIG. The current limiting characteristics of the voltages Vout3 and Vout4 are the same as in FIG. 7(a).

A timing chart showing this current limiting operation is shown in FIG. FIG. 13 shows a switching portion between the current limiting operation 1 and the current limiting operation 2. In FIG. The difference from FIG. 8, which is the timing chart of the current limiting operation in which the output voltage Vout is not detected by the comparator CP4, is that the waveform of the signal Ven is added. In FIG. 8, when the current value of the current limiting feedback circuit 27 becomes Ib<Ic, the current Ie flows and the current limiting operation 1 is switched to the current limiting operation 2. In FIG. Even if the current Ie is flowing, the current hold circuit 274A operates only when the signal Ven changes from "L" to "H", and the current limit operation 1 is switched to the current limit operation 2.

<Second Modification (27B) of Current Limiting Feedback Circuit 27>
FIG. 14 shows a current limiting feedback circuit 27B of a second modification, which includes means for detecting the output voltage Vout and enabling control of the current hold circuit 274A. In the current limiting feedback circuit 27B of FIG. 14, in the same way as the circuit described in FIG. , a proportional current Ig is drawn, and the current Ig, the voltage Vr5 generated by the resistor R5, and the voltage Vref6 of the voltage source VB6 are compared by the comparator CP5.

In the state of current limiting operation 1 during the period when the switching transistor MN1 is OFF, the current value of the current limiting feedback circuit 28B is Ib>Ic. "H". During the period in which the switching transistor MN1 is ON, the current Ia does not flow, so the current values are Ib=0 and Id=Ic. The output becomes "L".

When the output of the comparator CP5 is "H", the logic circuit 277 sets the signal Ven to "H" when the signal Vdrv (="H") for turning on the switching transistor MN1 is input. Further, when a signal Vdrv (=“L”) for turning off the switching transistor MN1 is input, the signal Ven is set to “L” if the output voltage Vout is higher than the voltage Vout2d and the output of the comparator CP5 is “H”. do. At this time, even if the current value of the current limit feedback circuit 27B is Ib<Ic, the current hold circuit 274A does not operate.

As the output voltage Vout decreases, the current Ia decreases, the current Ib also decreases, and Ib<Ic. output remains at "L", the reset operation ceases, and the signal Ven remains at "H".

<Third Modification (27C) of Current Limiting Feedback Circuit 27>
FIG. 15 shows a current limiting feedback circuit 27C of a second modification, which includes means for canceling the current hold of the current hold circuit 274B when the output voltage Vout drops close to 0V. This current limit feedback circuit 27C is a modification of the current limit feedback circuit 27A of FIG. FIG. 16 shows a current hold circuit 274B in this current limit feedback circuit 27B.

The current limiting feedback circuit 27C of FIG. 15 draws out a current Ih proportional to the current Ia by the first current mirror circuit 271B, converts this current Ih into a voltage Vr6 by a resistor R6, and converts the reference voltage Vref7 of the voltage source VB7 and the comparator CP6 into a voltage Vr6. When the voltage Vr6 is lower than the reference voltage Vref7, the signal Vlow is set to "H". The signal Vlow is input to the current hold circuit 274B via an AND circuit AND1 controlled by an inverter INV2 that inverts the signal Vdrv.

The current hold circuit 274B of FIG. 16 is the same as the current hold circuit 274A of FIG. 11 except that an OR circuit OR1 is added to turn on the sampling switch SW3 when either the voltage Vsp or the voltage Vlow becomes "H". is.

When the switching transistor MN1 is off, the state of the output voltage Vout can be detected by the current Ia. becomes larger. As a result, the charging current (=Ioff-Ifb3) of the capacitor C4 that controls the OFF period becomes particularly small, so that the OFF period is affected by variations in the current Ifb3.

At this time, the current Ih also decreases at the same time, so when the voltage Vr6 becomes lower than the reference voltage Vref7, the signal Vlow output from the converter CP6 becomes "H". At this time, since the signal Vdrv is "L", the inverter INV2 opens the AND gate AND1, and the "H" signal Vlow is directly input to the current hold circuit 274B to turn on the switch SW3 to hold the current. release. As a result, the feedback currents Ifb1-Ifb3 are controlled by the current Ie.

At this time, the output current Iout becomes the current Ia=0 when the conduction period of the diode D1 on the secondary side ends in the current limiting operation 3 and the free oscillation period starts, so the current Id=Ic and Ie=maximum. The feedback current Ifb3 becomes maximum, and the charging current (=Ioff-Ifb3) of the capacitor C4 further decreases. As a result, the OFF period becomes longer, and the short-circuit load current can be reduced when the output voltage Vout drops.

<Fourth Modification (27D) of Current Limiting Feedback Circuit 27>
FIG. 17 shows a current limiting feedback circuit 27D of a fourth modification, which includes means for canceling the current hold of the current hold circuit 274B when the output voltage Vout drops close to 0V. This current limiting feedback circuit 27D is a modification of the current limiting feedback circuit 27B of FIG. A current hold circuit 274B in this current limiting feedback circuit 27D is the same as that shown in FIG. Since the configuration and operation are the same as those described with reference to FIGS. 14 and 16, detailed description thereof will be omitted.

<Other Modifications>
In the above-described embodiment, when detecting a drop in the output voltage Vout to the voltages Vout2a, Vout2b, and Vout2c from the voltage obtained at the auxiliary winding L3 during the OFF period of the switching transistor MN1, the auxiliary winding is detected during the OFF period of the switching transistor MN1. When the voltage obtained on the line L3 is a negative voltage, when the negative voltage VL3 reaches a certain value, it is detected that the current Ia decreases and becomes Ib<Ic.

However, the present invention is not limited to this. If the voltage obtained at the auxiliary winding L3 during the OFF period of the switching transistor MN1 is a positive voltage, the current Ia decreases when the positive voltage reaches a certain value. Then, it may be detected that Ib<Ic. In other words, when the absolute value of the voltage obtained at the auxiliary winding L3 becomes smaller than a predetermined value during the OFF period of the switching transistor MN1, it is sufficient to detect that the current Ia decreases and becomes Ib<Ic. . This also applies to the detection of the enable voltage Vout2d described with reference to FIGS.

10: Transformer, L1: Primary Winding, L2: Secondary Winding, L3: Auxiliary Winding 20: Control Circuit, 21: ON Period Control Circuit, 22: OFF Period Control Circuit, 221: Logic Circuit, 23: SRFF Circuit 24: Drive circuit 25: Charging circuit 26: Inversion detection circuit 27, 27A, 27B, 27C, 27D: Current limiting feedback circuit 271, 271A, 271B, 271C: First current mirror circuit 272, 272A 274, 274A, 274B: current hold circuit 275: timing generation circuit 276, 277: logic circuit 28: Ipc distribution circuit 29: internal power supply circuit 30: output voltage feedback circuit 40: photocoupler

Claims (10)

A switching transistor that is ON/OFF controlled, a sense resistor that generates a sense voltage when the switching transistor is turned on, a primary winding to which an input voltage is applied when the switching transistor is turned on, and an output voltage to a load. a transformer having a secondary winding for supplying power and an auxiliary winding for detecting the output voltage; a photocoupler for generating first and second photocoupler currents corresponding to the output voltage; a current limiting feedback circuit that generates first, second, and third feedback currents inversely proportional to , taking the sense voltage, the first optocoupler current, and the first feedback current to generate an OFF timing signal for the switching transistor an ON period control circuit to generate; a voltage of a fourth capacitor charged with a constant current or a difference current between the constant current and the third feedback current and discharged when the switching transistor is turned on; the second feedback current; an OFF period control circuit that takes in the second photocoupler current and generates an ON timing signal for the switching transistor;
wherein the current limiting feedback circuit generates the first, second and third feedback currents when the output voltage is less than or equal to a second output voltage that is lower than the first output voltage;
When the output voltage exceeds the first output voltage, the ON period control circuit takes in the sense voltage and the first photocoupler current, and the OFF period control circuit is charged with the constant current. 4 capturing the voltage of the capacitor and the second photocoupler current,
When the output voltage becomes lower than the second output voltage, the ON period control circuit takes in the sense voltage and the first feedback current, and the OFF period control circuit receives the constant current and the third feedback current. taking in the second feedback current and the voltage of a fourth capacitor charged with the differential current of the feedback current;
A switching power supply device characterized by: The switching power supply device according to claim 1,
The switching power supply device, wherein the current limiting feedback circuit is enabled when the output voltage becomes lower than the second output voltage. The switching power supply device according to claim 1 or 2,
A switching power supply, wherein said first, second and third feedback currents of said current limiting feedback circuit are independent of each other, and said first and second photocoupler currents of said photocoupler are independent of each other. The switching power supply device according to any one of claims 1 to 3,
a first resistor connected between the auxiliary winding and the current limiting feedback circuit;
The first, second and third feedback currents are voltages that generate a current in the auxiliary winding that is inversely proportional to the current that flows in the first resistor due to the voltage generated in the auxiliary winding during the OFF period of the switching transistor. A switching power supply device characterized in that the current is held at the reversal timing of . The switching power supply device according to any one of claims 1 to 4,
The ON period control circuit generates an OFF timing signal for the switching transistor at an earlier timing as the first photocoupler current is larger, the first feedback current is larger, and the sense voltage is larger,
The OFF period control circuit generates the ON timing signal of the switching transistor at a later timing as the second photocoupler current becomes larger, the second feedback current becomes larger, and the third feedback current becomes larger. A switching power supply device characterized by: The switching power supply device according to any one of claims 1 to 5,
The ON period control circuit includes a second resistor inserted in a path through which the first photocoupler current or the first feedback current flows when the switching transistor is ON, and the first photocoupler current of the second resistor. or a first comparator that generates the OFF timing signal when a second voltage generated on the introduction side of the first feedback current becomes the same voltage as the sense voltage. The switching power supply device according to any one of claims 1 to 5,
The OFF period control circuit includes a third resistor inserted so as to cause a voltage drop from the voltage of the fourth capacitor by the second photocoupler current or the second feedback current, and the fourth capacitor connected to the third resistor. and a second comparator that generates the ON timing signal when a third voltage of a terminal on the opposite side of the side reaches a predetermined value. In the switching power supply device according to claim 5 or 7,
The switching power supply device, wherein the ON timing signal of the OFF period control circuit is retimed at the inversion timing of the voltage generated in the auxiliary winding. The switching power supply device according to claim 1,
The current limiting feedback circuit samples a signal inversely proportional to the output voltage when the switching transistor is controlled to be OFF when the output voltage becomes equal to or lower than a second output voltage lower than the first output voltage, and A current hold circuit is provided for holding the first, second and third feedback currents corresponding to the sampled signal from the time of sampling until the switching transistor is turned off next time. and switching power supplies. In the switching power supply device according to claim 9,
The current hold circuit releases hold of the first, second and third feedback currents when the output voltage becomes equal to or lower than a predetermined voltage lower than the second output voltage. 3. A switching power supply device characterized in that the feedback current is output in inverse proportion to the output voltage.

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