JP7151540B2 - Abnormality detection device for switching elements - Google Patents

Description

The present invention relates to an abnormality detection device for switching elements.

Conventionally, as an abnormality detection device for this type of switching element, one that includes a plurality of drive circuits and a control device has been proposed (see, for example, Patent Document 1). A plurality of drive circuits are provided for each of the plurality of switching elements of the inverter, drive the corresponding switching elements, and transmit an abnormality signal and a pulse signal of an assigned frequency to one communication line when an abnormality occurs. do. In this abnormality detection device, the control device receives the abnormality signal and the pulse signal transmitted to the communication line, and detects which switching element among the plurality of switching elements has become abnormal.

JP 2017-112786 A

In the switching element abnormality detection device described above, when an abnormality occurs in a plurality of switching elements at the same time, an abnormality signal or pulse signal collides. When such a collision of signals occurs, it becomes impossible to specify an abnormality to be dealt with, and it becomes impossible to properly control the switching element.

The main object of the switching element abnormality detection device of the present invention is to identify an abnormality that should be dealt with more appropriately when an abnormality occurs in a plurality of switching elements at the same time.

In order to achieve the main object described above, the switching element abnormality detection apparatus of the present invention employs the following means.

The switching element abnormality detection device of the present invention includes:
a plurality of drive circuits provided for each of a plurality of switching elements, driving the corresponding switching element and transmitting an abnormality message to a communication line when an abnormality occurs in the corresponding switching element;
An abnormality detection device for a switching element comprising:
The anomaly message includes information on the anomaly that has occurred,
The plurality of drive circuits are
storing information on an abnormality occurring in the corresponding switching element among the plurality of switching elements;
using the abnormality information included in the abnormality message received from the other drive circuit via the communication line, the stored abnormality information, and the priority of abnormality to be dealt with for a plurality of abnormalities identifying an abnormality to be dealt with, from among an abnormality occurring in the corresponding switching element and an abnormality occurring in the switching element corresponding to the other drive circuit;
This is the gist of it.

In the abnormality detection device for switching elements of the present invention, the abnormality message includes information about the abnormality that has occurred. The plurality of drive circuits store information on abnormalities occurring in corresponding switching elements among the plurality of switching elements. Then, using the abnormality information included in the abnormality message received from the other drive circuit via the communication line, the stored abnormality information, and the priority of the abnormality to be handled for the plurality of abnormalities, An abnormality to be dealt with is specified from among the abnormality occurring in the corresponding switching element and the abnormality occurring in the switching element corresponding to the other drive circuit. Thereby, when an abnormality occurs in a plurality of switching elements at the same time, it is possible to identify an abnormality that should be dealt with more appropriately.

In such a switching element abnormality detection device of the present invention, the plurality of drive circuits may drive the switching elements based on the set abnormality to be handled. By doing so, it is possible to appropriately control the switching element according to the abnormality to be dealt with.

1 is a schematic diagram showing the configuration of a hybrid vehicle 20 equipped with a switching element abnormality detection device according to an embodiment of the present invention; FIG. 1 is a configuration diagram showing an outline of the configuration of an electric drive system including motors MG1 and MG2; FIG. 4 is an explanatory diagram for explaining the configuration of an inverter 41; FIG. FIG. 4 is an explanatory diagram for explaining the contents of an abnormal message; 4 is an explanatory diagram for explaining an example of the operation of drive circuits 4uu to 4wl and a motor ECU 40; FIG. 4 is a timing chart showing an example of waveforms (temporal changes in amplitude) of gate signals UU, UL, VU, VL, WU, and WL when all transistors T11 to T16 are normal; 4 is a timing chart showing an example of waveforms (temporal changes in amplitude) of gate signals UU, UL, VU, VL, WU, and WL when a stuck-off abnormality occurs in transistor T11 and transistors T21 to T16 are normal; .

Next, a mode for carrying out the present invention will be described using examples.

FIG. 1 is a configuration diagram showing an outline of the configuration of a hybrid vehicle 20 equipped with an abnormality detection device for switching elements according to an embodiment of the present invention. FIG. 2 is a configuration diagram showing an outline of the configuration of an electric drive system including motors MG1 and MG2. FIG. 3 is an explanatory diagram for explaining the configuration of the inverter 41. As shown in FIG. As shown in FIG. 1, the hybrid vehicle 20 of the embodiment includes an engine 22, a planetary gear 30, motors MG1 and MG2, inverters 41 and 42, a battery 50 as a power storage device, a boost converter 55, and a system main unit. It includes a relay 56 and a hybrid electronic control unit (hereinafter referred to as “HVECU”) 70 .

The engine 22 is configured as an internal combustion engine that outputs power using gasoline, light oil, or the like as fuel. The operation of the engine 22 is controlled by an engine electronic control unit (hereinafter referred to as “engine ECU”) 24 .

Although not shown, the engine ECU 24 is configured as a microprocessor centering on a CPU, and in addition to the CPU, it has a ROM for storing processing programs, a RAM for temporarily storing data, an input/output port, and a communication port. . Signals from various sensors necessary for controlling the operation of the engine 22, such as the crank angle θcr from the crank position sensor 23 that detects the rotational position of the crankshaft 26 of the engine 22, are input to the engine ECU 24 from the input port. It is Various control signals for controlling the operation of the engine 22 are output from the engine ECU 24 through an output port. The engine ECU 24 is connected to the HVECU 70 via a communication port. The engine ECU 24 calculates the rotational speed Ne of the engine 22 based on the crank angle θcr from the crank position sensor 23 .

The planetary gear 30 is configured as a single pinion planetary gear mechanism. The sun gear of the planetary gear 30 is connected to the rotor of the motor MG1. A ring gear of the planetary gear 30 is connected to a drive shaft 36 that is connected to drive wheels 39a and 39b via a differential gear 38. As shown in FIG. A crankshaft 26 of the engine 22 is connected to the carrier of the planetary gear 30 via a damper 28 .

The motor MG1 is configured as a synchronous generator-motor having a rotor embedded with permanent magnets and a stator wound with a three-phase coil. ing. The motor MG2 is, like the motor MG1, configured as a synchronous generator-motor having a rotor embedded with permanent magnets and a stator wound with a three-phase coil. ing.

As shown in FIG. 2, the inverter 41 is connected to the high voltage power line 54a. The inverter 41 has transistors T11 to T16 as six switching elements, and six diodes D11 to D16 connected in parallel to the transistors T11 to T16 in opposite directions. The transistors T11 to T16 are arranged in pairs so as to be on the source side and the sink side with respect to the positive line and the negative line of the high-voltage power line 54a, respectively. Further, each of the three-phase coils (U-phase, V-phase, W-phase) of the motor MG1 is connected to each of the connection points between the transistors T11 to T16 which form a pair.

The inverter 41, as shown in FIG. 3, has a drive circuit 4uu corresponding to the U-phase upper arm transistor T11, a drive circuit 4ul corresponding to the U-phase lower arm transistor T14, and a V-phase upper arm transistor T12. a drive circuit 4vu (not shown) corresponding to the V-phase lower arm transistor T15, a drive circuit 4vl (not shown) corresponding to the W-phase upper arm transistor T13, and a drive circuit 4wu (not shown) corresponding to the W-phase upper arm transistor T13 , and a driving circuit 4wl corresponding to the transistor T16 of the W-phase lower arm. Since the drive circuits 4uu to 4wl have the same hardware configuration, detailed illustration of the configuration of the drive circuits 4ul to 4wl is omitted in FIG.

Each drive circuit 4uu to 4wl includes a drive IC 102, three abnormality detection circuits 104, a fail output circuit 106, a controller 108, and a transceiver 110.

The drive IC 102 inputs gate signals UU, UL, VU, VL, WU or WL from the motor ECU 40 via the photocoupler 100, and controls on/off of the corresponding transistors T11 to T16. When the drive stop signal is input from the fail output circuit 106, the drive IC 102 stops drive control of the corresponding transistor among the transistors T11 to T16. Further, when a fail-safe (F/S) control execution command is input from the controller 108, the drive IC 102 executes F/S control for the transistors T11 to T16. F/S control will be described later.

The three fault detection circuits 104 sequentially detect faults related to the corresponding transistors T11 to T16, that is, element faults such as short circuits, overcurrents, and overheating, and circuit faults such as voltage drops and erroneous driving in the drive circuits 4uu to 4wl. and an identifier (ID) for specifying the corresponding transistors T11 to T16 and information indicating which abnormality is detected (hereinafter referred to as "abnormality information"). natural number) is output to the fail output circuit 106 . FIG. 4 is an explanatory diagram for explaining the content of the abnormal message. In the error message, m bits (m is a natural number) from the first bit indicate an identifier (ID), and bits (m+1) to the last bit indicate detected error information.

The fail output circuit 106 stores the error messages output from the error detection circuit 104 as a history in an internal memory (not shown) in the order in which they were detected, outputs the latest error message to the controller 108 , and sends a drive stop signal to the drive IC 102 . Output.

The controller 108 outputs an abnormality message to the communication line Lc via the transceiver 110, and also outputs an abnormality message from another drive circuit (any one of the drive circuits 4uu to 4wl) transmitting the communication line Lc via the transceiver 110. Enter your message.

When the controller 108 receives an abnormal message from the fail output circuit 106 and does not receive an abnormal message from another drive circuit transmitting the communication line Lc via the transceiver 110, the controller 108 receives the error message from the fail output circuit 106. It outputs to drive IC 102 a F/S control execution command according to the abnormality information included in the abnormality message. For example, when the abnormality information included in the abnormality message from the fail output circuit 106 is the stuck-off abnormality (abnormality fixed at off) of the corresponding transistors T11 to T16, the F/ S control (for example, three-phase ON control that turns off the transistors T11 to T13 in the upper arm and turns on the transistors T14 to T16 in the lower arm) is executed.

When the controller 108 receives an abnormal message from the fail output circuit 106 and receives an abnormal message from another drive circuit transmitting the communication line Lc via the transceiver 110, the error message is stored in advance. The order of priority of anomalies to be dealt with for anomalies related to the corresponding transistors T11 to T16, that is, element anomalies such as short circuits, overcurrents, and overheating, and circuit anomalies such as voltage drops and erroneous driving in the drive circuits 4uu to 4wl; In accordance with the abnormality information having the higher priority among the abnormality information included in the abnormality message from the fail output circuit 106 and the abnormality information from the transceiver 110 of the other drive circuit input via the transceiver 110 Then, an F/S control execution command is transmitted to the driving IC 102 . For example, the abnormality information included in the abnormality message from the fail output circuit 106 is the stuck-off abnormality of the corresponding transistors T11 to T16, and the abnormality information from the transceiver 110 of another drive circuit input via the transceiver 110 is If there is an overcurrent in the transistors T11 to T16 corresponding to other drive circuits, and if the stuck-off error has a higher priority than the overcurrent, the F/S control suitable for the stuck-off error (for example, the above-mentioned three-phase on control).

When controller 108 receives an abnormal message from another drive circuit transmitting communication line Lc via transceiver 110 when no abnormal message is input from fail output circuit 106, controller 108 receives a communication line Lc. It outputs to drive IC 102 a F/S control execution command according to the abnormality information contained in the abnormality message from Lc.

The inverter 42 is connected to the high voltage power line 54a. The inverter 42 has transistors T21 to T26 as six switching elements, and six diodes D21 to D26 connected in parallel to the transistors T21 to T26 in the reverse direction. The transistors T21 to T26 are arranged in pairs so as to be on the source side and the sink side with respect to the positive line and the negative line of the high-voltage power line 54a, respectively. Further, each of the three-phase coils (U-phase, V-phase, W-phase) of the motor MG2 is connected to each of the connection points between the transistors T21 to T26 that form a pair. Although not shown, the inverter 42 includes a drive circuit 5uu corresponding to the U-phase upper arm transistor T21, a drive circuit 5ul corresponding to the U-phase lower arm transistor T24, and a drive circuit corresponding to the V-phase upper arm transistor T22. 5vu, a drive circuit 5vl corresponding to the V-phase lower arm transistor T25, a drive circuit 5wu corresponding to the W-phase upper arm transistor T23, and a drive circuit 5wl corresponding to the W-phase lower arm transistor T26. there is Since the driving circuits 5uu to 5wl have the same configuration as the driving circuits 4uu to 4wl, detailed description thereof will be omitted.

Inverter 41 is operated by a motor electronic control unit (hereinafter referred to as "motor ECU") 40, which adjusts the ON time ratio of paired transistors T11 to T16 when a voltage is applied. A rotating magnetic field is formed in the phase coil, and the motor MG1 is rotationally driven. When the voltage is applied to the inverter 42, the motor ECU 40 adjusts the ratio of the ON time of the paired transistors T21 to T26, thereby forming a rotating magnetic field in the three-phase coil and rotating the motor MG2. driven.

The boost converter 55 is connected to a high-voltage power line 54a to which the inverters 41 and 42 are connected, and a low-voltage power line 54b to which the battery 50 is connected. The boost converter 55 has transistors T31 and T32 as two switching elements, two diodes D31 and D32 connected in parallel to the transistors T31 and T32 in opposite directions, and a reactor L. The transistor T31 is connected to the positive line of the high-voltage power line 54a. The transistor T32 is connected to the transistor T31 and the negative lines of the high-voltage power line 54a and the low-voltage power line 54b. The reactor L is connected to a connection point between the transistors T31 and T32 and the positive line of the low-voltage power line 54b. The step-up converter 55 boosts the power on the low voltage side power line 54b and supplies it to the high voltage side power line 54a or supplies it to the high voltage side power line 54a by adjusting the ratio of the ON time of the transistors T31 and T32 by the motor ECU 40. The power on the power line 54a is stepped down and supplied to the low-voltage side power line 54b. Smoothing capacitors 57 are attached to the positive and negative lines of the high-voltage power line 54a, and smoothing capacitors 57 are attached to the positive and negative lines of the low-voltage power line 54b. A capacitor 58 is attached.

Although not shown, the motor ECU 40 is configured as a microprocessor centering on a CPU, and in addition to the CPU, includes a ROM for storing processing programs, a RAM for temporarily storing data, an input/output port, and a communication port. . As shown in FIG. 1, the motor ECU 40 receives signals from various sensors necessary for driving and controlling the motors MG1 and MG2 and the boost converter 55 via input ports. Signals input to the motor ECU 40 include, for example, rotational position detection sensors (for example, resolvers) 43 and 44 that detect the rotational positions of the rotors of the motors MG1 and MG2, and rotational positions θm1 and θm2 of the motors MG1 and MG2. Phase currents Iu1, Iv1, Iu2, and Iv2 from current sensors 45u, 45v, 46u, and 46v that detect the current flowing in each phase can be mentioned. Also, the voltage of the capacitor 57 (the voltage of the high-voltage side power line 54a) VH from the voltage sensor 57a attached between the terminals of the capacitor 57 and the voltage of the capacitor 58 from the voltage sensor 58a attached between the terminals of the capacitor 58 (Voltage of the low-voltage power line 54b) VL, and the current IL flowing through the reactor L from the current sensor 55a attached to the terminal of the reactor L can also be mentioned. The motor ECU 40 outputs switching control signals to the transistors T11 to T16 and T21 to T26 of the inverters 41 and 42 and switching control signals to the transistors T31 and T32 of the boost converter 55 through the output port. The motor ECU 40 is connected to the HVECU 70 via a communication port. The motor ECU 40 determines the electrical angles θe1, θe2, the angular velocities ωm1, ωm2, the rotational speeds Nm1, Nm2 of the motors MG1, MG2 based on the rotational positions θm1, θm2 of the rotors of the motors MG1, MG2 from the rotational position detection sensors 43, 44. is calculated. Also, the motor ECU 40 receives an abnormality message on the communication line Lc via the transceiver 112 .

The battery 50 is configured as, for example, a lithium-ion secondary battery or a nickel-hydrogen secondary battery, and is connected to the low-voltage side power line 54b. The battery 50 is managed by a battery electronic control unit (hereinafter referred to as “battery ECU”) 52 .

Although not shown, the battery ECU 52 is configured as a microprocessor centering on a CPU, and in addition to the CPU, includes a ROM for storing processing programs, a RAM for temporarily storing data, an input/output port, and a communication port. . Signals from various sensors necessary for managing the battery 50 are input to the battery ECU 52 through an input port. Signals input to the battery ECU 52 include, for example, a voltage Vb from a voltage sensor 51a installed between the terminals of the battery 50, a battery current Ib from a current sensor 51b attached to the output terminal of the battery 50, The temperature Tb from the attached temperature sensor 51c can be mentioned. The battery ECU 52 is connected to the HVECU 70 via a communication port. The battery ECU 52 calculates the charge ratio SOC based on the integrated value of the battery current Ib from the current sensor 51b. The power storage ratio SOC is the ratio of the amount of electric power that can be discharged from the battery 50 to the total capacity of the battery 50 .

The system main relay 56 is provided closer to the battery 50 than the capacitor 58 in the low-voltage power line 54b. System main relay 56 is ON/OFF-controlled by HVECU 70 to connect and disconnect battery 50 and boost converter 55 .

Although not shown, the HVECU 70 is configured as a microprocessor centering on a CPU, and in addition to the CPU, has a ROM for storing processing programs, a RAM for temporarily storing data, an input/output port, and a communication port. Signals from various sensors are input to the HVECU 70 through input ports. Signals input to the HVECU 70 include, for example, an ignition signal from an ignition switch 80 and a shift position SP from a shift position sensor 82 that detects the operating position of a shift lever 81 . Further, the accelerator opening Acc from an accelerator pedal position sensor 84 that detects the amount of depression of the accelerator pedal 83, the brake pedal position BP from a brake pedal position sensor 86 that detects the amount of depression of the brake pedal 85, and the vehicle speed sensor 88. Vehicle speed V can also be mentioned. The HVECU 70 is connected to the engine ECU 24, the motor ECU 40, and the battery ECU 52 via communication ports, as described above.

The hybrid vehicle 20 of the embodiment configured in this manner runs in a hybrid running (HV running) mode in which the engine 22 is operated and runs in an electric running (EV running) mode in which the engine 22 is not operated. .

Next, the operation of the hybrid vehicle 20 configured in this way, in particular, the operation when an abnormality related to the transistors T11 to T16 of the inverter 41 occurs will be described. FIG. 5 is an explanatory diagram for explaining an example of the operation of the drive circuits 4uu to 4wl and the motor ECU 40. As shown in FIG. Here, the operation when the transistor T11 is stuck off and the transistors T12 to T16 are normal will be described.

When an off-stuck abnormality occurs in the transistor T11, one of the three abnormality detection circuits 104 of the drive circuit 4uu corresponding to the transistor T11 (abnormal arm) detects the off-stuck abnormality, and outputs the off-stuck abnormality to the fail output circuit 106 as abnormality information. Output an error message, including that it is an error. The fail output circuit 106, which has received the abnormal message, stores the received abnormal message in its internal memory, outputs the latest abnormal message, that is, the input abnormal message to the controller 108, and outputs a drive stop signal to the drive IC 102, Controller 108 transmits an error message to communication line Lc via transceiver 110 (step S100). The drive IC 102 that receives the drive stop signal stops drive control of the transistor T11. In this way, by outputting a drive stop signal from the fail output circuit 106 to the drive IC 102 to stop driving the transistor T11, an abnormal message is transmitted to the motor ECU 40 via the transceivers 110 and 120, and the photocoupler is transmitted from the motor ECU 40. The driving of the transistor T11 (switching between ON and OFF) can be stopped more quickly than when the driving of the transistor T11 is stopped by outputting a drive stop signal to the driving IC 102 via 100. FIG.

Next, when the abnormality message is transmitted to the communication line Lc and the driving of the transistor T11 is stopped, F/S control is executed according to the abnormality message (step S110), and the process is terminated. Here, the off gate signal UU is sent to the transistor T11, but since the transistor T11 is stuck off now, the transistor T11 is off regardless of the gate signal UU.

In the drive circuits 4ul to 4wl corresponding to the normal transistors T12 to T16 (normal arm), when the controller 108 starts receiving the abnormal message sent to the communication line Lc via the transceiver 110, the controller 108 drives the drive IC 102. A stop signal is output (step S200). The drive IC 102 that receives the drive stop signal stops drive control of the corresponding transistors T12 to T16 (stops on/off switching of the gate signals UL, VU, WU, and WL). Stopping the drive control to the corresponding transistors T12 to T16 requires some time from the start of reception of the abnormal message sent to the communication line Lc to the completion of reception. This is because, even if it is possible to recognize that the transistor corresponding to , the abnormality information contained in the abnormality message cannot be recognized, it is better to stop driving the transistors T21 to T16 just in case.

When the reception of the abnormal message is completed, the F/S control corresponding to the abnormal message is executed (step S210), and the process ends. For example, when the ID included in the error message is the transistor T11 and the error information is fixed off, the F/S control turns on the lower-arm transistors T12, T14, and T16 among the transistors T12 to T16, and turns on T13 and T15. Execute three-phase on control to turn off. In this way, by executing F/S control according to an abnormality message from another drive circuit that transmits the communication line Lc, the normal transistors T12 to T16 can be properly controlled according to the content of the abnormality.

When the motor ECU 40 detects that an abnormality message is being transmitted to the communication line Lc via the transceiver 110, the motor ECU 40 receives the abnormality message and determines the content of the abnormality message (ID and abnormality information, that is, which of the transistors T11 to T16). information on what kind of abnormality has occurred in the transistor) is confirmed (step S300). Then, an abnormal message is transmitted to the HVECU 70 (step S310), and this routine ends. The HVECU 70 that has received the abnormality message transmits an instruction to execute the F/S control according to the abnormality message to the engine ECU 24 or the like as necessary. As a result, the behavior of the entire vehicle can be appropriately and comprehensively controlled with respect to the content of the abnormality message.

FIG. 6 is a timing chart showing an example of waveforms (temporal changes in amplitude) of gate signals UU, UL, VU, VL, WU, and WL when all transistors T11 to T16 are normal. When all the transistors T11 to T16 are normal, the gate signals UU, UL, VU, VL, WU, and WL are out of phase with the gate signal UU by a predetermined angle. The gate signal UL, the gate signal VU and the gate signal VL, and the gate signal WU and the gate signal WL are opposite phase pulse signals.

FIG. 7 shows an example of the waveforms (temporal changes in amplitude) of the gate signals UU, UL, VU, VL, WU, and WL when the transistor T11 is stuck off and the transistors T12 to T16 are normal. It is a timing chart. When the transistor T11 is stuck off, three-phase ON control is executed to turn ON the lower-arm transistors T12, T14, and T16 among the transistors T12 to T16 and turn OFF the transistors T13 and T15. Through such processing, the transistors T11 to T16 can be properly controlled according to the abnormality that has occurred. In this way, since the controller 108 of the drive circuits 4uu to 4wl instructs the drive IC 102 to execute the F/S control, an abnormality message is transmitted to the motor ECU 40 via the transceivers 110 and 120, and the photocoupler 100 is activated by the motor ECU 40. Faster F/S control can be realized than in the case where the drive IC 102 is instructed to execute the F/S control via the F/S control.

In the hybrid vehicle 20 of the embodiment, different abnormalities occur in different transistors T11 to T16 at the same time (for example, an off-fixing abnormality occurs in the transistor T11, an overcurrent occurs in the transistor T15, etc.), and the communication line Two failure messages may be transmitted to Lc. In this case, the controller 108 inputs the abnormality information contained in the abnormality message from the fail output circuit 106 and the communication line Lc via the transceiver 110 based on the stored priority of the abnormality to be handled. It transmits to the drive IC 102 a F/S control execution command according to the abnormality information with the higher priority to be dealt with among the abnormality information contained in the abnormality message from the transceiver 110 of the other drive circuit. For example, when the stuck-off abnormality occurs in the transistor T11 and the overcurrent occurs in the transistor T15, when the stuck-off abnormality has a higher priority than the overcurrent, the controllers 108 of the drive circuits 4uu to 4wl control the stuck-off state. A F/S control execution command for coping with the abnormality is output to the corresponding drive IC 102 . The driving ICs 102 of the driving circuits 4uu to 4wl execute F/S control for coping with the stuck-off abnormality for the transistors T11 to T16. /S control can be executed.

Furthermore, in the hybrid vehicle 20 of the embodiment, an internal memory (not shown) of the fail output circuit 106 of the drive circuits 4uu to 4wl stores anomalies detected by the anomaly detection circuit 104 in chronological order as an anomaly history. Therefore, when a signal inquiring about past abnormalities is input from the motor ECU 40 via the transceivers 112, 110 and the controller 108, the fail output circuit 106 detects the corresponding abnormality from the stored abnormality history. , the communication line Lc, and the transceiver 112 to the motor ECU 40 . As a result, the motor EUC 40 can recognize past anomalies and perform more appropriate control for past anomalies.

According to the hybrid vehicle 20 of the embodiment described above, the abnormality message includes information on the abnormality that has occurred, and the drive circuits 4uu to 4wl and 5uu to 5wl correspond to the plurality of transistors T11 to T16 and T21 to T26. Information on anomalies occurring in transistors is stored, information on anomalies included in anomaly messages received from other drive circuits via a communication line Lc, information on the stored anomalies, and information on a plurality of anomalies to be dealt with. Priorities are used to identify an abnormality that should be dealt with among an abnormality that has occurred in the corresponding transistor and an abnormality that has occurred in the other transistors corresponding to the drive circuits. If anomalies occur at the same time, it is possible to identify the anomaly that should be dealt with more appropriately.

In the hybrid vehicle 20 of the embodiment, the drive circuits 4uu to 4wl and 5uu to 5wl are provided with three abnormality detection circuits 104. FIG. However, the number of abnormality detection circuits 104 is not limited to three, and at least one is sufficient.

In the hybrid vehicle 20 of the embodiment, the drive circuits 4uu to 4wl and 5uu to 5wl have transceivers 110 . However, the transceiver 110 may not be provided, and the same functions may be installed in the drive IC 102 and the controller 108 .

In the hybrid vehicle 20 of the embodiment, the battery 50 is used as the power storage device, but the battery 50 may be replaced with a capacitor.

In the hybrid vehicle 20 of the embodiment, the case where the present invention is applied to the transistors T11 to T16 and T21 to T26 constituting the inverters 41 and 42 is illustrated. However, since the present invention only needs to detect an abnormality in a plurality of switching elements, it may be applied to the transistors T31 and T32 constituting the boost converter 55, for example.

The correspondence relationship between the main elements of the embodiments and the main elements of the invention described in the column of Means for Solving the Problems will be described. In the embodiment, the driving circuits 4uu to 4wl and 5uu to 5wl correspond to "a plurality of driving circuits".

Note that the correspondence relationship between the main elements of the examples and the main elements of the invention described in the column of Means for Solving the Problems is the Since it is an example for specifically explaining the mode for solving the problem, it does not limit the elements of the invention described in the column of the means for solving the problem. That is, the interpretation of the invention described in the column of Means to Solve the Problem should be made based on the description in that column, and the Examples are based on the description of the invention described in the column of Means to Solve the Problem. This is only a specific example.

Although the embodiments for carrying out the present invention have been described above, the present invention is not limited to such embodiments at all, and can be modified in various forms without departing from the scope of the present invention. Of course, it can be implemented.

INDUSTRIAL APPLICABILITY The present invention can be used in manufacturing industries such as an abnormality detection device for switching elements.

4uu~4wl, 5uu~5wl drive circuit, 20 hybrid vehicle, 22 engine, 23 crank position sensor, 24 engine electronic control unit (engine ECU), 26 crankshaft, 28 damper, 30 planetary gear, 36 drive shaft, 38 differential gear , 39a, 39b driving wheels 40 motor electronic control unit (motor ECU) 41, 42 inverter 43, 44 rotational position detection sensor 45u, 45v, 46u, 46v current sensor 50 battery 51a voltage sensor 51b current Sensor 51c Temperature sensor 52 Battery electronic control unit (battery ECU) 54a High voltage power line 54b Low voltage power line 55 Boost converter 55a Current sensor 56 System main relay 57, 58 Capacitor 57a , 58a voltage sensor, 70 hybrid electronic control unit (HVECU), 80 ignition switch, 81 shift lever, 82 shift position sensor, 83 accelerator pedal, 84 accelerator pedal position sensor, 85 brake pedal, 86 brake pedal position sensor, 88 vehicle speed Sensor, 100 Photocoupler, 102 Drive IC, 104 Abnormality Detection Circuit, 106 Fail Output Circuit, 108 Controller, 110, 112 Transceiver, D11 to D16, D21 to D26, D31, D32 Diode, L Reactor, MG, MG1, MG2 Motor , T11-T16, T21-T26, T31, T32 transistors.

Claims (1)

a plurality of drive circuits provided for each of a plurality of switching elements, driving the corresponding switching element and transmitting an abnormality message to a communication line when an abnormality occurs in the corresponding switching element;
An abnormality detection device for a switching element comprising:
The anomaly message includes information on the anomaly that has occurred,
The plurality of drive circuits are
storing information on an abnormality occurring in the corresponding switching element among the plurality of switching elements;
using the abnormality information included in the abnormality message received from the other drive circuit via the communication line, the stored abnormality information, and the priority of abnormality to be dealt with for a plurality of abnormalities identifying an abnormality to be dealt with, from among an abnormality occurring in the corresponding switching element and an abnormality occurring in the switching element corresponding to the other drive circuit;
An abnormality detection device for switching elements.

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