JP6716894B2 - Memory allocation device, memory allocation method, and program - Google Patents

Description

The present invention relates to a memory allocation device, a memory allocation method, and a program, and particularly to a memory allocation device, a memory allocation method, and a program that use both a volatile memory and a non-volatile memory as a main storage device.

An HDD (Hard Disk Drive) or the like, which has a low-speed but excellent cost per capacity and has a non-volatile characteristic, is used as an auxiliary storage device capable of guaranteeing the durability of data. On the other hand, although the cost per capacity is high, a DRAM (Dynamic Random Access Memory) capable of high-speed access has a volatile characteristic, and is therefore used as a main storage device that does not guarantee the persistence of data.

The auxiliary storage device and the main storage device are managed by the application side as separate storage devices because of the large difference in characteristics. The main storage device is accessed by a load/store instruction which is a synchronous instruction of a CPU (Central Processing Unit) or a MOV instruction. On the other hand, the auxiliary storage device has been subjected to asynchronous processing by DMA (Direct Memory Access) via a device driver. The reason is that the relatively slow I/O processing time is hidden from the CPU usage time.

In recent years, new nonvolatile memories such as NAND flash and phase change memory (hereinafter abbreviated as NV (Non-Volatile) memory) have appeared. These new NV memories have high-speed random access performance as well as low cost and non-volatility, that is, permanent data retention characteristics, and can be accessed by load/store or MOV instructions that are CPU synchronous instructions. To be done.

A new NV memory is being replaced by an auxiliary storage device such as an HDD, and a volatile memory such as DRAM and a new NV memory will coexist as a main storage device in an information processing device such as a computer. Is imagined.

Patent Document 1 discloses a system having memory devices having different latency times. This system allocates frequently accessed memory addresses to the shortest latency time area of physical memory.

Thus, the system makes this mapping available to the operating system, for example, by first allocating memory preferentially from the shortest latency time group. Also, when the memory is full, the operating system monitors which areas of memory are accessed most often, and then fro between shorter latency time groups and longer latency time groups. Move data to.

Special table 2006-500668

In the information processing device, the main storage device has been treated as a storage region of almost a single hierarchy. That is, the memory device used for the main memory has been basically treated as having a single characteristic even though the physical distance, that is, the difference in latency is conscious. The application side generally did not distinguish the characteristics of the memory device. An example of such a technique is found in the system of Patent Document 1 and the NUMA (Non-Uniform Memory Access) system.

In the future, when the performance of the new NV memory gets closer to that of DRAM, etc., it is expected that there will be a need to treat the NV memory as a main storage device rather than as an auxiliary storage device. In this case, when allocating the memory area of the main storage device to the application, it is necessary to ensure the characteristics and performance required by the application. However, it is difficult for the allocation method based on estimation by the operating system like the system of Patent Document 1 to finely meet the request from the application side.

The present invention solves the above problems, in an information processing apparatus in which a NV memory and a volatile memory such as DRAM coexist as a main memory, a memory allocation device capable of ensuring the characteristics and performance of a memory required by an application, a memory allocation method, Also, the purpose is to provide a program.

A memory securing device according to an embodiment of the present invention relates to a volatile main memory device, a non-volatile main memory device, and characteristic information storing a volatile or non-volatile distinction in association with each of the main memory devices. When the storage means and a storage area reservation request designating volatile or non-volatile distinction are input, the characteristic information storage means is searched to identify a main storage device satisfying the designation, and the identified main storage device is specified. And a main memory reserving means for reserving an area.

A memory securing method according to an embodiment of the present invention stores a volatile or non-volatile distinction in a characteristic information storage means in association with each of a volatile or non-volatile main memory device, When a storage area reservation request specifying the distinction is input, the characteristic information storage unit is searched to specify a main storage device that satisfies the specification, and an area is reserved from the specified main storage device.

A program according to an embodiment of the present invention relates to a computer provided with a volatile main memory device and a non-volatile main memory device, and associates each of the main memory devices with a volatile or non-volatile characteristic. When a process of storing in the information storage means and a storage area reservation request designating volatile or non-volatile distinction are input, the characteristic information storage means is searched to identify a main storage device that satisfies the designation, and specify. And a process for reserving an area from the main storage device that has been created.

The memory allocation device according to the present invention ensures the characteristics and performance of the memory required by the application when allocating the memory.

FIG. 1 is a diagram showing a configuration of a memory securing device 10 according to the first exemplary embodiment. FIG. 2 is a diagram showing the configuration of the memory securing device 10 according to the third embodiment. FIG. 3 is a diagram showing a configuration of the device characteristic information entry 30 stored in the characteristic information storage unit 1-7. FIG. 4 is a diagram showing the configuration of the device characteristic information table 40 stored in the characteristic information storage unit 1-7. FIG. 5 is an operation flowchart of the initial setting unit 1-6. FIG. 6 is an operation flowchart of memory reservation by the application program and the main memory reservation unit 1-5. FIG. 7 is a diagram showing the configuration of the device characteristic information entry 30 according to the second embodiment.

<First Embodiment>
<Structure>
FIG. 1 is a diagram showing a configuration of a memory securing device 10 according to the present exemplary embodiment.

The memory securing device 10 is connected to the CPU1-1, the V memory 1-3 connected to the CPU1-1, the NV memory 1-2, the chipset 1-4, and the chipset 1-4 to the CPU1-1. Including NV memory 1-2 connected. Here, the V memory 1-3 is a volatile memory, that is, a memory that cannot hold a value when the power supply is cut off, and is, for example, a DRAM. The NV memory 1-2 is a non-volatile semiconductor memory, that is, a memory that can retain a value even when power supply is cut off, and is, for example, a NAND flash or a phase change memory. The chipset 1-4 is a device that has a built-in controller for the NV memory 1-2 and controls memory access requests from the CPU 1-1. The access performance of each V memory 1-3 and NV memory 1-2, for example, the access latency time does not have to be uniform.

The memory securing device 10 further includes a main memory securing unit 1-5, an initial setting unit 1-6, a characteristic information storage unit 1-7, and an interconnect 1-8. The main memory securing unit 1-5, the initial setting unit 1-6, and the characteristic information storage unit 1-7 are connected to the CPU 1-1, the V memory 1-3, the NV memory 1-2, and the Connected with Chipset 1-4.

The main memory securing unit 1-5, for example, receives a request from an application program executed by the CPU 1-1 and secures an area of the V memory 1-3 or the NV memory 1-2. The initial setting unit 1-6 acquires the characteristic information of the V memory 1-3 and the NV memory 1-2 at the time of initial setting, and registers them in the characteristic information storage unit 1-7.

The main memory securing unit 1-5 and the initial setting unit 1-6 are composed of logic circuits. The main memory securing unit 1-5 or the initial setting unit 1-6 is realized by a program (not shown) stored in the V memory 1-3 or the NV memory 1-2 and executed by the CPU 1-1. May be. In this case, the memory securing device 10 is a computer device, and the CPU 1-1 that executes the program functions as the main memory securing unit 1-5 or the initial setting unit 1-6. In this case, the main memory securing unit 1-5 and the initial setting unit 1-6 are realized, for example, as a part of the operating system or as an extension.

The characteristic information storage unit 1-7 may be a part of the V memory 1-3 and the NV memory 1-2, or may be a separate semiconductor memory device.

FIG. 3 is a diagram showing a configuration of the device characteristic information entry 30 stored in the characteristic information storage unit 1-7. FIG. 4 is a diagram showing the configuration of the device characteristic information table 40 stored in the characteristic information storage unit 1-7. The device characteristic information entry 30 and the device characteristic information table 40 store the characteristic information of the V memories 1-3 and the NV memories 1-2.

According to FIG. 3, the device characteristic information entry 30 has a device ID 3-1 and a measured flag 3-2 corresponding to each of the V memory 1-3 and the NV memory 1-2 (hereinafter abbreviated as a memory device). The volatile flag 3-3 and the table pointer 3-4 are stored.

The device ID 3-1 is a unique value assigned to each memory device and is used as an identifier. The measured flag 3-2 is a flag indicating whether or not the characteristic detection and performance measurement of each memory device have been performed. The volatile flag 3-3 is a flag indicating whether or not each memory device is volatile. The table pointer 3-4 is pointer information to the device characteristic information table 40 that holds the performance characteristic of each memory device.

Here, the measured flag 3-2 stores, for example, a value of "1" when the characteristic detection and performance measurement of the memory device have been executed, and a value of "0" when the performance measurement has not been executed. The measured flag 3-2 is used for determination for characteristic detection and performance measurement when the memory device is initialized, if not yet done. The volatile flag 3-3 stores, for example, a value of "1" for a volatile memory device and a value of "0" for a nonvolatile memory device. The table pointer 3-4 stores a pointer (address) pointing to the device characteristic information table 40 in which the performance measurement information of each memory device is stored.

According to FIG. 4, the device characteristic information table 40 stores the performance value 4-2 for each performance attribute 4-1.

The performance attribute 4-1 stores an access pattern that is a condition for measuring the performance of the memory device. The access pattern is, for example, a combination of discrimination of sequential read, random read, sequential write, or random write and the block size of data transfer. In the figure, sequential read is shown as READ/SEQ, random read is shown as READ/RND, sequential write is shown as WRITE/SEQ, and random write is shown as WRITE/RND. The block sizes are described as 64B and 128B, for example.

The performance value 4-2 stores the performance value of the memory device measured by the corresponding access pattern. In this figure, latency (unit is [ns]) is taken as an example, but throughput or the like may be used.

<Operation>
FIG. 5 is an operation flowchart of the initial setting unit 1-6. The initial setting unit 1-6 is activated when the memory is initialized, for example, when the memory securing device 10 is started up. When activated, the initial setting unit 1-6 sequentially accesses each entry of the device characteristic information entry 30 from the beginning to the end (steps 5-5 and 5-6) and performs the following processing.

The initial setting unit 1-6 reads the measured flag 3-2 of the entry being accessed in step 5-1 and confirms whether or not the performance measurement is completed in step 5-1a. If the measured flag 3-2 is '1' and the performance measurement is completed (Yes in step 5-1a), the performance measurement of the memory device corresponding to the relevant entry is not necessary, so in step 5-6, To access the entry.

When the measured flag 3-2 is '0' and the performance measurement is not completed (No in step 5-1a), the initial setting unit 1-6 sets the volatile flag 3-3 in step 5-2. Set and update the measured flag 3-2.

The initialization unit 1-6 sets the volatile flag 3-3 to '1' when the memory device corresponding to the entry being accessed is explicitly determined to be volatile from the system parameters and the like, and is determined to be nonvolatile. Set the volatile flag 3-3 to '0'.

If the characteristics cannot be obtained explicitly, the initial setting unit 1-6 writes the test data to the memory device, shuts off the power to the memory device and turns it on again, reads the data from the memory device, compares the write data with the read data. And confirm the volatility. The initial setting unit 1-6 determines that the written data and the read data are non-volatile if they match, and the volatile if they do not match.

The initial setting unit 1-6 updates the measured flag 3-2 to "1" indicating that the measurement has been performed in advance in order to continuously measure the performance.

In step 5-3, the initial setting unit 1-6 measures the performance of the memory device corresponding to the entry being accessed. The initial setting unit 1-6 performs performance measurement with a plurality of access patterns including a combination of read/write, sequential access/random access, and block size. The block size is set by the size at which the characteristics of the memory device change or by the access unit of a workload such as a database. The block size is, for example, 64B, 128B, 256B, 512B, 1KB, 4KB, 8KB, 16KB, 32KB, 64KB, 128GB, 256GB, 512KB, 1MB, 4MB.

In step 5-4, the initial setting unit 1-6 stores the performance measurement result of each pattern obtained in step 5-3 in the performance value 4-2 of the device characteristic information table 40. The initial setting unit 1-6 stores the measured value of the pattern in an entry in which the pattern indicated by the performance attribute 4-1 and the pattern on which the measurement is performed match. This makes it possible to obtain a performance value according to the access pattern for each memory device.

The initial setting unit 1-6 performs performance measurement a plurality of times on the same memory device and the same pattern, and sets the worst value, average value, best value, and the like. The initial setting unit 1-6 may store any one of these in the performance value 4-2, or may have each measured value in a separate table.

In step 5-5, the initial setting unit 1-6 confirms whether the accessed device characteristic information entry 30 is the final entry. In other words, the initial setting unit 1-6 confirms whether the performance measurement of all memory devices has been completed. If it is the final entry (Yes in step 5-5), the initialization unit 1-6 ends the process. If it is not the final entry (No in step 5-5), the initial setting unit 1-6 selects the next entry in step 5-6. Proceed to access. For example, in the example of the device characteristic information entry 30 of FIG. 3, when the device ID 3-1 of the accessed record is “1”, the initialization unit 1-6 causes the device ID 3- 1 accesses the record of '2' after that.

As a result, the performance of all memory devices, for which the performance has not been measured, is measured. Further, when a new memory device is added, a new record is added to the device characteristic information table 40. For devices that support hot-plugging, the initialization section 1-6 is activated at the time of initialization when incorporated, and performance measurements are performed.

FIG. 6 is an operation flowchart of memory reservation by the application program and the main memory reservation unit 1-5.

The application program makes a memory allocation request to the main memory securing unit 1-5 to obtain the available memory. At that time, the application program specifies the memory requirements for allocation in step 6-1. The requirements include, for example, performance requirements and required memory size in addition to whether the attributes of the memory device are volatile or nonvolatile. Performance requirements are specified for each type of access pattern. The performance requirements are, for example, a sequential read with a block size of 128B, an access latency of less than 500 ns, a sequential write with a block size of 128B, an access latency of less than 1 μs, and an access latency of any other access pattern.

In response to the memory allocation request from the application program, the main memory reserving unit 1-5 scans the device characteristic information entry 30 and the device characteristic information table 40 in step 6-2, and there is a vacancy in the memory device satisfying the requirements. Check if.

Specifically, the main memory reserving unit 1-5 first searches for the device characteristic information entry 30 in which the volatile and non-volatile attributes specified by the application program match the volatile flag 3-3. If found, the main memory reserving unit 1-5 scans the performance attribute 4-1 of the device characteristic information table 40 pointed to by the table pointer 3-4, and makes an entry that matches the type of access pattern specified by the application program. Refer to performance value 4-2 of. If the value is within the range that satisfies the performance requirement of the application program, the main memory reserving unit 1-5 reserves an area from the memory device corresponding to the corresponding device ID 3-1 and allocates it to the application program. At this time, the main memory reserving unit 1-5 determines whether or not reserving is possible depending on whether or not there is a free space in the corresponding memory device.

When the memory allocation succeeds, the main memory reserving unit 1-5 notifies the application program of the reserved memory address, for example. The main memory securing unit 1-5 may map the secured memory to a virtual address designated by the application program.

The main memory reserving unit 1-5 indexes all the device characteristic information tables 40, and returns an error code to the application program when there is no memory device entry satisfying the requirements of the application program.

The application program refers to the end code of the memory allocation request in step 6-3, and if there is an error (Yes in step 6-3), abnormally ends the memory allocation. At this time, the application program may make another memory allocation request with different requirements.

If the exit code is not an error (No in Step 6-3), memory allocation has been performed normally. Therefore, the application program can access the memory within the requested memory size range from the returned memory address. Step 6-4 shows the part of access to the allocated memory device by the application program.

When the processing in the application program is completed (Yes in step 6-3a) and the corresponding memory space can be released, the application program sends a memory deallocation request to the main memory securing unit 1-5 in step 6-5. To do.

The main memory reserving unit 1-5 releases the memory area in step 6-6 according to the memory deallocation request from the application program.

<Effect>
The memory securing device 10 according to the present embodiment can ensure the characteristics and performance of the memory required by the application program when allocating the memory. The reason is that the main memory reserving unit 1-5 accepts the requirements specified by the application program for the memory allocation request and reserves a memory area that meets the requirements. The requirements include, for example, performance requirements and required memory size in addition to whether the attributes of the memory device are volatile or nonvolatile.

As a result, the application program that uses the memory securing device 10 according to the present embodiment unifies the memory devices having different characteristics (volatile, non-volatile, and performance characteristics) as the main storage device, not as the auxiliary storage device. Available.

<Second Embodiment>
<Structure and operation>
FIG. 7 is a diagram showing the configuration of the device characteristic information entry 30 according to the present embodiment. The device characteristic information entry 30 according to the present embodiment is added with a lifetime 3-5 as compared with the device characteristic information entry 30 according to the first embodiment.

The limited life 3-5 stores the life index of the memory device corresponding to the entry. The life index is, for example, 0 for semi-permanent (no life), 1 for high endurance products, 2 for middle endurance products, and 3 for low endurance products. For example, DRAM is semi-permanent, phase change memory is high endurance product, SLC (Single Level Cell) NAND flash is middle endurance product, and MLC (Multi Level Cell) NAND flash is low endurance product.

The main memory reserving unit 1-5 of the present embodiment, as a requirement specified by the application program for the memory allocation request, for example, whether the attribute of the memory device is volatile or non-volatile, the performance requirement, the required memory size, in addition to , Accept life index. As a result, in step 6-2 of FIG. 6, the main memory reserving unit 1-5 determines that the volatile and non-volatile attributes designated by the application program match the volatile flag 3-3, and the application program designates them. The device characteristic information entry 30 whose searched life index matches the life index of the existing life 3-5 is searched for. Other than that, the main memory securing unit 1-5 operates in the same manner as in the first embodiment.

<Effect>
The application program can select the device in consideration of the life of the device by the memory allocation request. This allows workloads with a high write ratio to avoid the use of end-of-life devices.

<Third Embodiment>
FIG. 2 is a diagram showing the configuration of the memory securing device 10 according to the present embodiment. The memory securing device 10 includes a V memory 1-3 that is a volatile main memory device, an NV memory 1-2 that is a non-volatile main memory device, a characteristic information storage unit 1-7, and a main memory securing unit 1. -5 and.

The characteristic information storage unit 1-7 stores volatile or non-volatile distinction in association with each of the main storage devices. When the storage reservation request specifying the distinction between volatile and non-volatile is input, the main memory reservation unit 1-5 searches the characteristic information storage unit 1-7 to identify the main storage device that satisfies the specification. Reserve an area from the specified main memory.

The memory reservation request may be issued by an application program executed by CUP1-1 (not shown), or by a dedicated image processing chip or the like.

The memory securing device 10 according to the present embodiment can ensure the characteristics and performance of the memory required by the application program when allocating the memory. The reason is that the main memory reserving unit 1-5 accepts the requirements specified by the application program for the memory allocation request and reserves a memory area that meets the requirements. The requirements include, for example, performance requirements and required memory size in addition to whether the attributes of the memory device are volatile or nonvolatile.

As a result, the application program that uses the memory securing device 10 according to the present embodiment unifies the memory devices having different characteristics (volatile, non-volatile, and performance characteristics) as the main storage device, not as the auxiliary storage device. Available.

Although the present invention has been described with reference to the exemplary embodiments, the present invention is not limited to the above exemplary embodiments. Various modifications that can be understood by those skilled in the art can be made to the configuration and details of the present invention within the scope of the present invention.

1-1 CPU
1-2 NV memory
1-3 V memory
1-4 chipset
1-5 Main memory securing unit
1-6 Initial setting section
1-7 Characteristic information storage
1-8 interconnect
3-1 Device ID
3-2 Measured flag
3-3 Volatile flag
3-4 Table pointer
3-5 Life
4-1 Performance attributes
4-2 Performance value
10 Memory securing device
30 Device characteristic information entry
40 Device characteristic information table

Claims (12)

A volatile main memory device,
A non-volatile main memory device,
Storing an attribute of each of the main storage device indicating whether the non-volatile is a volatilization properties, in association with each of the main memory, further distinguish between the read / write, and distinction between random access / sequential access , A block size, and a characteristic information storage unit that stores access performance for each access pattern that is a combination of
With the access pattern and the combination of the access performance and the attributes and, storage ensures request specifying requirements including is input, the characteristic information by searching the storage unit, a main storage device satisfying the requirements identified, a main storage securing section to secure the area from the main memory specified, Ru provided with,
Memory allocation system. A volatile main memory device,
A non-volatile main memory device,
Storing an attribute of each of the main storage device indicating whether the non-volatile is a volatilization properties, in association with the main memory, furthermore, a characteristic information storage means for storing the length of life,
When a storage reservation request specifying a requirement including the attribute and the life span is input, the characteristic information storage unit is searched to identify a main storage device that satisfies the requirement, and the identified main storage is specified. a main storage securing means for securing a region from the device, Ru provided with,
Memory allocation system. The characteristic information storage means further stores access performance in association with a main storage device,
It said main storage securing means, when the access performance the storage allocation request specifying the requirements further comprising a is input, searches the characteristic information storage unit, specifies the main storage device that meets the requirements, The memory allocation device according to claim 2, wherein an area is secured from the identified main storage device. Said characteristic information storing means, a main storage device in association further stores distinction between read / write, distinguish the random access / sequential access, and the block size, the access performance for each access pattern is a combination of ,
It said main storage securing means, said when the storage ownership request combinations specifying the requirements further comprising a the access pattern and the access performance is input, searches the characteristic information storage means, comply with the requirement 4. The memory allocation device according to claim 3, wherein a main storage device is specified and an area is secured from the specified main storage device. 5. The initial setting means for accessing the main storage device to determine whether each of the main storage devices is volatile or non-volatile, and registering the determination result in the characteristic information storage means, further. 2. The memory allocation device according to any one of 1. Computer
Each of the volatile or non-volatile main memory stores an attribute indicating whether it is volatile or non-volatile in the characteristic information storage means,
In association with the main storage device, access characteristics are further stored in the characteristic information storage means for each access pattern which is a combination of read/write distinction, random access/sequential access distinction, and block size,
With the access pattern and the combination of the access performance and the attributes and, storage ensures request specifying requirements including is input, the characteristic information by searching the storage unit, a main storage device satisfying the requirements Specify and reserve an area from the specified main memory,
Memory allocation method. Computer
Each of the volatile or non-volatile main memory stores an attribute indicating whether it is volatile or non-volatile in the characteristic information storage means,
In association with the main storage device, further stores the length of life in the characteristic information storage means,
When a storage reservation request specifying a requirement including the attribute and the life span is input, the characteristic information storage unit is searched to identify a main storage device that satisfies the requirement, and the identified main storage device is identified. It secures an area from the storage device,
Memory allocation method. Computer
In the process of storing in the characteristic information storage means , the access performance is further stored in the characteristic information storage means in association with the main storage device,
In the process of securing the area, said the access performance the storage allocation request specifying the requirements further comprising a is input, the characteristic information by searching the storage unit, specifies the main storage to meet the requirements The memory allocation method according to claim 7, wherein an area is secured from the identified main storage device. Computer
In the process of storing the said characteristic information storage means, in association with the main memory, furthermore, the access and distinction of the read / write, distinguish the random access / sequential access for each access pattern is a combination of the block size, The performance is stored in the characteristic information storage means,
In the process of securing the area, the when the storage ownership request combinations specifying the requirements further comprising a the access pattern and the access performance is input, searches the characteristic information storing means, with the requirement 9. The memory allocation method according to claim 8 , wherein a main storage device to be filled is specified and an area is secured from the specified main storage device. Computer
10. The memory allocation according to claim 6, wherein each of the main storage devices is volatile or non-volatile and is discriminated by accessing the main storage device and the discrimination result is registered in the characteristic information storage means. Method. In a computer having a volatile main memory and a non-volatile main memory,
A process of storing in the characteristic information storage means an attribute indicating whether each of the main storage devices is volatile or non-volatile;
A process of storing access performance in the characteristic information storage means for each access pattern that is a combination of read/write distinction, random access/sequential access distinction, and block size in association with the main storage device. ,
With the access pattern and the combination of the access performance and the attributes and, storage ensures request specifying requirements including is input, the characteristic information by searching the storage unit, a main storage device satisfying the requirements identified, Help program is executed and a process for reserving an area from the main memory specified. A computer having a volatile main memory and a non-volatile main memory,
A process of storing in the characteristic information storage means an attribute indicating whether each of the main storage devices is volatile or non-volatile;
A process of storing the length of life in the characteristic information storage means in association with the main storage device;
When a storage reservation request specifying a requirement including the attribute and the life span is input, the characteristic information storage unit is searched to identify a main storage device that satisfies the requirement , and the identified main storage is specified. Help program is executed and a process for reserving an area from the device.

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