JP6593522B2 - Electro-optical device, electronic apparatus, and method of manufacturing electro-optical device - Google Patents

Description

  The present invention relates to an electro-optical device in which a transistor is provided on one side of a substrate, an electronic apparatus, and a method for manufacturing the electro-optical device.

  In an electro-optical device (liquid crystal device) used as a light valve of a projection display device, a semiconductor layer is provided between a substrate and a pixel electrode, and a transistor is configured using the semiconductor layer. In such an electro-optical device, light from a light source or light emitted from the electro-optical device is reflected on the semiconductor layer by an optical element or the like and is incident on the electro-optical device again. Leakage current is generated, causing malfunction of the transistor. Therefore, a semiconductor layer is provided so as to overlap with the light-shielding wiring provided between the semiconductor layer and the pixel electrode in plan view, and a light-shielding layer overlapping with the semiconductor layer in plan view is provided between the semiconductor layer and the substrate. A structure has been proposed. On the other hand, an air layer is provided on both sides in the width direction of the semiconductor layer between the non-opening region that overlaps with the light-shielding wiring in a plan view and the opening region surrounded by the light-shielding wiring, and the interface between the air layer and the insulating film A technique for suppressing the incidence of light from the opening region to the semiconductor layer has been proposed using reflection on the surface. (See Patent Document 1).

JP 2012-208449 A

  However, in the configuration described in FIG. 4 of Patent Document 1, an air layer (insulating portion 411) is provided only in a region in the width direction of the channel portion 308 of the transistor between the non-opening region and the opening region. Therefore, from the length direction of the semiconductor layer of the transistor, the direction inclined obliquely with respect to the length direction, the width direction excluding the channel portion of the semiconductor layer, and the direction inclined obliquely with respect to the width direction excluding the channel portion There is a problem that light traveling toward the semiconductor layer cannot be blocked by the air layer. Therefore, with the configuration described in Patent Document 1, it is difficult to sufficiently suppress the occurrence of light leakage current. Note that FIG. 10 of Patent Document 1 has a configuration in which the channel portion 308 of the transistor is surrounded from four directions in a plan view by an insulating portion 611 disposed in a layer on the light incident side of the layer where the channel portion is disposed. In such a configuration, the length of the semiconductor layer of the transistor, the direction inclined obliquely with respect to the length direction, the width direction, and the direction inclined obliquely with respect to the width direction are directed toward the semiconductor layer. Therefore, it is difficult to sufficiently prevent the occurrence of light leakage current.

  In view of the above problems, an object of the present invention relates to an electro-optical device, an electronic apparatus, and a method of manufacturing an electro-optical device that can effectively suppress the incidence of light on a semiconductor layer of a transistor. .

  In order to solve the above problem, an aspect of the electro-optical device according to the present invention is provided between a substrate, a pixel electrode provided on one side of the substrate, and the substrate and the pixel electrode. A first light-shielding layer extending along an edge of the pixel electrode in a plan view; and a semiconductor layer extending between the substrate and the first light-shielding layer and overlapping the first light-shielding layer in a plan view. A transistor, a second light-shielding layer provided between the substrate and the semiconductor layer and overlapping the semiconductor layer in plan view, and an insulating layer provided between the substrate and the pixel electrode. And a cavity provided on both sides in the width direction of the semiconductor layer and on both sides in the length direction of the semiconductor layer. In the present invention, “plan view” means a state seen from the thickness direction which is a direction perpendicular to the substrate.

  In the present invention, since the semiconductor layer overlaps the first light shielding layer and the second light shielding layer in plan view, the light traveling from the pixel electrode side and the substrate side toward the semiconductor layer is transmitted by the first light shielding layer and the second light shielding layer. Can be blocked. In addition, inside the insulating layer, cavities are provided on both sides in the width direction of the semiconductor layer and on both sides in the length direction of the semiconductor layer. For this reason, it is possible to block light that is about to enter the semiconductor layer from the width direction of the semiconductor layer by using reflection at the interface between the cavity and the insulating layer, and to determine the length direction and length of the semiconductor layer. Light traveling toward the semiconductor layer from a direction inclined obliquely with respect to the direction can be blocked using reflection at the interface between the cavity and the insulating layer. Therefore, since the incidence of light on the semiconductor layer can be more effectively suppressed, the generation of light leakage current can be more effectively suppressed in the transistor.

  In the present invention, it is possible to adopt a mode in which the cavity surrounds the semiconductor layer in a plan view. According to this aspect, the incidence of light on the semiconductor layer can be more effectively suppressed.

  In the present invention, an embodiment in which the inside of the cavity is a vacuum can be employed. According to this aspect, since the cavity is closed using a semiconductor process in a vacuum, it is easier to form the cavity as compared with the case where the inside of the cavity is an air layer. In the present invention, “vacuum” means a spatial state where the pressure is lower than atmospheric pressure.

  In the present invention, the cavity is provided from a position closer to the substrate than the semiconductor layer to a position closer to the pixel electrode than the semiconductor layer in a thickness direction that is a direction perpendicular to the substrate. Can be adopted. According to this aspect, the incidence of light on the semiconductor layer can be more effectively suppressed. In this case, it is possible to adopt a mode in which the semiconductor layer is located behind at least one of the light shielding layer and the cavity when viewed from any direction from the substrate side. According to this aspect, even when the light emitted from the electro-optical device is reflected by the optical element or the like and the return light incident again on the electro-optical device tries to travel from the substrate side toward the semiconductor layer, the light is emitted. Can be more effectively shielded by reflection at the interface between the cavity and the insulating layer or a light shielding layer.

  In the present invention, the cavity is provided from the gate electrode provided on the pixel electrode side to the pixel electrode side from the semiconductor layer of the transistor in the thickness direction, and the gate electrode includes the first electrode. It is possible to adopt a mode in which the scanning line formed as one of the light shielding layer and the second light shielding layer is electrically connected to the cavity from the pixel electrode side. According to this aspect, even when light tries to travel from the pixel electrode side toward the semiconductor layer, the light can be efficiently blocked by reflection at the interface between the cavity and the insulating layer. In this case, when the gate electrode itself is a part of the scanning line, the scanning line is interrupted in the cavity, but the scanning line provided separately from the gate electrode is electrically connected to the gate electrode from the pixel electrode side to the cavity. If it is the aspect which is connected, it can avoid that a scanning line interrupts with a cavity.

  In the present invention, it is possible to adopt a mode in which the first end portion, which is the end portion on the pixel electrode side of the cavity, includes a first bent portion bent inward where the semiconductor layer is located in a plan view. . According to this aspect, even when light tries to travel from the pixel electrode side toward the semiconductor layer, the light can be blocked by reflection at the interface between the first bent portion of the cavity and the insulating layer.

  In the present invention, the second end portion, which is the end portion of the cavity on the substrate side, includes a second bent portion that is bent outward from the side opposite to the side where the semiconductor layer is located in plan view. Can be adopted. According to this aspect, even when the light emitted from the electro-optical device is reflected by the optical element or the like and the return light incident again on the electro-optical device tries to travel from the substrate side toward the semiconductor layer, the light is emitted. Can be blocked by reflection at the interface between the second bent portion of the cavity and the insulating layer or by a light shielding layer.

  In the present invention, the insulating layer includes an outer wall forming film that is provided so as to cover the semiconductor layer and forms a wall surface of the cavity opposite to the semiconductor layer, and the outer wall forming film is formed on the semiconductor layer. On the other hand, it is possible to adopt a mode in which an opening communicating with the cavity is provided in a portion overlapping on the pixel electrode side.

  In the present invention, it is possible to adopt an aspect in which the insulating layer includes an inner wall forming film that is provided so as to cover the semiconductor layer and forms a wall surface of the cavity on the semiconductor layer side.

An electro-optical device according to a reference example of the invention includes a substrate, a pixel electrode provided on one surface side of the substrate, and provided between the substrate and the pixel electrode. A transistor including a first light-shielding layer extending along the substrate, a semiconductor layer extending between the substrate and the first light-shielding layer, and overlapping the first light-shielding layer in plan view, the substrate, and the substrate A second light-shielding layer provided between the semiconductor layer and overlapping the semiconductor layer in plan view; and an insulating layer provided between the substrate and the pixel electrode. The semiconductor layer and the insulating layer are separated on both sides in the width direction of the layer and on both sides in the length direction of the semiconductor layer.

In the electro-optical device according to the reference example of the invention, since the semiconductor layer overlaps the first light-shielding layer and the second light-shielding layer in plan view, the light traveling from the pixel electrode side and the substrate side toward the semiconductor layer is first. It can be blocked by the light shielding layer and the second light shielding layer. Further, in plan view, the semiconductor layer and the insulating layer are separated on both sides in the width direction of the semiconductor layer and on both sides in the length direction of the semiconductor layer. For this reason, it is possible to block light that is about to enter the semiconductor layer from the width direction of the semiconductor layer by using reflection at the interface of the insulating layer, and also to the length direction and the length direction of the semiconductor layer. Thus, light traveling toward the semiconductor layer from a slanting direction can be blocked using reflection at the interface of the insulating layer. Therefore, since the incidence of light on the semiconductor layer can be more effectively suppressed, the generation of light leakage current can be more effectively suppressed in the transistor.

  The electro-optical device to which the present invention is applied is used in various electronic apparatuses. In the present invention, when the electronic apparatus is a projection display device, the projection display device includes a light source unit that emits light supplied to the electro-optical device, and projection optics that projects light modulated by the electro-optical device. A system is provided.

  The present invention provides a substrate, a pixel electrode provided on one side of the substrate, a first electrode provided between the substrate and the pixel electrode, and extending along an edge of the pixel electrode in plan view. A light-shielding layer; a transistor including a semiconductor layer extending between the substrate and the first light-shielding layer and overlapping the first light-shielding layer in plan view; and provided between the substrate and the semiconductor layer. In the method of manufacturing an electro-optical device, the method includes: a second light-shielding layer that overlaps the semiconductor layer in plan view; and an insulating layer provided between the substrate and the pixel electrode. After forming a light shielding layer, the semiconductor layer, and a part of the insulating layer, a part of the insulating layer is etched to form a wall surface that surrounds the semiconductor layer and covers the pixel electrode side of the semiconductor layer. A step of forming a sacrificial film so as to cover the wall surface; A step, a third step of forming another part of the insulating layer different from the part of the insulating layer so as to cover the sacrificial film, and an opening in a portion overlapping with the other part of the sacrificial film in the plan view And a fifth step of forming cavities on both sides in the width direction of the semiconductor layer and on both sides in the length direction of the semiconductor layer in plan view by removing the sacrificial film from the opening. It is characterized by having.

  In the present invention, after forming a sacrificial film on the wall surface formed on the insulating film so as to cover the periphery of the semiconductor layer and the pixel electrode side of the semiconductor layer, another insulating film covering the sacrificial film is formed, and the sacrificial film is formed from the opening. Are removed by etching to form a cavity. For this reason, it is possible to easily form cavities on both sides in the width direction of the semiconductor layer and on both sides in the length direction of the semiconductor layer in plan view. Therefore, light that is about to enter the semiconductor layer from the width direction of the semiconductor layer can be blocked using reflection at the interface between the cavity and the insulating layer, and the length direction and length direction of the semiconductor layer can be blocked. The light traveling toward the semiconductor layer from the direction inclined obliquely with respect to can be blocked using reflection at the interface between the cavity and the insulating layer. Therefore, since the incidence of light on the semiconductor layer can be further suppressed, the generation of light leakage current can be further suppressed in the transistor.

1 is a plan view of an electro-optical device to which the present invention is applied. FIG. 2 is a cross-sectional view of the electro-optical device shown in FIG. FIG. 2 is a plan view of a plurality of adjacent pixels in the electro-optical device shown in FIG. 1. FIG. 4 is a cross-sectional view of the electro-optical device shown in FIG. 3 taken along the line FF ′. GG 'sectional drawing of the electro-optical apparatus shown in FIG. The top view which shows the light-shielding structure of the semiconductor layer shown in FIG. X1-X1 'sectional drawing when the light-shielding structure shown in FIG. 6 is cut | disconnected in the width direction of a semiconductor layer. FIG. 7 is a cross-sectional view taken along line Y1-Y1 ′ when the light shielding structure shown in FIG. 6 is cut in the length direction of the semiconductor layer. FIG. 3 is a process cross-sectional view illustrating a method for manufacturing the electro-optical device illustrated in FIG. 1. Process sectional drawing which shows the process after the process shown in FIG. 1 is a schematic configuration diagram of a projection display device (electronic device) using an electro-optical device to which the present invention is applied.

  Embodiments of the present invention will be described with reference to the drawings. In the drawings to be referred to in the following description, the scales are different for each layer and each member so that each layer and each member have a size that can be recognized on the drawing. In the following description, when describing each layer formed on the first substrate 10, the upper layer side or the surface side is the side opposite to the side where the first substrate 10 is located (the side where the second substrate 20 is located). The lower layer side means the side on which the first substrate 10 is located.

(Configuration of electro-optical device)
FIG. 1 is a plan view of an electro-optical device 100 to which the present invention is applied. FIG. 2 is a cross-sectional view of the electro-optical device 100 shown in FIG. As shown in FIGS. 1 and 2, in the electro-optical device 100, the first substrate 10 and the second substrate 20 are bonded to each other with a sealant 107 through a predetermined gap, and the first substrate 10 and the second substrate are combined. 20 is facing. The sealing material 107 is provided in a frame shape along the outer edge of the second substrate 20, and an electro-optic such as a liquid crystal layer is formed in a region surrounded by the sealing material 107 between the first substrate 10 and the second substrate 20. Layer 80 is disposed. Accordingly, the electro-optical device 100 is configured as a liquid crystal device. The sealing material 107 is a photo-curing adhesive or a photo-curing and thermo-curing adhesive, such as glass fiber or glass beads for setting the distance between both substrates to a predetermined value. Gap material is blended. Both of the first substrate 10 and the second substrate 20 are quadrangular, and a display region 10 a is provided as a quadrangular region in the approximate center of the electro-optical device 100. Corresponding to this shape, the sealing material 107 is also provided in a substantially square shape, and a rectangular frame-shaped peripheral region 10b is provided between the inner peripheral edge of the sealing material 107 and the outer peripheral edge of the display region 10a.

  The first substrate 10 is a translucent substrate such as a quartz substrate or a glass substrate, and on the one surface 10 s side of the first substrate 10 on the second substrate 20 side, on the outside of the display region 10 a, A data line driving circuit 101 and a plurality of terminals 102 are formed along one side, and a scanning line driving circuit 104 is formed along another side adjacent to the one side. A flexible wiring substrate (not shown) is connected to the terminal 102, and various potentials and various signals are input to the first substrate 10 through the flexible wiring substrate.

  On one surface 10 s of the first substrate 10, the display region 10 a is electrically connected to each of a plurality of translucent pixel electrodes 9 a made of an ITO (Indium Tin Oxide) film and the like and a plurality of pixel electrodes 9 a. Transistors (not shown in FIG. 2) are formed in a matrix. A first alignment film 18 is formed on the second substrate 20 side with respect to the pixel electrode 9 a, and the pixel electrode 9 a is covered with the first alignment film 18.

  The second substrate 20 is a translucent substrate such as a quartz substrate or a glass substrate. A translucent common electrode 21 made of an ITO film or the like is formed on one surface 20 s of the second substrate 20 facing the first substrate 10, and the first substrate 10 side of the common electrode 21 is formed on the first substrate 10 side. A second alignment film 28 is formed. The common electrode 21 is formed on substantially the entire surface of the second substrate 20 and is covered with the second alignment film 28. A light-shielding light-shielding layer 27 made of resin, metal, or metal compound is formed between the one surface 20 s of the second substrate 20 and the common electrode 21, and the light-transmitting property is provided between the light-shielding layer 27 and the common electrode 21. The protective layer 26 is formed. The light shielding layer 27 is formed, for example, as a frame-shaped parting line 27a extending along the outer peripheral edge of the display region 10a. The light shielding layer 27 is also formed as a light shielding layer 27b (black matrix) in a region overlapping in plan view with a region sandwiched between adjacent pixel electrodes 9a. Of the peripheral region 10b of the first substrate 10, a dummy pixel electrode 9b formed simultaneously with the pixel electrode 9a is formed in the dummy pixel region 10c overlapping the parting line 27a in plan view.

The first alignment film 18 and the second alignment film 28 are inorganic alignment films (vertical alignment films) made of oblique vapor deposition films such as SiO _x (x <2), SiO ₂ , TiO ₂ , MgO, Al ₂ O _3. The liquid crystal molecules having negative dielectric anisotropy used for the electro-optic layer 80 are tilted and aligned. For this reason, the liquid crystal molecules form a predetermined angle with respect to the first substrate 10 and the second substrate 20. In this manner, the electro-optical device 100 is configured as a VA (Vertical Alignment) mode liquid crystal device.

  The first substrate 10 has an inter-substrate conduction electrode for providing electrical continuity between the first substrate 10 and the second substrate 20 in a region overlapping the corner portion of the second substrate 20 outside the sealing material 107. 109 is formed. The inter-substrate conducting electrode 109 is provided with an inter-substrate conducting material 109 a containing conductive particles, and the common electrode 21 of the second substrate 20 is interposed between the inter-substrate conducting material 109 a and the inter-substrate conducting electrode 109. And electrically connected to the first substrate 10 side. For this reason, a common potential is applied to the common electrode 21 from the first substrate 10 side.

  In the electro-optical device 100, the pixel electrode 9a and the common electrode 21 are formed of a light-transmitting conductive film such as an ITO film, and the electro-optical device 100 is configured as a transmissive liquid crystal device. In the electro-optical device 100, the light incident on the electro-optical layer 80 from one of the first substrate 10 and the second substrate 20 is modulated while being transmitted through the other substrate and emitted. Is displayed. In the present embodiment, as indicated by an arrow L, the light incident from the second substrate 20 is modulated for each pixel by the electro-optic layer 80 while being transmitted through the first substrate 10 and emitted to display an image.

(Specific pixel configuration)
FIG. 3 is a plan view of a plurality of adjacent pixels in the electro-optical device 100 shown in FIG. 4 is a cross-sectional view taken along line FF ′ of the electro-optical device 100 shown in FIG. 3, and is a cross-sectional view taken along the data line 6a. 5 is a cross-sectional view taken along the line GG ′ of the electro-optical device 100 shown in FIG. 3, and is a cross-sectional view taken along the scanning line 3a. FIG. 5 shows a state where the pixel electrode 9a is cut at a position passing through the contact hole 17d.

  As shown in FIG. 3, a pixel electrode 9a is formed on each of a plurality of pixels on the surface of the first substrate 10 facing the second substrate 20, and data is arranged along the end of the pixel electrode 9a. The line 6a, the scanning line 3a, the first capacitance line 51a, the second capacitance line 52a, and the like extend. For example, the scanning line 3a extends in the first direction X in the inter-pixel region, and the data line 6a extends in the second direction Y in the inter-pixel region. A transistor 30 is formed corresponding to the intersection of the data line 6a and the scanning line 3a. The first capacitor line 51a extends in the first direction X so as to overlap the scanning line 3a in plan view, and the second capacitor line 52a extends in the second direction Y so as to overlap the data line 6a in plan view. is doing.

  The scanning line 3a, the data line 6a, the first capacitor line 51a, and the second capacitor line 52a are light-shielding wirings made of a light-shielding material, and a plurality of light-shielding layers are configured by the light-shielding wirings. . Therefore, the region where the scanning line 3a, the data line 6a, the first capacitance line 51a, and the second capacitance line 52a are formed is a light shielding region 108a through which light does not pass, and the region surrounded by the light shielding region 108a Is an opening region 108b (light-transmitting region) through which light is transmitted.

  4 and 5, the electro-optical device 100 includes a first substrate 10, a pixel electrode 9a provided on the one surface 10s side of the first substrate 10, and a first substrate 10 and a pixel electrode 9a. A plurality of light-shielding layers extending along the edge of the pixel electrode 9a in a plan view as viewed from the thickness direction which is a direction perpendicular to the first substrate 10 between The plurality of light shielding layers are the scanning line 3a, the data line 6a, the first capacitance line 51a, the second capacitance line 52a, and the like.

  The electro-optical device 100 includes a transistor 30 including a semiconductor layer 1a that extends between the first substrate 10 and the plurality of light shielding layers and overlaps at least one of the plurality of light shielding layers in plan view. A second light-shielding layer 8a that overlaps the semiconductor layer 1a in plan view between the first substrate 10 and the semiconductor layer 1a, and a plurality of interlayer insulating films provided between the first substrate 10 and the pixel electrode 9a. The semiconductor layer 1a and the first light shielding layer are formed between the plurality of interlayer insulating films.

  The transistor 30 is a thin film transistor, and includes a semiconductor layer 1a provided between the first substrate 10 and the pixel electrode 9a, a gate electrode 31a provided on the pixel electrode 9a side with respect to the semiconductor layer 1a, and a pixel electrode A source electrode 51s provided between 9a and the semiconductor layer 1a, and a drain electrode 51d provided between the pixel electrode 9a and the semiconductor layer 1a.

  As described below, the insulating layer 110 includes a gate insulating layer 2, a first dielectric layer 42a, a second dielectric layer 72a, and the like in addition to a plurality of interlayer insulating films. First, an interlayer insulating film 19 is formed between the second light shielding layer 8a and the semiconductor layer 1a, and an interlayer insulating film 11 is formed between the gate electrode 31a and the scanning line 3a. An interlayer insulating film 12 is formed between the scanning line 3a and the first capacitor line 51a, and an interlayer insulating film 13 is formed between the first capacitor line 51a and the first capacitor electrode 41a. An interlayer insulating film 14 is formed between the second capacitor electrode 43a and the data line 6a, and an interlayer insulating film 15 is formed between the data line 6a and the second capacitor line 52a. An interlayer insulating film 16 is formed between the second capacitor line 52a and the third capacitor electrode 71a, and an interlayer insulating film 17 is formed between the fourth capacitor electrode 73a and the pixel electrode 9a. The interlayer insulating films 19 and 11 to 17 are all translucent insulating films made of a silicon oxide film or the like.

(Detailed pixel configuration)
A second light shielding layer 8a is formed on one surface 10s of the first substrate 10, and the second light shielding layer 8a is made of a light shielding conductive film such as a metal silicide film, a metal film, or a metal compound film. The semiconductor layer 1a of the transistor 30 is formed on the surface of the interlayer insulating film 11 on the pixel electrode 9a side, and the semiconductor layer 1a is covered with the gate insulating layer 2 from the pixel electrode 9a side. The semiconductor layer 1a is composed of a polysilicon film (polycrystalline silicon film) or the like, and extends along the data line 6a. The gate insulating layer 2 has a two-layer structure of a first gate insulating layer made of a silicon oxide film obtained by thermally oxidizing the semiconductor layer 1a and a second gate insulating layer made of a silicon oxide film formed by a low pressure CVD method or the like. .

  A gate electrode 31 a is formed on the surface of the gate insulating layer 2 on the pixel electrode 9 a side, and the scanning line 3 a extends in the first direction X between the interlayer insulating film 11 and the interlayer insulating film 12, The insulating film 11 is electrically connected to the gate electrode 31a through the contact hole 11a. In the interlayer insulating film 19 and the interlayer insulating film 11, a contact hole 11b for electrically connecting the scanning line 3a and the second light shielding layer 8a is formed. Accordingly, the second light shielding layer 8a functions as a back gate.

  The gate electrode 31a overlaps the central portion in the length direction of the semiconductor layer 1a. The semiconductor layer 1a includes a channel region 1i facing the gate electrode 31a via the gate insulating layer 2, and includes a source region 1b and a drain region 1c on both sides of the channel region 1i. The transistor 30 has an LDD structure. Accordingly, each of the source region 1b and the drain region 1c includes the low concentration regions 1d and 1e on both sides of the channel region 1i, and a high concentration is applied to a region adjacent to the low concentration regions 1d and 1e on the opposite side to the channel region 1i. Regions 1f and 1g are provided. The gate electrode 31a is made of a light-shielding conductive film such as a conductive polysilicon film, a metal silicide film, a metal film, or a metal compound film. The scanning line 3a is made of a light-shielding conductive film such as a metal silicide film, a metal film, or a metal compound film. In the present embodiment, the gate electrode 31a and the scanning line 3a include, for example, a multilayer structure of Ti (titanium) layer / TiN (titanium nitride) layer / Al (aluminum) layer / TiN (titanium nitride) layer, TiN layer / Al It has a multilayer structure of layer / TiN layer.

  On the surface of the interlayer insulating film 12 on the pixel electrode 9a side, a light-shielding first capacitor line 51a that overlaps the gate electrode 31a in plan view is formed, and a common potential is applied to the first capacitor line 51a. . The first capacitance line 51a extends in the first direction X and overlaps the scanning line 3a in plan view. On the surface of the interlayer insulating film 12 on the pixel electrode 9a side, a source electrode 51s and a drain electrode 51d are formed at positions spaced in the second direction Y with respect to the first capacitance line 51a. The source electrode 51s and the drain electrode 51d is configured by the same conductive layer as the first capacitor line 51a. The source electrode 51s and the drain electrode 51d are electrically connected to the source region 1b and the drain region 1c through contact holes 12s and 12d that penetrate the interlayer insulating film 12, respectively. The first capacitor line 51a, the source electrode 51s, and the drain electrode 51d are made of a light-shielding conductive film such as a metal silicide film, a metal film, or a metal compound film. In the present embodiment, the first capacitor line 51a, the source electrode 51s, and the drain electrode 51d have, for example, a multilayer structure of Ti (titanium) layer / TiN (titanium nitride) layer / Al (aluminum) layer / TiN (titanium nitride) layer. Alternatively, it has a multilayer structure of TiN layer / Al layer / TiN layer.

  The interlayer insulating film 13 is formed with a first recess 44a that overlaps the first capacitor line 51a in plan view. Further, in a region overlapping with the first recess 44a, there is a light-shielding first capacitor electrode 41a extending from the bottom of the first recess 44a to the surface of the interlayer insulating film 13 on the pixel electrode 9a side, and the first capacitor electrode 41a. A light-shielding second capacitance electrode 43a overlapping from the pixel electrode 9a side is formed. Here, the second capacitor electrode 43a is electrically connected to the drain electrode 51d and the pixel electrode 9a. The first capacitor electrode 41a and the second capacitor electrode 43a are made of a conductive film such as a conductive polysilicon film, a metal silicide film, a metal film, or a metal compound film. In the present embodiment, the first capacitor electrode 41a and the second capacitor electrode 43a are made of a TiN (titanium nitride) layer or the like.

  The first capacitor electrode 41a is electrically connected to the first capacitor line 51a at the bottom of the first recess 44a. More specifically, a contact hole 13a penetrating the interlayer insulating film 13 is formed at the bottom of the first recess 44a, and the first capacitor electrode 41a is connected to the first capacitor line 51a via the contact hole 13a. Electrically connected. A first dielectric layer 42a is formed between the first capacitor electrode 41a and the second capacitor electrode 43a, and is held by the first capacitor electrode 41a, the first dielectric layer 42a, and the second capacitor electrode 43a. A first holding capacitor 551 of the capacitor 55 is configured.

  On the surface of the interlayer insulating film 13 on the pixel electrode 9a side, a relay electrode 41s that overlaps the source electrode 51s in plan view is formed at a position spaced from the first capacitor electrode 41a. The relay electrode 41s is configured by the same conductive layer as the first capacitor electrode 41a. The relay electrode 41 s is electrically connected to the source electrode 51 s through a contact hole 13 s that penetrates the interlayer insulating film 13. The second capacitor electrode 43 a is electrically connected to the drain electrode 51 d through a contact hole 13 d that penetrates the interlayer insulating film 13.

  A light shielding data line 6 a is formed on the surface of the interlayer insulating film 14 on the pixel electrode 9 a side so as to extend in the second direction Y. The data line 6 a is a contact hole penetrating the interlayer insulating film 14. It is electrically connected to the relay electrode 41s via 14s. Therefore, the data line 6a is electrically connected to the source region 1b via the relay electrode 41s and the source electrode 51s. The data line 6a is made of a light-shielding conductive film such as a metal silicide film, a metal film, or a metal compound film. In the present embodiment, the data line 6a is, for example, a multilayer structure of Ti (titanium) layer / TiN (titanium nitride) layer / Al (aluminum) layer / TiN (titanium nitride) layer, or TiN layer / Al layer / TiN layer. It consists of a multilayer structure.

  A relay electrode 6b that overlaps the second capacitor electrode 43a in a plan view is formed at a position away from the data line 6a. The relay electrode 6 b is electrically connected to the second capacitor electrode 43 a through a contact hole 14 d that penetrates the interlayer insulating film 14. The relay electrode 6b is composed of the same conductive layer as the data line 6a.

  A light-shielding second capacitance line 52a extending in the second direction Y is formed on the surface of the interlayer insulating film 15 on the pixel electrode 9a side so as to overlap the data line 6a in plan view. A common potential is applied to the second capacitor line 52a. The interlayer insulating film 16 is formed with a second recess 74a made of a through hole that overlaps the second capacitor line 52a in plan view. Further, in a region overlapping with the second recess 74a, there is a light-shielding third capacitor electrode 71a extending from the bottom of the second recess 74a to the surface on the pixel electrode 9a side of the interlayer insulating film 16 and the third capacitor electrode 71a. A light-shielding fourth capacitor electrode 73a that overlaps from the pixel electrode 9a side is formed.

  The fourth capacitor electrode 73a is electrically connected to the drain electrode 51d and the pixel electrode 9a. More specifically, the fourth capacitor electrode 73 a is electrically connected to the relay electrode 6 b through a contact hole 16 d that penetrates the interlayer insulating films 15 and 16. The second capacitor line 52a is made of a light-shielding conductive film such as a metal silicide film, a metal film, or a metal compound film. In the present embodiment, the second capacitor line 52a, the source electrode 51s, and the drain electrode 51d have, for example, a multilayer structure of Ti (titanium) layer / TiN (titanium nitride) layer / Al (aluminum) layer / TiN (titanium nitride) layer. Alternatively, it has a multilayer structure of TiN layer / Al layer / TiN layer.

  The third capacitor electrode 71a is electrically connected to the second capacitor line 52a at the bottom of the second recess 74a. A second dielectric layer 72a is formed between the third capacitor electrode 71a and the fourth capacitor electrode 73a, and is held by the third capacitor electrode 71a, the second dielectric layer 72a, and the fourth capacitor electrode 73a. A second holding capacitor 552 of the capacitor 55 is configured. The third capacitor electrode 71a and the fourth capacitor electrode 73a are made of a conductive film such as a conductive polysilicon film, a metal silicide film, a metal film, or a metal compound film.

  A pixel electrode 9 a is formed on the surface of the interlayer insulating film 17 opposite to the first substrate 10. The pixel electrode 9 a is electrically connected to the fourth capacitor electrode 73 a through a contact hole 17 d that penetrates the interlayer insulating film 17. Accordingly, the pixel electrode 9a is electrically connected to the drain region 1c via the fourth capacitor electrode 73a, the relay electrode 6b, the second capacitor electrode 43a, and the drain electrode 51d.

(Light shielding structure for the semiconductor layer 1a)
FIG. 6 is a plan view showing a light shielding structure of the semiconductor layer 1a shown in FIG. FIG. 7 is a cross-sectional view taken along the line X1-X1 ′ when the light shielding structure shown in FIG. 6 is cut in the width direction of the semiconductor layer 1a. FIG. 8 is a cross-sectional view taken along the line Y1-Y1 ′ when the light shielding structure shown in FIG. 6 is cut in the length direction of the semiconductor layer 1a.

  As shown in FIGS. 6, 7, and 8, the second light shielding layer 8 a includes a main body portion 8 a 1 extending in the length direction (Y direction) of the semiconductor layer 1 a so as to overlap the semiconductor layer 1 a in plan view, Convex portions 8a2 and 8a3 projecting in the width direction (X direction) intersecting the main body portion 8a1 from an intermediate position of the main body portion 8a1, and the convex portions 8a2 and 8a3 overlap the scanning line 3a in plan view. ing. In this embodiment, a contact hole 11b that electrically connects the second light shielding layer 8a and the scanning line 3a is formed at a position overlapping the convex portion 8a2 in plan view.

  Further, on the one surface 10 s side of the first substrate 10, it extends in the thickness direction on both sides in the width direction of the semiconductor layer 1 a and both sides in the length direction of the semiconductor layer 1 a inside the insulating layer 110. A cavity 120 surrounding the entire circumference of the semiconductor layer 1a is provided. Here, the cavity 120 is vacuum and has a refractive index of 1. On the other hand, the refractive index of the silicon oxide film or the like constituting the insulating layer 110 is 1.46, for example. Therefore, the interface between the cavity 120 and the insulating layer 110 constitutes a reflective surface.

  In forming this cavity 120, in this embodiment, the interlayer insulating film 11 provided between the gate electrode 31a and the scanning line 3a is composed of the first insulating film 112 and the pixel electrode 9a side of the first insulating film 112. The second insulating film 116 is formed. Further, in the insulating layer 110, the interlayer insulating film 19, the gate insulating layer 2, and the first insulating film 112 form a wall surface 111 that covers the semiconductor layer 1a and the pixel electrode 9a side of the semiconductor layer 1a. The semiconductor layer 1a is removed in the thickness direction on both sides in the width direction and on both sides in the length direction of the semiconductor layer 1a. More specifically, the interlayer insulating film 19, the gate insulating layer 2, and the first insulating film 112 are removed from the semiconductor layer 1a and left only around the semiconductor layer 1a to form the wall surface 111. ing.

  Therefore, inside the wall surface 111, the interlayer insulating film 19, the semiconductor layer 1a, the gate insulating layer 2, the gate electrode 31a, and the first insulating film 112 are stacked, and the wall surface 111 includes the semiconductor layer 1a and the gate electrode. 31a is covered. In the present embodiment, the wall surface 111 is formed in a range overlapping the second light shielding layer 8a in plan view, and the wall surface 111 is formed so that the end on the first substrate 10 side is in contact with the second light shielding layer 8a. Has been.

  Here, the insulating layer 110 includes an inner wall forming film 113 formed so as to cover the wall surface 111, and the inner wall forming film 113 covers the semiconductor layer 1a and the gate electrode 31a. The inner wall forming film 113 forms a wall surface of the cavity 120 on the semiconductor layer 1a side.

  The insulating layer 110 includes an outer wall forming film 115 formed so as to cover the semiconductor layer 1a and the gate electrode 31a on the side opposite to the inner wall forming film 113 with respect to the cavity 120, and the inner wall forming film 113 and the outer wall forming film are formed. A cavity 120 is provided between Therefore, the outer wall forming film 115 constitutes a wall surface on the opposite side of the cavity 120 from the semiconductor layer 1a.

  The outer wall forming film 115 is provided with an opening 115a communicating with the cavity 120 at a portion overlapping the semiconductor layer 1a on the pixel electrode 9a side. In the state of the electro-optical device 100, the opening 115a is the second insulating film 116. It is blocked by. The cavity 120 has a connecting portion 125 that connects the cavities 120 located on both sides in the width direction of the semiconductor layer 1a through a portion where the opening 115a is formed in a region overlapping the semiconductor layer 1a in plan view. The other substantially entire region is a region where the cavity 120 does not exist. In this embodiment, in a region where the cavity 120 does not exist, the source electrode 51s and the drain electrode 51d are electrically connected to the source region 1b and the drain region 1c of the semiconductor layer 1a through the contact holes 12s and 12d.

  In the present embodiment, the cavity 120 is provided from a position closer to the first substrate 10 than the semiconductor layer 1a to a position closer to the pixel electrode 9a than the semiconductor layer 1a. More specifically, the cavity 120 is provided toward the pixel electrode 9a from the gate electrode 31a provided on the pixel electrode 9a side to the pixel electrode 9a side from the semiconductor layer 1a of the transistor 30 to the position on the pixel electrode 9a side. The scanning line 3a formed as one of the second light shielding layer 8a and the first light shielding layer is electrically connected to the electrode 31a from the pixel electrode 9a side with respect to the cavity 120. In the present embodiment, since the scanning line 3a is formed on the surface of the interlayer insulating film 11 covering the gate electrode 31a on the pixel electrode 9a side, the scanning line 3a includes the second insulating film 116, the outer wall forming film 115, The gate electrode 31a is electrically connected through a contact hole 11a penetrating the inner wall forming film 113 and the first insulating film 112.

  Further, the cavity 120 extends toward the first substrate 10 to a position where it overlaps with the end portion of the second light shielding layer 8a only through the inner wall forming film 113. Therefore, the semiconductor layer 1a is located behind at least one of the second light shielding layer 8a and the cavity 120 when viewed from any direction from the first substrate 10 side.

  In the present embodiment, the first end 121, which is the end of the cavity 120 on the pixel electrode 9a side, includes a first bent portion 126 bent inward where the semiconductor layer 1a is located in plan view. The second end 122, which is the end of the cavity 120 on the first substrate 10 side, includes a second bent portion 127 that is bent outwardly on the opposite side to the side where the semiconductor layer 1a is located in plan view. .

(Method of manufacturing electro-optical device 100)
FIG. 9 is a process cross-sectional view illustrating the manufacturing method of the electro-optical device 100 illustrated in FIG. 1 and illustrates the processes until the inner wall forming film 113 is formed. FIG. 10 is a process cross-sectional view illustrating processes subsequent to the process illustrated in FIG. 9, and illustrates the process until the second insulating film 116 is formed. 9 and 10 correspond to cross-sectional views taken along line X2-X2 'of FIG.

  Of the manufacturing processes of the electro-optical device 100 of the present embodiment, the process of forming the cavity 120 is as follows. First, in step ST1 shown in FIG. 9, a part of the second light shielding layer 8a, the semiconductor layer 1a, and the insulating layer 110 (interlayer insulating film 19, gate insulating layer 2 and first layer 10) is formed on the one surface 10s side of the first substrate 10. An insulating film 112) is formed. In the semiconductor layer 1a, impurities are introduced into the source region 1b and the drain region 1c shown in FIG.

  Next, in step ST2 shown in FIG. 9, with the etching mask M1 formed on the surface of the first insulating film 112, the interlayer insulating film 19, the gate insulating layer 2, and the first insulating film 112 are etched to form a semiconductor layer. The interlayer insulating film 19, the gate insulating layer 2, and the first insulating film 112 are removed from the periphery of 1a. As a result, a wall surface 111 that covers the semiconductor layer 1a and the pixel electrode 9a side of the semiconductor layer 1a is formed, and the wall surface 111 reaches the second light shielding layer 8a. At this time, the one surface 10s of the first substrate 10 is also etched with a predetermined thickness using the second light shielding layer 8a as a mask. Thereafter, the etching mask M1 is removed.

  Next, in step ST3 shown in FIG. 9, an insulating inner wall forming film 113 such as a silicon oxide film is formed as a protective film on the one surface 10s side of the first substrate 10, and the inner wall forming film 113 is formed on the wall surface 111. Are laminated. Next, in step ST4 (second step) shown in FIG. 9, a sacrificial film 114 such as a silicon film is formed so as to cover the wall surface 111. In the present embodiment, the sacrificial film 114 is formed so as to cover the wall surface 111 via the inner wall forming film 113.

  Next, in step ST5 shown in FIG. 9, the sacrificial film 114 is patterned in a state where an etching mask (not shown) is formed, and most of the portion of the sacrificial film 114 that overlaps the semiconductor layer 1a in plan view. Remove. In the present embodiment, the sacrificial film 114 is formed on a portion corresponding to the connecting portion 125 described with reference to FIG. 6 and the first bent portion 126 shown in FIG. Leave. Further, portions of the sacrificial film 114 and the inner wall forming film 113 that protrude from the second light shielding layer 8a are removed by etching.

  Next, in step ST6 (third step) shown in FIG. 10, the other part (outer wall formation) different from the part (interlayer insulating film 19, gate insulating layer 2 and first insulating film 112) of the insulating layer 110. A film 115) is formed so as to cover the sacrificial film 114. The outer wall forming film 115 is made of a silicon oxide film or the like.

  Next, in step ST7 (fourth step) shown in FIG. 10, etching is performed in a state where an etching mask (not shown) is formed, and among other parts of the insulating layer 110 (outer wall formation film 115), An opening 115a is formed in a portion overlapping the sacrificial film 114 in plan view. In the present embodiment, the opening 115a is formed in a portion overlapping the connecting portion 125 in plan view.

  Next, in step ST8 (fifth step) shown in FIG. 10, the sacrificial film 114 is removed from the opening 115a by etching, and the thickness is increased on both sides in the width direction of the semiconductor layer 1a and on both sides in the length direction of the semiconductor layer 1a. A cavity 120 extending in the vertical direction and surrounding the semiconductor layer 1a in plan view is formed. The sacrificial film 114 is removed by dry etching with high etching selectivity between the silicon oxide film and the silicon film in a vacuum atmosphere.

  Next, in step ST9 shown in FIG. 10, the second insulating film 116 is formed on the one surface 10s of the first substrate 10 and the surface of the outer wall forming film 115. As a result, the opening 115 a is blocked by the second insulating film 116. Here, since the second insulating film 116 is formed by a film forming method such as a CVD method in a vacuum atmosphere, the cavity 120 is sealed in a vacuum state.

  Thereafter, as shown in FIGS. 6, 7, 8, etc., the second insulating film 116, the outer wall forming film 115, the inner wall forming film 113, the contact hole 11 a penetrating the first insulating film 112, and the second insulating film are formed. After the contact hole 11b penetrating the film 116 and the outer wall forming film 115 is formed, the scanning line 3a is formed. As a result, the scanning line 3a is electrically connected to the gate electrode 31a and the second light shielding layer 8a.

  Thereafter, after forming an interlayer insulating film, various wirings, and the like, the electro-optical device 100 can be obtained by performing a known process such as making the first substrate 10 and the second substrate 20 face each other via the electro-optical layer 80. Complete.

(Main effects of the embodiment)
As described above, in the electro-optical device 100 according to the present embodiment, the entire semiconductor layer 1a of the transistor 30 is viewed in plan in the first light shielding layer such as the scanning line 3a and the data line 6a and the second light shielding layer 8a. Therefore, light from the pixel electrode 9a side and the first substrate 10 side toward the semiconductor layer 1a can be blocked by the first light shielding layer and the second light shielding layer 8a.

  The insulating layer 110 formed on the one surface 10s of the first substrate 10 has a planar surface extending in the thickness direction on both sides in the width direction of the semiconductor layer 1a and on both sides in the length direction of the semiconductor layer 1a. A cavity 120 that surrounds the periphery of the semiconductor layer 1a is provided. For this reason, it is possible to block light that is about to enter the semiconductor layer 1a from the width direction of the semiconductor layer 1a by using reflection at the interface between the cavity 120 and the insulating layer 110, and the length of the semiconductor layer 1a Light traveling toward the semiconductor layer 1a from a direction inclined obliquely with respect to the vertical direction or the length direction can be blocked using reflection at the interface between the cavity 120 and the insulating layer 110. That is, not only the channel region 1i but also the light traveling toward the semiconductor layer 1a can be blocked over the entire circumference. Therefore, since the incidence of light on the semiconductor layer 1a of the transistor 30 can be further suppressed, the generation of light leakage current can be further suppressed in the transistor 30.

  In other words, in plan view, the semiconductor layer 1a and the insulating layers (the outer wall forming film 115 and the second insulating film) covering the semiconductor layer 1a on both sides in the width direction of the semiconductor layer 1a and on both sides in the length direction of the semiconductor layer 1a. 116). For this reason, it is possible to block light that is about to enter the semiconductor layer 1a from the width direction of the semiconductor layer 1a by using reflection on the wall surface of the outer wall forming film 115, and in the length direction of the semiconductor layer 1a. Light traveling toward the semiconductor layer 1a from a direction inclined obliquely with respect to the length direction can be blocked using reflection on the wall surface of the outer wall forming film 115. Therefore, since the incidence of light on the semiconductor layer 1a of the transistor 30 can be further suppressed, the generation of light leakage current can be further suppressed in the transistor 30.

  The cavity 120 overlaps at least one of the first light shielding layer such as the scanning line 3a, the data line 6a, the first capacitance line 51a, the second capacitance line 52a, and the second light shielding layer 8a in plan view. Can be provided. Therefore, the occurrence of light leakage current can be suppressed without narrowing the opening region 108b (translucent region) of each pixel.

  Moreover, since the inside of the cavity 120 is a vacuum, the cavity 120 may be closed using a semiconductor process in a vacuum. Therefore, it is easier to form the cavity 120 than when the inside of the cavity 120 is an air layer.

  In this embodiment, since the cavity 120 is provided in the thickness direction from the position on the first substrate 10 side with respect to the semiconductor layer 1a to the position on the pixel electrode 9a side with respect to the semiconductor layer 1a, the cavity 120 attempts to enter the semiconductor layer 1a. Can be blocked by reflection at the interface between the cavity 120 and the insulating layer 110. The semiconductor layer 1a is located behind at least one of the second light shielding layer 8a and the cavity 120 when viewed from any direction from the first substrate 10 side. Therefore, even when the light emitted from the electro-optical device 100 is reflected by an optical element or the like and the return light incident again on the electro-optical device 100 is going to travel from the first substrate 10 side toward the semiconductor layer 1a. Such light can be blocked by reflection at the interface between the cavity 120 and the insulating layer 110 or by the second light shielding layer 8a.

  The cavity 120 is provided toward the pixel electrode 9a from the gate electrode 31a provided on the pixel electrode 9a side to the pixel electrode 9a side from the semiconductor layer 1a of the transistor 30. Even in this case, since the scanning line 3a is formed on the surface of the second insulating film 116 covering the gate electrode 31a on the pixel electrode 9a side, the scanning line 3a includes the second insulating film 116, the outer wall forming film 115, It is electrically connected to the gate electrode 31a through a contact hole 11a penetrating the inner wall forming film 113 and the first insulating film 112. Therefore, it is possible to avoid the scanning line 3a being interrupted by the cavity 120.

  The first end 121, which is the end of the cavity 120 on the pixel electrode 9a side, includes a first bent portion 126 bent inward where the semiconductor layer 1a is located in a plan view. Even when the diffracted light tends to travel from the pixel electrode 9a side toward the semiconductor layer 1a, the light can be blocked by reflection at the interface between the first bent portion 126 of the cavity 120 and the insulating layer 110. The second end 122, which is the end of the cavity 120 on the first substrate 10 side, includes a second bent portion 127 that is bent outwardly on the opposite side to the side where the semiconductor layer 1a is located in plan view. Therefore, even when the light diffracted by the surrounding light shielding layer attempts to travel toward the semiconductor layer 1a from the gap between the second light shielding layer 8a and the cavity 120, the light is transmitted to the second bent portion 127 of the cavity 120 and the insulating layer 110. It can be blocked by reflection at the interface and a light shielding layer.

  Further, according to the manufacturing method described with reference to FIGS. 9 and 10, the wall surface 111 formed on the insulating film so as to cover the semiconductor layer 1a and the pixel electrode 9a side of the semiconductor layer 1a is formed into the inner wall forming film 113. After the sacrificial film 114 is formed so as to cover the insulating film 114, another insulating film (outer wall forming film 115) covering the sacrificial film 114 is formed, and the sacrificial film 114 is removed from the opening 115a of the outer wall forming film 115 by etching. Thus, the cavity 120 is formed. For this reason, the cavity 120 having a shape suitable for light shielding, such as surrounding the semiconductor layer 1a, can be easily formed.

[Modification of the present invention]
In the above embodiment, the wall surface of the cavity 120 on the semiconductor layer 1a side is configured by the inner wall forming film 113. However, without providing the inner wall forming film 113, the interlayer insulating film 19 positioned inside the cavity 120, the gate insulating layer 2, The first insulating film 112 may constitute a wall surface of the cavity 120 on the semiconductor layer 1a side. In this case, the second end 122 of the cavity 120 on the first substrate 10 side is in contact with the second light shielding layer 8a. According to this configuration, it is possible to more reliably suppress the return light incident from the first substrate 10 side from entering the semiconductor layer 1a.

[Other Embodiments]
In the above embodiment, the cavity 120 is formed so as to surround the entire circumference of the semiconductor layer 1a in plan view, but extends on both sides in the width direction of the semiconductor layer 1a and both sides in the length direction of the semiconductor layer 1a. If it is a structure, a part in the circumferential direction may be interrupted.

  In the manufacturing method described with reference to FIGS. 9 and 10, the sacrificial film 114 is patterned before the outer wall forming film 115 is formed. However, when the opening 115 a is formed in the outer wall forming film 115, the semiconductor layer 1 a A method of etching the sacrificial film 114 using a region where the cavity 120 is not provided, such as a region overlapping in plan view, as the opening 115a may be employed. In this case, since the second insulating film 116 is formed in a region where the sacrificial film 114 is removed in a region that overlaps the semiconductor layer 1a in plan view, the cavity 120 is not formed.

[Example of mounting on electronic equipment]
An electronic apparatus using the electro-optical device 100 according to the above-described embodiment will be described. FIG. 11 is a schematic configuration diagram of a projection display device (electronic apparatus) using the electro-optical device 100 to which the present invention is applied. In FIG. 11, an optical element such as a polarizing plate is not shown. A projection display device 2100 illustrated in FIG. 11 is an example of an electronic apparatus using the electro-optical device 100. In the projection display device 2100, the electro-optical device 100 is used as a light valve, and high-definition and bright display is possible without increasing the size of the device. As shown in this figure, a lamp unit 2102 (light source unit) having a white light source such as a halogen lamp is provided inside the projection display device 2100. The projection light emitted from the lamp unit 2102 is converted into three primary colors of R (red), G (green), and B (blue) by three mirrors 2106 and two dichroic mirrors 2108 arranged inside. To be separated. The separated projection light is respectively guided to the light valves 100R, 100G, and 100B corresponding to the respective primary colors and modulated. B light has a longer optical path than other R and G colors. Therefore, in order to prevent the loss, light of B color is guided through a relay lens system 2121 having an incident lens 2122, a relay lens 2123, and an output lens 2124. It is burned.

  The lights modulated by the light valves 100R, 100G, and 100B are incident on the dichroic prism 2112 from three directions. In the dichroic prism 2112, the R and B light beams are reflected at 90 degrees, and the G light beam is transmitted. Accordingly, after the primary color images are combined, a color image is projected onto the screen 2120 by the projection lens group 2114 (projection optical system).

(Other projection display devices)
In addition, about a projection type display apparatus, you may comprise the LED light source etc. which radiate | emit the light of each color as a light source part, and supply each color light radiate | emitted from this LED light source to another liquid crystal device. .

(Other electronic devices)
The electronic apparatus including the electro-optical device 100 to which the present invention is applied is not limited to the projection display device 2100 of the above embodiment. For example, you may use for electronic devices, such as a projection type HUD (head-up display), a direct view type HMD (head mounted display), a personal computer, a digital still camera, and a liquid crystal television.

DESCRIPTION OF SYMBOLS 1a ... Semiconductor layer, 3a ... Scan line, 6a ... Data line, 8a ... 2nd light shielding layer, 8a1 ... Main-body part, 8a2, 8a3 ... Convex part, 9a ... Pixel electrode, 10 ... 1st board | substrate, 10a ... Display area, 10s: one side, 11, 12, 13, 14, 15, 16, 17, 19 ... interlayer insulating film, 20 ... second substrate, 21 ... common electrode, 30 ... transistor, 31a ... gate electrode, 51a ... first capacitor Wire 51d drain electrode 51s source electrode 52a second capacitance line 80 electro-optical layer 100 electro-optical device 100B, 100G, 100R light valve 110 insulating layer 111 wall 112 DESCRIPTION OF SYMBOLS 1st insulating film, 113 ... Inner wall formation film, 114 ... Sacrificial film, 115 ... Outer wall formation film, 115a ... Opening part, 116 ... 2nd insulation film, 120 ... Cavity, 121 ... 1st edge part, 122 ... 2nd Edge, 1 DESCRIPTION OF SYMBOLS 5 ... Connection part, 126 ... 1st bending part, 127 ... 2nd bending part, 2100 ... Projection type display apparatus, 2102 ... Lamp unit (light source part), 2106 ... Mirror, 2108 ... Dichroic mirror, 2112 ... Dichroic prism, 2114 ... projection lens group (projection optical system), 2120 ... screen, 2121 ... relay lens system, 2122 ... incident lens, 2123 ... relay lens, 2124 ... exit lens.

Claims (13)

A substrate,
A pixel electrode provided on one side of the substrate;
A first light-shielding layer provided between the substrate and the pixel electrode and extending along an edge of the pixel electrode in plan view;
A transistor including a semiconductor layer extending between the substrate and the first light-shielding layer and overlapping the first light-shielding layer in plan view;
A second light-shielding layer provided between the substrate and the semiconductor layer and overlapping the semiconductor layer in plan view;
An insulating layer provided between the substrate and the pixel electrode;
In a plan view, cavities provided on both sides in the width direction of the semiconductor layer and on both sides in the length direction of the semiconductor layer;
An electro-optical device comprising: The electro-optical device according to claim 1.
The electro-optical device, wherein the cavity surrounds the semiconductor layer in a plan view. The electro-optical device according to claim 1,
An electro-optical device characterized in that the inside of the cavity is a vacuum. The electro-optical device according to any one of claims 1 to 3,
The cavity is provided from a position closer to the substrate than the semiconductor layer to a position closer to the pixel electrode than the semiconductor layer in a thickness direction that is a direction perpendicular to the substrate. Electro-optic device. The electro-optical device according to claim 4.
The electro-optical device, wherein the semiconductor layer is located behind at least one of the light shielding layer and the cavity when viewed from any direction from the substrate side. The electro-optical device according to claim 4 or 5,
The cavity is provided from the gate electrode provided on the pixel electrode side from the semiconductor layer of the transistor in the thickness direction to a position on the pixel electrode side,
A scanning line formed as one of the first light-shielding layer and the second light-shielding layer is electrically connected to the gate electrode from the pixel electrode side with respect to the cavity. Optical device. The electro-optical device according to any one of claims 1 to 6,
An electro-optical device, wherein a first end portion which is an end portion of the cavity on the pixel electrode side includes a first bent portion bent inward where the semiconductor layer is located in a plan view. The electro-optical device according to any one of claims 1 to 7,
The second end portion, which is the end portion of the cavity on the substrate side, includes a second bent portion that is bent outward on a side opposite to the side on which the semiconductor layer is located in a plan view. Optical device. The electro-optical device according to any one of claims 1 to 8,
The insulating layer includes an outer wall forming film that is provided so as to cover the semiconductor layer and forms a wall surface on the opposite side of the cavity from the semiconductor layer,
The electro-optical device, wherein the outer wall forming film is provided with an opening communicating with the cavity at a portion overlapping the semiconductor layer on the pixel electrode side. The electro-optical device according to any one of claims 1 to 9,
The electro-optical device, wherein the insulating layer includes an inner wall forming film that is provided so as to cover the semiconductor layer and forms a wall surface of the cavity on the semiconductor layer side. The electro-optical device according to any one of claims 1 to 9,
An electro-optical device comprising: an inner wall forming film which is provided so as to surround the semiconductor layer on the semiconductor layer side with respect to the cavity and forms a wall surface of the cavity on the semiconductor layer side. An electronic apparatus comprising the electro-optical device according to any one of claims 1 to 11 . A substrate,
A pixel electrode provided on one side of the substrate; a first light shielding layer provided between the substrate and the pixel electrode and extending along an edge of the pixel electrode in plan view;
A transistor including a semiconductor layer extending between the substrate and the first light-shielding layer and overlapping the first light-shielding layer in plan view;
A second light-shielding layer provided between the substrate and the semiconductor layer and overlapping the semiconductor layer in plan view;
An insulating layer provided between the substrate and the pixel electrode;
In a method of manufacturing an electro-optical device having:
After forming a part of the first light-shielding layer, the semiconductor layer, and the insulating layer on one side of the substrate,
A first step of etching a part of the insulating layer to form a wall surface surrounding the semiconductor layer and covering the pixel electrode side of the semiconductor layer;
A second step of forming a sacrificial film so as to cover the wall surface;
A third step of forming another part different from the part of the insulating layer so as to cover the sacrificial film;
A fourth step of forming an opening in a portion overlapping the other part of the sacrificial film in the plan view;
A fifth step of removing the sacrificial film from the opening and forming cavities on both sides in the width direction of the semiconductor layer and on both sides in the length direction of the semiconductor layer in plan view;
A method for manufacturing an electro-optical device.