JP6589296B2 - Electrostatic protection circuit, circuit device and electronic device - Google Patents

Electrostatic protection circuit, circuit device and electronic device Download PDF

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JP6589296B2
JP6589296B2 JP2015039014A JP2015039014A JP6589296B2 JP 6589296 B2 JP6589296 B2 JP 6589296B2 JP 2015039014 A JP2015039014 A JP 2015039014A JP 2015039014 A JP2015039014 A JP 2015039014A JP 6589296 B2 JP6589296 B2 JP 6589296B2
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power supply
circuit
electrostatic protection
transistors
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JP2016162844A (en
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池田 益英
益英 池田
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セイコーエプソン株式会社
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Description

  The present invention relates to an electrostatic protection circuit, a circuit device, an electronic device, and the like.

  When an electronic device is exposed to electrostatic discharge from a charged operator, a transistor of a circuit device built in the electronic device may be electrostatically broken. In order to prevent such electrostatic breakdown, the circuit device is provided with an electrostatic protection circuit. As a conventional technique of this electrostatic protection circuit, for example, there is a technique disclosed in Patent Document 1.

  FIG. 1 shows a configuration example of the electrostatic protection circuit disclosed in Patent Document 1. An ESD (Electro Static Discharge) event occurs when static electricity is charged in a human body or a transport device when a semiconductor circuit device (IC) is transported and flows into the circuit device. At the first time point, the first power supply line PL1 in FIG. 1 is equipotential with the second power supply line PL2. During normal operation, the first power supply line PL1 is a supply line for the high-potential-side power supply voltage VDD, and the second power supply line PL2 is a supply line for the low-potential-side power supply voltage VSS.

  Here, as an ESD event, a positive ESD surge is applied to the first power supply line PL1 with reference to the second power supply line PL2. The charge due to the ESD surge is charged into the capacitor CA via the resistor RA of the time constant circuit 500. Here, the value of the CR time constant determined by the resistance value of the resistor RA and the capacitance value of the capacitor CA is sufficiently large. Therefore, the input node of the first-stage inverter 502 is maintained at the L level for a period corresponding to the time constant. In a state where the input node of the inverter 502 is maintained at the L level, the potential of the gate of the N-type transistor TA1 is set to the H level via the subsequent inverters 504 and 505. Accordingly, the N-type transistor TA1, which is a discharge element for electrostatic protection, is turned on. In this way, by releasing the surge current through the transistor TA1, a high voltage is applied between the first power supply line PL1 and the second power supply line PL2, and the transistors in the internal circuit are destroyed. Can be suppressed. Note that the potential of the gate of the transistor TA1 is lowered with the passage of a period defined by the time constant circuit 500 after the ESD surge is applied.

JP 2009-182119 A

  However, in the conventional electrostatic protection circuit, in a normal operation in which power is supplied to the power supply lines PL1 and PL2, an abnormal state in which current continues to flow when the transistor TA1 enters a snapback state due to external noise or the like. There is a possibility of falling into. In this case, it is possible to return from such an abnormal state to a normal state by stopping the power supply to the circuit device and reducing the power supply voltage. However, it is not desirable to stop the power supply to recover from such an abnormal state.

  According to some aspects of the present invention, it is possible to provide an electrostatic protection circuit, a circuit device, an electronic device, and the like that can suppress an abnormal state such as a current continuously flowing due to external noise or the like.

  One embodiment of the present invention is provided between a first power supply line to which a first power supply voltage is supplied and a second power supply line to which a second power supply voltage lower than the first power supply voltage is supplied. A trigger circuit provided, and a discharge circuit having a first transistor and a second transistor, at least one of which is controlled based on an output of the trigger circuit, wherein the first transistor and the second transistor are: , And an electrostatic protection circuit cascade-connected between the first power supply line and the second power supply line.

  In one embodiment of the present invention, the discharge circuit includes first and second transistors connected in cascade between the first power supply line and the second power supply line. At least one of the first and second transistors is controlled based on the output of the trigger circuit. If the discharge circuit has such a configuration, the discharge operation of the discharge circuit can be realized by the two-stage first and second transistors cascaded between the first power supply line and the second power supply line. It becomes like this. Therefore, for example, during a normal operation with power supplied, even when a current flows due to external noise or the like, an abnormal state in which the current continues to flow is detected in two cascaded stages. It can be suppressed by the first and second transistors.

  In one embodiment of the present invention, the voltage obtained by adding the snapback hold voltage of the first transistor and the snapback hold voltage of the second transistor is the first power supply voltage and the second power supply voltage. It may be larger than the voltage difference between the power supply voltages.

  In this way, even when a snapback current flows due to external noise or the like, the added voltage of the snapback hold voltage of the first and second transistors becomes the first and second power supplies. Since the voltage difference is larger than the voltage difference, it is possible to suppress the current from continuing to flow.

  In one embodiment of the present invention, the first transistor and the second transistor may be formed in the same well.

  By doing so, parasitic first and second bipolar transistors are formed corresponding to the first and second transistors. Accordingly, it is possible to suppress an abnormal state in which a current continues to flow due to external noise or the like due to a hold voltage or the like by these first and second bipolar transistors.

  In one embodiment of the present invention, the first transistor and the second transistor may be N-type transistors.

  In this way, the discharge operation of the discharge circuit can be realized using the N-type first and second transistors having a high current supply capability.

  In one embodiment of the present invention, an output of the trigger circuit may be input to a gate of the first transistor and a gate of the second transistor.

  In this way, for example, when an electrostatic discharge surge is applied, the N-type first and second transistors that are turned on by the output of the trigger circuit can discharge the current due to the surge. .

  In one embodiment of the present invention, the gate of one of the first transistor and the second transistor is connected to the first power supply line, and the output of the trigger circuit is connected to the gate of the other transistor. It may be entered.

  In this way, for example, when a surge of electrostatic discharge is applied, one transistor turned on by the output of the trigger circuit and the other turned on by connecting the first power supply line With this transistor, the current due to the surge can be discharged.

  In one embodiment of the present invention, at least one of the first transistor and the second transistor may be a P-type transistor.

  In this way, the discharge operation of the discharge circuit can be realized using the P-type first and second transistors.

  In one embodiment of the present invention, the first transistor is a P-type transistor, the second transistor is an N-type transistor, and an output of the trigger circuit is input to a gate of the N-type transistor. May be.

  In this way, for example, when an electrostatic discharge surge is applied, the N-type second transistor turned on by the output of the trigger circuit and the P-type turned on by setting the gate potential, etc. With this first transistor, the current due to the surge can be discharged.

  In one embodiment of the present invention, the trigger circuit includes a resistor and a capacitor provided in series between the first power supply line and the second power supply line, and a connection node between the resistor and the capacitor as an input node. And an inverter.

  In this way, for example, when an electrostatic discharge surge is applied, the output of the trigger circuit is set to a predetermined voltage level for a period corresponding to a time constant determined by the resistance value of the resistor and the capacitance value of the capacitor. Thus, the discharge operation of the discharge circuit can be realized.

  In one embodiment of the present invention, the first transistor and the second transistor may be arranged such that a well potential setting impurity region faces a drain region of the first transistor.

  In this way, for example, a negative surge of electrostatic discharge is applied using a parasitic diode formed by the well potential setting impurity region and the drain region of the first transistor facing each other. In this case, it is possible to realize a discharge operation.

  In the aspect of the invention, the first transistor includes a plurality of first unit transistors, the second transistor includes a plurality of second unit transistors, and the plurality of first units. The source of the unit transistor and the drains of the plurality of second unit transistors may be commonly connected.

  In this way, the first and second transistors of the discharge circuit can be realized by the plurality of first unit transistors and the plurality of second unit transistors. For example, even when a failure or the like occurs in one of the first unit transistor and the second unit transistor, the other unit transistor corresponding to the one unit transistor does not contribute to electrostatic protection. Can be prevented.

  In the aspect of the invention, the plurality of first unit transistors are disposed in a first region, and the plurality of second unit transistors are disposed in a second region different from the first region. May be.

  In this way, a plurality of first unit transistors can be arranged together in the first region, and a plurality of second unit transistors can be arranged together in the second region. An efficient layout arrangement can be realized.

  In one embodiment of the present invention, a drain region of at least one unit transistor of the plurality of first unit transistors may be disposed so as to face a well potential setting impurity region.

  In this way, by using a parasitic diode formed by the well potential setting impurity region and the drain region of at least one unit transistor of the first transistor facing each other, for example, negative electrostatic discharge can be performed. It is possible to realize a discharge operation when a surge or the like is applied.

  In the aspect of the invention, the first transistor includes a plurality of first unit transistors, the second transistor includes a plurality of second unit transistors, and the plurality of first units. Each first unit transistor of the unit transistors is connected to one corresponding second unit transistor among the plurality of second unit transistors, and may be disconnected from the other second unit transistors. Good.

  In this way, the first and second transistors of the discharge circuit can be realized by the plurality of first unit transistors and the plurality of second unit transistors, and an efficient layout arrangement of the electrostatic protection circuit can be realized. .

  Another aspect of the present invention relates to a circuit device including the static electricity protection circuit described above.

  Another aspect of the invention relates to an electronic device including the circuit device described above.

A configuration example of a conventional electrostatic protection circuit. FIG. 6 is a discharge path diagram when a positive ESD surge is applied in a circuit device in which an electrostatic protection circuit is arranged between power supplies. FIG. 5 is a discharge path diagram when a negative ESD surge is applied in a circuit device in which an electrostatic protection circuit is arranged between power supplies. The graph explaining the operation | movement at the time of applying the conventional electrostatic protection circuit in the discharge path | route figure of FIG. 2 or FIG. The figure which shows the discharge current waveform of the standard of ESD immunity test. 6 is a configuration example of an electronic device on which a circuit device is mounted. FIGS. 7A to 7C are operation explanatory diagrams of an equivalent circuit of a conventional electrostatic protection circuit when a steep surge current is input. The graph of IV characteristic explaining the operation | movement of FIG. 7 (A)-FIG.7 (C). 1 is a first configuration example of an electrostatic protection circuit according to an embodiment. Sectional drawing of the 1st, 2nd transistor which comprises a discharge circuit. FIGS. 11A to 11C are operation explanatory diagrams of the equivalent circuit of the first configuration example when a steep surge current is input. The graph of IV characteristic explaining the operation | movement of FIG. 11 (A)-FIG.11 (C). The 2nd structural example of the electrostatic protection circuit of this embodiment. FIG. 14A to FIG. 14C are operation explanatory diagrams of an equivalent circuit of the second configuration example when a steep surge current is input. FIG. 15 is a graph of IV characteristics for explaining the operation of FIGS. The 3rd structural example of the electrostatic protection circuit of this embodiment. FIGS. 17A to 17C are operation explanatory diagrams of an equivalent circuit of the third configuration example when a steep surge current is input. The 4th structural example of the electrostatic protection circuit of this embodiment. FIGS. 19A to 19C are operation explanatory diagrams of an equivalent circuit of the fourth configuration example when a steep surge current is input. The 5th structural example of the electrostatic protection circuit of this embodiment. 6 is a sixth configuration example of an electrostatic protection circuit of the present embodiment. The 1st layout arrangement example of this embodiment. The equivalent circuit of the 1st, 2nd transistor in the 1st layout arrangement example. Sectional drawing for demonstrating the parasitic diode for electrostatic protection. The 2nd layout arrangement example of this embodiment. The 3rd layout arrangement example of this embodiment. The equivalent circuit of the 1st, 2nd transistor in the 3rd layout arrangement example. The 4th layout arrangement example of this embodiment. Configuration example of an electronic device.

  Hereinafter, preferred embodiments of the present invention will be described in detail. The present embodiment described below does not unduly limit the contents of the present invention described in the claims, and all the configurations described in the present embodiment are indispensable as means for solving the present invention. Not necessarily.

1. Occurrence of abnormal state due to static electricity First, problems of the conventional electrostatic protection circuit will be described with reference to FIGS. FIG. 2 is a discharge path diagram when the electrostatic protection circuit PC is arranged between the power sources of VDD and VSS and a positive ESD surge is applied to the input terminal PIN. The ESD surge current IESD is discharged through the diode DB1, the parasitic resistance RB1 of the VDD power supply wiring, the electrostatic protection circuit PC, and the parasitic resistance RB2 of the VSS power supply wiring.

  In this discharge operation, the internal circuit 210 can be protected by the electrostatic protection circuit PC if the source-drain voltage of the N-type transistor TB2 constituting the internal circuit 210 of the circuit device is lower than the voltage VDMG leading to destruction. . For this purpose, it is necessary to satisfy the following formula (1).

VFD + VWR + VPC <VDMG (1)
Here, VFD is a forward voltage when a current flows in the forward direction of the diode DB1. VWR is a voltage induced when the surge current IESD flows through the parasitic resistance RB1 of the power supply wiring. VPC is a voltage induced when a surge current IESD flows through the electrostatic protection circuit PC.

  FIG. 3 is a discharge path diagram when the electrostatic protection circuit PC is arranged between the power sources of VDD and VSS and a negative ESD surge is applied to the input terminal PIN. The ESD surge current IESD is discharged through the parasitic resistance RB1 of the VDD power supply wiring, the electrostatic protection circuit PC, the parasitic resistance RB2 of the VSS power supply wiring, and the diode DB2.

  In this discharge operation, the internal circuit 210 can be protected by the electrostatic protection circuit PC if the source-drain voltage of the P-type transistor TB1 constituting the internal circuit 210 of the circuit device is lower than the voltage VDMG that causes destruction. . For this purpose, the following formula (2) must be satisfied.

VFD + VWR + VPC <VDMG (2)
Here, VFD is a forward voltage when a current flows in the forward direction of the diode DB2. VWR is a voltage induced when the surge current IESD flows through the parasitic resistance RB2 of the power supply wiring. VPC is a voltage induced when a surge current IESD flows through the electrostatic protection circuit PC.

  As can be understood from the above formulas (1) and (2), both can be expressed by the same formula. That is, it is a necessary condition for protecting the internal circuit 210 from static electricity that the total voltage (VFD + VWR + VPC) induced in each device on the discharge path is lower than the voltage VDMG that causes the internal circuit 210 to break down.

  FIG. 4 is a graph of IV characteristics (current-voltage characteristics) for explaining the operation when the conventional electrostatic protection circuit (FIG. 1) is used as the electrostatic protection circuit PC in the discharge path diagram of FIG. 2 or FIG. . In FIG. 4, the horizontal axis represents voltage, and the vertical axis represents current. A1 is the IV characteristic of the electrostatic protection circuit PC alone. A2 is the IV characteristic when the wiring resistance (RB1, RB2) is further considered. A3 is the IV characteristic when considering the wiring resistance and the forward voltage of the diodes (DB1, DB2). For example, in the IV characteristic of A3, if the voltage at the target current ITG is lower than the voltage VDMG leading to destruction and the margin voltage VMA is secured, the internal circuit 210 can be protected by the electrostatic protection circuit PC. . For example, in the human body model (HBM) test method, an ESD surge current is flowed from an external capacitor through, for example, a 1500 Ω resistor, so that the target current ITG when 2000 V is applied is 2000 V / 1500 Ω.

  FIG. 5 is a diagram showing a discharge current waveform of the standard (IEC61000-4-2) of the electrostatic discharge immunity test (ESD immunity test). This standard is for electronic equipment that is exposed to electrostatic discharge from a charged operator, either directly or through a nearby object. As indicated by A5 in FIG. 5, the rise time is as fast as 0.8 nsec. In the human body model (HBM) test method, the rise time is about 10 nsec. In the peak indicated by A6 in FIG. 5, a current application is performed with a longer period but a longer period than the peak indicated by A5.

  The ESD immunity test is performed in order to verify the continuity and reliability of operation at a realistic ESD level in accordance with the actual use state of the electronic device. For example, a circuit device is mounted on a circuit board (test board), and a discharge pulse by a discharge gun is applied to a terminal or the like of the circuit device (IC) while power is supplied. When an abnormal state in which a large current flows between the power supplies of the circuit device due to this discharge pulse, it is necessary to be able to recover from this abnormal state without stopping the power supply to the circuit device.

  However, in the conventional electrostatic protection circuit of FIG. 1 or the like, if a snap-back of the transistor TA1, for example, occurs due to a discharge pulse and falls into an abnormal state in which a large current flows, there is a problem that the normal state cannot be restored from this abnormal state. there were.

  For example, FIG. 6 is a block diagram showing a state where the electronic device 250 on which the circuit device 200 is mounted is normally operated. Power supply voltages VDD and VSS are supplied from the power supply device 540 to the electronic device 250 and the circuit device 200. In the electronic device 250, noise countermeasures are taken by the bypass capacitor CB1 provided between the power supplies. The bypass capacitor CB1 is provided, for example, on a circuit board on which the circuit device 200 is mounted. In the wiring of the circuit board of the electronic device 250, there are parasitic resistances RB3 and RB4 of the wiring. When the ESD immunity test is performed on the electronic device 250, the noise component can be removed to some extent by the bypass capacitor CB1, but due to the presence of the wiring parasitic resistances RB3 and RB4, the power supply of the circuit device 200 varies rapidly. there's a possibility that. For example, when a discharge pulse is applied to the VDD or VSS terminal of the circuit device 200 with a discharge gun, the impedance of the parasitic resistances RB3 and RB4 is high, so that the surge current due to the discharge pulse cannot be absorbed by the bypass capacitor CB1. Rapid potential fluctuation occurs between power supplies.

  FIGS. 7A to 7C are operation explanatory diagrams of an equivalent circuit of a conventional electrostatic protection circuit when a steep surge current is input. TA1 is an N-type transistor included in the electrostatic protection circuit PC of FIG. 6, and is provided between the power sources of VDD and VSS as shown in FIG. 1 and functions as a discharge element for electrostatic protection.

  In FIG. 7A, the transistor TA1 as a discharge element has not yet been turned on, and thus the transistor TA1 is in an off state. That is, a steep surge current rising in a period shorter than the time constant period of the time constant circuit 500 of FIG. 1 is applied, and in this state, the transistor TA1 is turned off. A parasitic NPN bipolar transistor BA1 is formed in the transistor TA1. The drain, substrate, and source of the transistor TA1 correspond to the collector, base, and emitter of the NPN bipolar transistor BA1, respectively. The parasitic resistance RA1 of the substrate becomes a base resistance.

  FIG. 7B is a discharge path diagram when the drain voltage of the transistor TA1 exceeds the breakdown voltage and the current IE starts to flow. The breakdown voltage is determined by the breakdown voltage between the collector and base of the NPN bipolar transistor BA1. As the current IE increases, the current flows through the parasitic resistor RA1 serving as the base resistor, thereby increasing the potential of the base node NA1 of the bipolar transistor BA1.

  FIG. 7C is a discharge path diagram when the transistor TA1 is in a snapback state. As the potential of the base node NA1 rises, the parasitic bipolar transistor BA1 is turned on, and snapback occurs.

  FIG. 8 is a graph of IV characteristics for explaining the operations of FIGS. 7 (A) to 7 (C). In FIG. 8, the horizontal axis represents voltage, and the vertical axis represents current. As shown in B1 of FIG. 8, when the drain voltage of the N-type transistor TA1 exceeds the breakdown voltage VBD, a current starts to flow. As shown in B2, when the drain voltage exceeds the snapback start voltage VSB, the transistor TA1 starts a clamping operation, and as shown in B3, snapback occurs in which the drain voltage drops to the hold voltage VHD. In B3, the hold voltage VHD is lower than the absolute maximum rated voltage VABS. Therefore, in a state where power is supplied to the circuit device, if such a snapback occurs, an abnormal state in which current continues to flow occurs, and the normal state cannot be restored.

  As described above, in the conventional electrostatic protection circuit, when normal operation is performed when power is supplied and the circuit device operates, noise or the like enters from the outside, and current continues to flow when the N-type transistor TA1 enters the snapback state. There is a possibility of falling into an abnormal state. In this case, if the power supply voltage is lowered to be lower than the hold voltage VHD, this abnormal state is resolved and the normal state can be restored. However, in an in-vehicle electronic device or the like, it is not desirable to stop the power supply in order to lower the power supply voltage in such an abnormal state. For this reason, in a circuit device mounted on an electronic apparatus, an ESD immunity test in which a discharge pulse is applied to a terminal or the like by a discharge gun is performed in a normal operation state where power is supplied, and an abnormal state in which current continues to flow does not occur. It is inspected.

2. First Configuration Example of Electrostatic Protection Circuit FIG. 9 shows a first configuration example of the electrostatic protection circuit of the present embodiment that can solve the above-described problems. The electrostatic protection circuit includes a trigger circuit 10 and a discharge circuit 20. The electrostatic protection circuit of this embodiment is characterized in that two or more stages of transistors are provided as discharge elements of the discharge circuit 20.

  The trigger circuit 10 includes a first power supply line PL1 to which a first power supply voltage VDD is supplied and a second power supply line PL2 to which a second power supply voltage VSS lower than the first power supply voltage VDD is supplied. Between. The discharge circuit 20 includes a first transistor T1 and a second transistor T2, at least one of which is controlled (on / off control) based on the output (QT) of the trigger circuit 10.

  The first transistor T1 and the second transistor T2 are cascade-connected between the first power supply line PL1 and the second power supply line PL2. For example, the first and second transistors T1 and T2 are connected in series between the first power supply line PL1 and the second power supply line PL2 (between VDD and VSS).

  Although FIG. 9 shows an example in which the discharge circuit 20 has two stages of transistors T1 and T2 connected in cascade, the number of transistors in the discharge circuit 20 may be three or more. Various modifications such as disposing another circuit element (for example, a diode) in the series connection path of the transistors T1 and T2 or providing a discharge element different from the transistor are possible.

  The trigger circuit 10 includes a resistor RD, a capacitor CD, and an inverter IV. Resistor RD and capacitor CD are provided in series between power supply lines PL1 and PL2. For example, one end of the resistor RD is connected to the power supply line PL1, and the other end is connected to the node ND1. One end of capacitor CD is connected to power supply line PL2, and the other end is connected to node ND1. These resistors RD and capacitor CD constitute a CR time constant circuit.

  The inverter IV has a connection node ND1 between the resistor RD and the capacitor CD as an input node, and includes a P-type transistor TD1 and an N-type transistor TD2 provided between the power supply lines PL1 and PL2. A connection node ND1 of the resistor RD and the capacitor CD is connected to the gates of the transistors TD1 and TD2. The source of the P-type transistor TD1 is connected to the power supply line PL1, and the drain is connected to the output node ND2 of the trigger signal QT. The source of N-type transistor TD2 is connected to power supply line PL2, and the drain is connected to output node ND2 of trigger signal QT.

  The trigger circuit 10 is not limited to the configuration shown in FIG. For example, the time constant circuit may be realized by using circuit elements other than the resistor RD and the capacitor CD, or may be realized by changing the connection configuration of the resistor and the capacitor. FIG. 9 shows an example in which the number of stages of the inverter IV is one, but a plurality of (odd number) stages of inverters may be provided. For example, first to Nth inverters (N is an integer of 2 or more) are provided, a connection node ND1 is connected to the input of the first inverter of the first stage, and the output (QT) of the Nth inverter of the final stage is discharged to the discharge circuit. 20 Further, the circuit configuration of the inverter IV is not limited to the configuration illustrated in FIG. 9, and may be any configuration as long as it can output at least an inverted signal of the input signal.

  In FIG. 9, the transistors T1 and T2 are N-type transistors. In other words, the discharge circuit 20 includes N-type transistors T1 and T2 cascaded between the power supply lines PL1 and PL2. Specifically, the drain of the transistor T1 is connected to the power supply line PL1, and the source is connected to the node N1. The drain of the transistor T2 is connected to the node N1, and the source is connected to the power supply line PL2. The output of the trigger circuit 10 is connected to the gates of the transistors T1 and T2. That is, the trigger signal QT from the trigger circuit 10 is input. For example, the drain of an N-type transistor is an impurity region having a higher set potential among the two impurity regions (diffusion regions) of the transistor, and the source is an impurity region having a lower set potential.

  In FIG. 9, the transistors T1 and T2 are formed in the same well (P-type well). That is, the same substrate potential (VSS) is supplied to the transistors T1 and T2.

  As will be described in detail later, the voltage obtained by adding the snapback hold voltage of the transistor T1 and the snapback hold voltage of the transistor T2 becomes larger than the voltage difference between the power supply voltage VDD and the power supply voltage VSS (GND). ing. For example, when the hold voltages in the snapback state of the transistors T1 and T2 are VHD1 and VHD2, the relationship of VHD1 + VHD2> VDD−VSS is established. It is desirable that VHD1 + VHD2> VABS when the absolute maximum rated voltage of the circuit device (transistor) is VABS.

  Next, the operation of the electrostatic protection circuit of this embodiment will be described. First, the operation of the electrostatic protection circuit in a state where power is not supplied will be described.

  For example, as an ESD event, a positive ESD surge is applied to the first power supply line PL1 with reference to the second power supply line PL2. The electric charge due to the ESD surge is charged to the capacitor CD via the resistor RD constituting the time constant circuit. Here, the value of the CR time constant determined by the resistance value of the resistor RD and the capacitance value of the capacitor CD is sufficiently large. Accordingly, the input node of the inverter IV is maintained at the L level for a period corresponding to the time constant. In a state where the input node of inverter IV is maintained at L level, trigger signal QT output from trigger circuit 10 is at H level. Accordingly, the N-type transistors T1 and T2 of the discharge circuit 20 are turned on because the H level trigger signal QT is input to the gates thereof. In this way, by releasing the surge current with the transistors T1 and T2, it is possible to suppress the breakdown of the transistors and the like of the internal circuit of the circuit device by applying a high voltage between the power supply lines PL1 and PL2. . Note that the potentials of the gates of the transistors T1 and T2 are lowered with the passage of a period defined by the time constant circuit of the resistor RD and the capacitor CD after the ESD surge is applied. Further, when a negative ESD surge is applied, electrostatic protection is realized by an electrostatic protection diode (diode DI in FIG. 22 and the like described later) provided between the VDD and VSS power supplies.

  FIG. 10 is an example of a cross-sectional view of transistors T1 and T2 (discharge elements) constituting the discharge circuit 20. As shown in FIG. 10, the transistors T1 and T2 are formed in the same P-type well PWL. That is, N-type impurity regions (diffusion regions) serving as the sources and drains of the N-type transistors T1 and T2 are formed in the P-type well PWL. The P-type well PWL is formed on, for example, an N-type well. The P-type well PWL is set to the VSS potential (substrate potential) by the P-type impurity region (DF).

  The high-potential-side power supply voltage VDD is supplied to the N-type impurity region that becomes the drain region DR1 of the transistor T1. The source region SR1 of the transistor T1 and the drain region DR2 of the transistor T2 are formed by a common N-type impurity region, for example. Note that the source region SR1 and the drain region DR2 may be formed of separate N-type impurity regions. The power supply voltage VSS (GND) on the low potential side is supplied to the source region SR2 of the transistor T2. The trigger signal QT from the trigger circuit 10 is input to the gate GT1 of the transistor T1 and the gate GT2 of the transistor T2.

  As shown in FIG. 10, parasitic NPN bipolar translators BP1 and BP2 and parasitic resistors R1, R2 and R3 are formed in the well PWL in which the transistors T1 and T2 are formed.

  The collector (C), base (B), and emitter (E) of the parasitic NPN bipolar transistor BP1 correspond to the drain (DR1), substrate (PWL), and source (SR1) of the transistor T1, respectively. The collector (C), base (B), and emitter (E) of the parasitic NPN bipolar transistor BP2 correspond to the drain (DR2), substrate (PWL), and source (SR2) of the transistor T2, respectively.

  The resistor R1 is a parasitic resistance (well resistance) formed between the base of the bipolar transistor BP1 and the base of the bipolar transistor BP2. The resistor R2 is a parasitic resistance (well resistance) formed between the base of the bipolar transistor BP2 and VSS (DF). The resistor R3 is a parasitic resistance (well resistance) formed between the base of the bipolar transistor BP1 and VSS.

  FIGS. 11A to 11C are operation explanatory diagrams of the equivalent circuit of the first configuration example of FIG. 9 when a steep surge current is input. The transistors T1 and T2 are transistors that constitute the discharge circuit 20 of the electrostatic protection circuit of FIG. 9, and are provided between the power sources of VDD and VSS (between the power supply lines PL1 and PL2).

  In FIG. 11A, since the N-type transistors T1 and T2 serving as the discharge elements have not yet been turned on, the transistors T1 and T2 are in an off state. That is, a steep surge current rising in a period shorter than the time constant period due to the resistor RD and the capacitor CD in FIG. 9 is applied, and in this state, the transistors T1 and T2 are turned off. As described with reference to FIG. 10, parasitic NPN bipolar transistors BP1 and BP2 are formed in the transistors T1 and T2. In addition, parasitic resistances R1, R2, and R3 of the well PWL serving as the substrate are also formed.

  FIG. 11B is a discharge path diagram when the drain voltage of the transistor T1 exceeds the breakdown voltage and the current IE starts to flow. The breakdown voltage is determined by the breakdown voltage between the collector and base of the NPN bipolar transistor BP1. This breakdown voltage is a breakdown voltage at the junction between the N-type impurity region serving as the drain region DR1 of the transistor T1 of FIG. 10 and the P-type well PWL. As the current IE increases, the current flows through the parasitic resistances R1, R2, and R3 serving as base resistances, thereby increasing the potentials of the base nodes NB1 and NB2 of the bipolar transistors BP1 and BP2.

  FIG. 11C is a discharge path diagram when the transistors T1 and T2 are in the snapback state. As the potentials of the base nodes NB1 and NB2 rise, the parasitic bipolar transistors BP1 and BP2 are turned on, and snapback occurs.

  FIG. 12 is a graph of IV characteristics for explaining the operations of FIGS. 11 (A) to 11 (C). As indicated by E1 in FIG. 12, when the drain voltage of the N-type transistor T1 exceeds the breakdown voltage VBD, a current starts to flow. Then, as indicated by E2, when the drain voltage exceeds the snapback start voltage VSB, the transistors T1 and T2 start the clamping operation, and snapback occurs.

  In this case, in the present embodiment, the discharge circuit 20 is configured by two-stage transistors T1 and T2 cascaded between the power lines PL1 and PL2 of VDD and VSS. Accordingly, as indicated by E3 in FIG. 12, the hold voltage VHD as a whole of the discharge circuit 20 is higher than that in the conventional example of FIG. For example, as shown in FIG. 10, the transistors T1 and T2 are formed in the same well PWL. Therefore, when the snapback hold voltage of the transistor T1 is VHD1 and the snapback hold voltage of the transistor T2 is VHD2, the overall hold voltage VHD of the discharge circuit 20 is the voltage (sum of VHD1 and VHD2). Voltage). That is, VHD = VHD1 + VHD2 is established.

  As indicated by E3 in FIG. 12, in the present embodiment, this hold voltage VHD = VHD1 + VHD2 is larger than the absolute maximum rated voltage VABS of the circuit device (IC). For example, the hold voltage VHD = VHD1 + VHD2 is at least larger than the voltage difference between the power supply voltage VDD and VSS. Therefore, it is possible to effectively avoid an abnormal state in which current continues to flow even if the transistors T1 and T2 snap back due to external noise in a normal operation where power is supplied.

  For example, after applying a surge current due to noise or the like, the voltage difference between the power supply lines PL1 and PL2 returns to VDD−VSS by the power supply of the power supply device 540 of FIG. That is, the hold voltage VHD indicated by E3 in FIG. 12 is larger than the voltage difference VDD−VSS, and thus the hold voltage VHD is not maintained. For this reason, the snapback state of the transistors T1 and T2 is canceled and the normal state is restored from the abnormal state. For example, even when a discharge pulse is applied by a discharge gun in an ESD immunity test, the snapback state is canceled and normal by the voltage difference between the power supply lines PL1 and PL2 returning to VDD-VSS after the discharge pulse is applied. Return to the state.

  On the other hand, in the conventional example of FIG. 8, even if the voltage difference between the power supply lines PL1 and PL2 returns to VDD-VSS due to the power supply of the power supply device 540 after applying a surge current due to noise or the like, it is shown as B3 in FIG. The hold voltage VHD is smaller than the voltage difference VDD−VSS. Therefore, the abnormal state in which current flows is continued without returning to the normal state.

  As described above, in the present embodiment, the hold voltage at the time of snapback can be increased by using two or more cascaded transistors as the discharge elements. For example, the hold voltage can be made higher than the absolute maximum rated voltage or the voltage difference between the power supplies. For this reason, it is possible to avoid an abnormal state in which current continues to flow even if noise or the like enters from the outside during normal operation and the transistor as the discharge element snaps back. In FIG. 9 and the like, the case where two stages of transistors are cascade-connected has been described, but three or more stages of transistors may be cascade-connected.

  In the N-type transistor, the substrate potential (well potential) rises due to the avalanche current generated by the avalanche breakdown at the end of the drain, and when the substrate potential reaches about 0.6 V, for example, the parasitic NPN bias is increased. The polar transistor is turned on. The bipolar transistor in the on state forms a low-impedance current path between the drain and source of the transistor, and a large current flows. Then, for example, the voltage drops to a hold voltage (sustain voltage) determined by the product of the collector-emitter resistance of the bipolar transistor and the collector current. This phenomenon is called snapback. In the present embodiment, by using cascaded two-stage (two or more stages) transistors as the discharge elements of the discharge circuit, the hold voltage as a whole of the discharge circuit is increased. For example, two stages of transistors are formed in the same well, and a parasitic bipolar transistor is formed for each transistor. That is, since a two-stage bipolar transistor is formed corresponding to the two-stage transistor, the hold voltage determined by the product of the collector-emitter resistance of the bipolar transistor and the collector current is also two stages. Accordingly, the hold voltage as a whole of the discharge circuit is a hold voltage for two stages, for example, higher than the power supply voltage difference VDD-VSS. Therefore, after the surge current due to noise or the like is applied, the voltage difference between the power supply lines returns to VDD-VSS, so that the snapback state of the transistor is canceled and the normal state is restored. Thus, in this embodiment, it has succeeded in suppressing the generation | occurrence | production of the abnormal state by snapback resulting from the external noise etc. at the time of normal operation.

3. Various configuration examples of the electrostatic protection circuit The electrostatic protection circuit of the present embodiment can be variously modified. For example, FIG. 13 shows a second configuration example of the electrostatic protection circuit of this embodiment. The difference from the first configuration example of FIG. 9 is the configuration of the discharge circuit 20, and the configuration of the trigger circuit 10 is the same as that of FIG.

  That is, in the first configuration example of FIG. 9, the output (QT) of the trigger circuit 10 is input to both the gate of the transistor T1 and the gate of the transistor T2.

  On the other hand, in the second configuration example of FIG. 13, the gate of T1, which is one of the transistors T1 and T2, is connected to the power supply line PL1, and the output of the trigger circuit 10 is connected to the gate of the other transistor T2. Have been entered. That is, the power supply line PL1 of the power supply voltage VDD is connected to the gate of the N-type transistor T1, and the output of the trigger circuit 10 is input to the gate of the N-type transistor T2 as in FIG.

  FIG. 14A to FIG. 14C are operation explanatory diagrams of an equivalent circuit of the second configuration example of FIG. 13 when a steep surge current is input.

  In FIG. 14A, the N-type transistor T2 as a discharge element has not yet been turned on, and thus the transistor T2 is in an off state. The transistors T1 and T2 are formed with parasitic NPN bipolar transistors BP1 and BP2 and parasitic resistors R1, R2, and R3, as in the case of FIGS. 11A to 11C.

  FIG. 14B is a discharge path diagram when the drain voltage of the transistors T1 and T2 exceeds the breakdown voltage and the current IE starts to flow. Since the transistors T1 and T2 are formed in the same well, a current flows simultaneously. For example, as a current path of the current IE, a path of the current IE1 via the N-type transistor T1 which is turned on by connecting the VDD power line PL1 to the gate, and only through the resistors R1, R2, and R3 There is a path for the current IE2.

  FIG. 14C is a discharge path diagram when the transistors T1 and T2 are in the snapback state. As the potentials of the base nodes NB1 and NB2 rise, the parasitic bipolar transistors BP1 and BP2 are turned on, and snapback occurs.

  FIG. 15 is a graph of IV characteristics for explaining the operations of FIGS. 14 (A) to 14 (C). As shown in F1 of FIG. 15, when the drain voltage exceeds the breakdown voltage VBD, current starts to flow. As shown in F2, when the drain voltage exceeds the snapback start voltage VSB, the transistors T1 and T2 perform the clamping operation. Start and snapback occurs.

  As shown in FIG. 14B, in this second configuration example, since there are two current paths of currents IE1 and IE2, the snapback start current ISB is shown in FIG. It has increased compared to E2. For this reason, as indicated by F3 in FIG. 15, the hold voltage VHD also increases as compared with E3 in FIG. 12, and the voltage difference from the absolute maximum rated voltage VABS increases, thereby reducing the risk of malfunction.

  Further, in the third configuration example of FIG. 13, the gate of one transistor T <b> 2 is connected to the output of the inverter IV of the trigger circuit 10 among the cascaded discharge elements. The transistor T1 that is not connected to the output of the inverter IV is gate-connected so as to be turned on. Accordingly, since the parasitic capacitance of the output of the inverter IV is reduced, the size and the like of the transistors TD1 and TD2 of the inverter IV can be reduced.

  FIG. 16 shows a third configuration example of the electrostatic protection circuit. In the second configuration example of FIG. 13, the gate of the high-potential side transistor T1 is connected to the VDD power line PL1, and the gate of the low-potential side transistor T2 is connected to the output of the trigger circuit 10. On the other hand, in the third configuration example of FIG. 16, the gate of the low potential side transistor T2 is connected to the VDD power line PL1, and the gate of the high potential side transistor T1 is connected to the output of the trigger circuit 10. Others are the same as in the second configuration example of FIG. As described above, in FIGS. 13 and 16, the gate of one of the transistors T1 and T2 is connected to the power supply line PL1, and the gate of the other transistor is connected to the output of the trigger circuit 10.

  FIG. 17A to FIG. 17C are operation explanatory diagrams of the equivalent circuit of the third configuration example of FIG. 16 when a steep surge current is input.

  In FIG. 17A, the N-type transistor T1 as a discharge element has not yet been turned on, and thus the transistor T1 is in an off state.

  FIG. 17B is a discharge path diagram when the drain voltage of the transistor T1 exceeds the breakdown voltage and the current IE starts to flow. Since the transistors T1 and T2 are formed in the same well, a current flows simultaneously.

  FIG. 17C is a discharge path diagram when the transistors T1 and T2 are in the snapback state. As the potentials of the base nodes NB1 and NB2 rise, the parasitic bipolar transistors BP1 and BP2 are turned on, and snapback occurs.

  Note that the IV characteristic graph for explaining the operations of FIGS. 17A to 17C is the same as FIG.

  FIG. 18 shows a fourth configuration example of the electrostatic protection circuit. In FIG. 18, the N-type transistors T1 and T2 in FIG. 9 are replaced with P-type transistors TP1 and TP2. That is, in FIG. 9, the discharge circuit 20 is composed of two stages of cascade-connected N-type transistors T1 and T2, but in FIG. 18, two stages of cascade-connected P-type transistors TP1 and TP2 It is comprised by.

  Further, in FIG. 18, in order to match the polarity of the operation of the trigger circuit 10, the connection order of the resistor RD and the capacitor CD is different from that in FIG. That is, in FIG. 9, the resistor RD is provided between the VDD power line PL1 and the connection node ND1, and the capacitor CD is provided between the connection node ND1 and the VSS power line PL2. On the other hand, in FIG. 18, the capacitor CD is provided between the VDD power line PL1 and the connection node ND1, and the resistor RD is provided between the connection node ND1 and the VSS power line PL2.

  FIG. 19A to FIG. 19C are operation explanatory diagrams of an equivalent circuit of the fourth configuration example of FIG. 18 when a steep surge current is input.

  In FIG. 19A, since the P-type transistors TP1 and TP2 serving as the discharge elements are not turned on, the transistors TP1 and TP2 are in an off state. The transistors TP1 and TP2 are formed with parasitic PNP bipolar transistors BP3 and BP4 and parasitic resistors R4, R5, and R6.

  FIG. 19B is a discharge path diagram when the drain voltage of the transistor TP2 exceeds the breakdown voltage and the current IE starts to flow.

  FIG. 19C is a discharge path diagram when the transistors TP1 and TP2 are in the snapback state. In FIG. 19C, the parasitic PNP bipolar transistors BP3 and BP4 are turned on, and snapback occurs.

  FIG. 20 shows a fifth configuration example of the electrostatic protection circuit. In FIG. 20, the N-type transistor T1 of FIG. 9 is replaced with a P-type transistor TP1, and the gate of the transistor TP1 is connected to the VSS power supply line PL1. The output of the trigger circuit 10 is input to the gate of the N-type transistor T2 as in FIG.

  FIG. 21 shows a sixth configuration example of the electrostatic protection circuit. In FIG. 20, the N-type transistor T1 of FIG. 9 is replaced with a P-type transistor TP1, and the gate of the transistor TP1 is connected to the node N1. That is, the transistor TP1 is diode-connected. The output of the trigger circuit 10 is input to the gate of the N-type transistor T2 as in FIG.

  As described above, in the electrostatic protection circuit of the present embodiment, as shown in the fourth, fifth, and sixth configuration examples of FIGS. 18, 20, and 21, the first, At least one of the second transistors may be a P-type transistor.

  Furthermore, in the fifth and sixth configuration examples of FIGS. 20 and 21, the first transistor of the cascaded first and second transistors is a P-type transistor TP1, and the second transistor is N Type transistor T2. The output of the trigger circuit 10 is input to the gate of the N-type transistor T2.

  As described above, in this embodiment, a P-type transistor (PMOS) and an N-type transistor (NMOS) may be mixed to form a cascade connection. Then, at least one of the first and second transistors is connected to the output of the trigger circuit 10 (inverter IV). A transistor as a discharge element that is not connected to the trigger circuit 10 may be connected to the power supply line PL2 (PL1) so that its gate is turned on.

4). Layout Arrangement Next, various layout arrangement examples of this embodiment will be described. Here, a layout arrangement example of the N-type transistors T1 and T2 constituting the discharge circuit 20 of FIG. 9 and the like will be described.

  FIG. 22 shows a first layout arrangement example of the present embodiment. In the following, the direction orthogonal (crossing) the first direction D1 is the second direction D2, the opposite direction of the first direction D1 is the third direction D3, and the opposite direction of the second direction D2 Is a fourth direction D4. For example, in FIG. 22, the first, second, third, and fourth directions D1, D2, D3, and D4 are the right direction, the upward direction, the left direction, and the downward direction, respectively.

  In FIG. 22, the gate GT1 of the transistor T1 and the gate GT2 of the transistor T2 are arranged along the D1 direction with the D2 direction as the longitudinal direction. The region where the transistors T1 and T2 are disposed is surrounded by a P-type impurity region (DF). This impurity region is a well potential setting (substrate potential setting) impurity region (diffusion region) called a guard bar (guard ring). The P-type impurity region (DF) causes the P-type well to be VSS. The potential (substrate potential) is set. The power supply voltage VSS is supplied to the P-type impurity region for setting the well potential from the upper metal wirings MLB3 and MLB5 through a through hole (metal wiring formed in the through hole; the same applies hereinafter).

  The drain region DR1 of the transistor T1 is disposed (formed) on the D1 direction side (right side) of the left P-type impurity region (DF) in FIG. A gate GT1 of the transistor T1 is disposed on the D1 direction side of the drain region DR1. A source region SR1 of the transistor T1 is disposed on the D1 direction side of the gate GT1. In the drain region DR1, the gate GT1, and the source region SR1, the direction D2 is the longitudinal direction.

  The power supply voltage VDD is supplied to the drain region DR1 of the transistor T1 from the upper metal wirings MLB2 and MLB4 through a through hole or the like. On the other hand, the power source voltage VSS is supplied to the source region SR2 of the transistor T2 from the upper metal wirings MLB3 and MLB5 through a through hole or the like.

  A gate GT2 of the transistor T2 is formed on the D1 direction side of the source region SR1 of the transistor T1. Note that the drain region DR2 of the transistor T2 is an impurity region (diffusion region) common to the source region SR1 of the transistor T1. A source region SR2 of the transistor T2 is formed on the D1 direction side of the gate GT2 of the transistor T2. A gate GT2 of the transistor T2 is formed on the D1 direction side of the source region SR2. A drain region DR2 of the transistor T2 is formed on the D1 direction side of the gate GT2. The drain region DR2 is an impurity region common to the source region SR1 of the adjacent transistor T1 on the D1 direction side.

  In FIG. 22, the transistors T1 and T2 are laid out by repeating the above arrangement pattern. The gates GT1 and GT2 of the transistors T1 and T2 are commonly connected by an upper metal wiring MLB1 (trigger signal QT).

  FIG. 23 is a diagram showing an equivalent circuit of the transistors T1 and T2 in the layout arrangement of FIG. 22 and 23, the first transistor T1 includes a plurality of first unit transistors T11, T12, T13, and T14. The second transistor T2 includes a plurality of second unit transistors T21, T22, T23, and T24.

  For example, the four gates GT1 in FIG. 22 correspond to the gates of the first unit transistors T11, T12, T13, and T14 in FIG. The four gates GT2 in FIG. 22 correspond to the gates of the second unit transistors T21, T22, T23, and T24 in FIG.

  For example, the first gate GT1 from the left in FIG. 22 is the gate of the first unit transistor T11, and the second gate GT2 adjacent to the right is the gate of the second unit transistor T21. The source (SR1) of the first unit transistor T11 and the drain (DR2) of the second unit transistor T21 form a common impurity region and are electrically connected.

  The third gate GT2 from the left in FIG. 22 is the gate of the second unit transistor T22, and the fourth gate GT1 adjacent to the right is the gate of the first unit transistor T12. The source (SR1) of the first unit transistor T12 and the drain (SR2) of the second unit transistor T22 form a common impurity region and are electrically connected. The layout of the other first unit transistors T13 and T14 and the second unit transistors T23 and T24 is the same.

  22 and FIG. 23, each first unit transistor of the plurality of first unit transistors T11, T12, T13, and T14 corresponds to one of the plurality of second unit transistors T21, T22, T23, and T24. It is connected to one second unit transistor and is not connected to the other second unit transistor. That is, the nodes N11, N12, N13, and N14 are not commonly connected but are separated.

  For example, the source of the first unit transistor T11 is connected to the drain of the corresponding second unit transistor T21, and is not connected to the drains of the other second unit transistors T22, T23, T24. The source of the first unit transistor T12 is connected to the drain of the corresponding second unit transistor T22, and is not connected to the drains of the other second unit transistors T21, T23, T24. The connection relationship between the first unit transistors T13 and T14 and the second unit transistors T23 and T24 is the same.

  As shown in FIG. 23, in the electrostatic protection circuit of the present embodiment, a diode DI having a forward direction from VSS to VDD is formed. The diode DI functions as a diode for electrostatic protection against, for example, a negative ESD surge.

  For example, in FIG. 22, the transistors T1 and T2 are arranged so that the well region setting impurity region DF faces the drain region DR1 of the transistor T1. The diode DI of FIG. 23 is realized by making the P-type impurity region DF for setting the well potential and the N-type drain region DR1 of the transistor T1 face each other as described above.

  For example, FIG. 24 is a diagram schematically showing a cross-sectional view taken along line G1 in FIG. As shown in FIG. 24, the power supply voltage VSS on the low potential side is transferred from the upper metal wiring MLB to the P-type impurity region DF for setting the well potential through the through hole TH, the lower metal wiring MLA, and the contact CN. Supplied. The power supply voltage VDD on the high potential side is transferred from the upper metal wiring MLB to the N-type drain region DR1 (N-type impurity region) of the transistor T1 through the through hole TH, the lower metal wiring MLA, and the contact CN. Supplied. A diode DI having a forward direction from VSS to VDD is formed by the P-type impurity region DF for setting the well potential and the N-type drain region DR1. Specifically, the diode DI is formed by the junction surface between the drain region DR1 and the P-type well PWL.

  In FIG. 22, the transistor is set such that the P-type impurity region DF for setting the well potential whose longitudinal direction is the D2 direction and the N-type drain region DR1 of the transistor T1 whose longitudinal direction is the same D2 direction. The unit transistors T1 and T2 are laid out. That is, the layout is arranged so that the drain region DR1 of the unit transistor of the transistor T1 is located outside the transistor arrangement region. This layout arrangement is realized by arrangement of through holes in the upper metal wirings MLB2 and MLB4 that supply the power supply voltage VDD. For example, by forming the through hole corresponding to the leftmost impurity region of the transistor arrangement region, the impurity region is formed as the drain region of the transistor T1, and the diode DI depicted on the left side of FIG. 22 is formed. To do. Further, by forming the through hole corresponding to the rightmost impurity region of the transistor arrangement region, the impurity region is formed as the drain region of the transistor T1, and the diode DI depicted on the right side of FIG. 22 is formed. .

  By adopting such a layout arrangement, it is possible to increase the junction area of the diode DI. That is, the junction area of the diode DI is increased by making the P-type impurity region DF for setting the well potential and the drain region DR1 of the transistor T1 face each other over a long distance in the direction D2, which is the longitudinal direction. Thus, the performance such as ESD withstand voltage can be improved.

  FIG. 25 shows a second layout arrangement example of the present embodiment. The second layout arrangement example of FIG. 25 is basically the same layout arrangement as FIG. In FIG. 25, the transistor arrangement region is divided into a first region and a second region, and a P-type impurity region DF for setting a well potential is formed between the first region and the second region. It arrange | positions so that D2 direction may become a longitudinal direction. By doing so, the central P-type impurity region DF can be opposed to the drain region DR1 of the transistor T1. As a result, the two diodes DI depicted in the central part of FIG. 25 can be formed as new diodes not shown in FIG. Therefore, compared with FIG. 22, the area of the junction surface of the diode DI can be further increased, and the performance such as ESD withstand voltage can be further improved.

  FIG. 26 shows a third layout arrangement example of the present embodiment. In the third layout arrangement of FIG. 26, unlike FIG. 22 and FIG. 25, among the transistors T1 connected in cascade, the transistor T1 is arranged in the first region RG1, and the transistor T2 is arranged in the first region RG1. Are arranged in different second regions RG2. Specifically, a plurality of first unit transistors constituting the transistor T1 are arranged in the first region RG1, and a plurality of second unit transistors constituting the transistor T2 are arranged in the second region RG2. ing.

  Also in the layout arrangement of FIG. 26, the drain region DR1 of at least one unit transistor of the plurality of first unit transistors constituting the transistor T1 is arranged so as to face the impurity region DF for setting the well potential. ing. As a result, a diode DI having a forward direction from VSS to VDD is realized.

  FIG. 27 is a diagram showing an equivalent circuit of the transistors T1 and T2 in the layout arrangement of FIG. 26 and 27, the first transistor T1 includes a plurality of first unit transistors T11, T12, T13, and T14, and the second transistor T2 includes a plurality of second unit transistors T21, T22, It is comprised by T23 and T24. The sources of the plurality of first unit transistors T11, T12, T13, and T14 and the drains of the plurality of second unit transistors T21, T22, T23, and T24 are connected in common. That is, in FIG. 23, the nodes N11, N12, N13, and N14 are separated, but in FIG. 24, the sources of the first unit transistors T11, T12, T13, and T14 of the transistor T1 and the second of the transistor T2 The sources of the unit transistors T21, T22, T23, and T24 are commonly connected to the node N1.

  The first gate GT1 from the left in FIG. 26 is the gate of the first unit transistor T11, and the second gate GT1 adjacent to the right is the gate of the first unit transistor T12. The source region SR1 of the first unit transistor T11 and the source region SR1 of the first unit transistor T12 are formed by a common impurity region. Similarly, the third and fourth gates GT1 are the gates of the first unit transistors T13 and T14. The source region SR1 of the first unit transistors T13 and T14 is formed by a common impurity region.

  The fifth gate GT2 from the left is the gate of the second unit transistor T21, and the sixth gate GT2 adjacent to the right is the gate of the second unit transistor T22. The drain region DR2 of the second unit transistor T21 and the drain region DR2 of the second unit transistor T22 are formed by a common impurity region. Similarly, the seventh and eighth gates GT2 are the gates of the second unit transistors T23 and T24. The drain regions DR2 of these second unit transistors T23 and T24 are formed by a common impurity region.

  The gates GT1 and GT2 of the transistors T1 and T2 are commonly connected to the upper metal wiring MLB1. The power supply voltage VDD is supplied to the drain region DR1 of the transistor T1 from the upper metal wiring MLB2 and MLB4 through a through hole or the like. The power source voltage VSS is supplied to the source region SR2 of the transistor T2 from the upper metal wirings MLB3 and MLB5 through a through hole or the like.

  Further, the source region SR1 of the transistor T1 and the drain region DR2 of the transistor T2 are electrically connected using upper metal wirings MLB6 and MLB7, through holes, and the like. That is, in FIG. 27, the source region SR1 of the first unit transistors T11, T12, T13, and T14 that constitute the transistor T1, and the drain region DR2 of the second unit transistors T21, T22, T23, and T24 that constitute the transistor T2 are Are electrically connected using metal wiring MLB6, MLB7 (node N1), and the like.

  In FIG. 26, on the left side of the first region RG1, the N-type drain region DR1 of the transistor T1 and the P-type impurity region DF for setting the well potential are opposed to each other with the direction D2 as the longitudinal direction. Thus, a diode DI for electrostatic protection is realized. Similarly, on the right side of the first region RG1, with the direction D2 as the longitudinal direction, the N-type drain region DR1 of the transistor T1 and the P-type impurity region DF for setting the well potential are opposed to each other. A diode DI for electrostatic protection is realized.

  FIG. 28 shows a fourth layout arrangement example of the present embodiment. FIG. 28 shows a layout arrangement almost the same as FIG. 26, and the difference is the number of unit transistors formed in a region surrounded by a P-type impurity region (DF). That is, in FIG. 26, the number of unit transistors constituting each of the transistors T1 and T2 is four, but is three in FIG. For example, in FIG. 26, four gates GT1 corresponding to the four unit transistors of the transistor T1 and four gates GT2 corresponding to the four unit transistors of the transistor T2 are arranged, for a total of eight gates. Has been placed. In contrast, in FIG. 28, three gates GT1 corresponding to the three unit transistors of the transistor T1 and three gates GT2 corresponding to the three unit transistors of the transistor T2 are arranged, for a total of six. The gate is arranged.

  For example, in the first and second layout arrangements of FIGS. 22 and 25, the equivalent circuit is as shown in FIG. Therefore, for example, when the unit transistor T11 in FIG. 23 has a failure, not only the unit transistor T11 but also the unit transistor T21 connected thereto cannot contribute to electrostatic protection. Similarly, when there is a failure in the unit transistor T21, not only the unit transistor T21 but also the unit transistor T11 cannot contribute to electrostatic protection. The same applies to the relationship between the other unit transistors T12 to T14 and T21 to T24.

  On the other hand, in the third and fourth layout arrangements of FIGS. 26 and 28, the equivalent circuit is as shown in FIG. For this reason, for example, even when the unit transistor T11 of FIG. 27 has a failure, the unit transistor T21 can contribute to electrostatic protection. Similarly, when the unit transistor T21 has a failure, the unit transistor T11 can contribute to electrostatic protection. The same applies to the other unit transistors. Therefore, in this respect, the layout arrangement of FIG. 26 and FIG. 28 is more advantageous than FIG. 22 and FIG.

  In the layout arrangements of FIGS. 26 and 28, an even number of unit transistors (even number of gates) can be arranged in each region of RG1 and RG2, and an odd number of unit transistors (odd number of gates) can be arranged. It can also be arranged. For example, FIG. 26 shows an example in which an even number (four) of unit transistors (even number of gates) are arranged in each region, and FIG. 28 shows an odd number (three) of unit transistors (odd number) in each region. This is an example in which a gate of a book is arranged. Therefore, FIG. 26 and FIG. 28 also have an advantage that the degree of freedom of layout arrangement is high. That is, the degree of freedom in design is improved and optimal design is possible.

5. Electronic Device FIG. 29 shows a configuration example of an electronic device to which the circuit device 200 of this embodiment is applied. The electronic device includes a circuit device 200, a processing unit 300, a storage unit 310, an operation unit 320, a bus 340, and a display unit 350.

  The processing unit 300 performs various processes such as a control process for an electronic device, and can be realized by a processor such as a CPU or a logic circuit generated by an automatic placement and routing technique such as a gate array. The storage unit 310 stores various data and programs, and can be realized by, for example, a RAM or a ROM. The operation unit 320 is for inputting various types of information and can be realized by an operation key, a touch panel, or the like. The display unit 350 is for displaying various types of information and can be realized by, for example, a liquid crystal display, an organic EL display, or the like.

  The circuit device 200 performs display control of the display unit 350, for example. An example of the circuit device 200 is a display driver that controls display of a liquid crystal display, for example. The circuit device 200 is provided with a plurality of electrostatic protection circuits PC1, PC2, PC3... Described in the present embodiment. These electrostatic protection circuits PC1, PC2, PC3... Are protection circuits provided between the power supplies of the circuit device 200. For example, the circuit device 200 outputs a plurality of source signals to a display panel (liquid crystal display panel or the like) that is the display unit 350, and effectively uses a region below the output pad that is an output terminal of the source signal. Thus, each electrostatic protection circuit of PC1, PC2, PC3... Can be arranged.

  By providing such electrostatic protection circuits PC1, PC2, PC3..., ESD performance of the circuit device 200 can be improved, and reliability and the like can be improved. For example, when the electronic device is an in-vehicle electronic device, even if an abnormal state due to snapback occurs due to external noise or the like, the abnormality is not performed without stopping the power supply to the circuit device 200 or the like. Can return from normal to normal. Therefore, it is possible to realize an electronic device and a circuit device 200 suitable for in-vehicle use.

  Although the present embodiment has been described in detail as described above, it will be easily understood by those skilled in the art that many modifications can be made without departing from the novel matters and effects of the present invention. Accordingly, all such modifications are intended to be included in the scope of the present invention. For example, a term described at least once together with a different term having a broader meaning or the same meaning in the specification or the drawings can be replaced with the different term in any part of the specification or the drawings. All combinations of the present embodiment and the modified examples are also included in the scope of the present invention. The configurations and operations of the electrostatic protection circuit, the circuit device, and the electronic device are not limited to those described in this embodiment, and various modifications can be made.

PL1 first power line, PL2 second power line,
T1, TP1 first transistor, T2, TP2 second transistor,
RD resistor, CD capacitor, IV inverter,
BP1-BP4 bipolar transistor, R1-R6 resistors,
GT1, GT2 gate, SR1, SR2 source region, DR1, DR2 drain region,
DF well potential setting impurity region, DI diode,
10 trigger circuit, 20 discharge circuit,
200 circuit devices, 210 internal circuits, 250 electronic devices,
300 processing unit, 310 storage unit, 320 operation unit, 340 bus, 350 display unit

Claims (15)

  1. A trigger circuit provided between a first power supply line to which a first power supply voltage is supplied and a second power supply line to which a second power supply voltage lower than the first power supply voltage is supplied;
    A discharge circuit having a first transistor and a second transistor, at least one of which is controlled based on the output of the trigger circuit;
    Including
    The first transistor and the second transistor are cascade-connected between the first power line and the second power line,
    Well impurity region for potential setting, the first so as to face the drain region of the transistor, the static electricity protection circuit, characterized in that the said first transistor second transistor is arranged.
  2. A trigger circuit provided between a first power supply line to which a first power supply voltage is supplied and a second power supply line to which a second power supply voltage lower than the first power supply voltage is supplied;
    A discharge circuit having a first transistor and a second transistor, at least one of which is controlled based on the output of the trigger circuit;
    Including
    The first transistor and the second transistor are cascade-connected between the first power line and the second power line,
    The first transistor includes a plurality of first unit transistors,
    The second transistor includes a plurality of second unit transistors,
    The electrostatic protection circuit, wherein the sources of the plurality of first unit transistors and the drains of the plurality of second unit transistors are connected in common.
  3. In claim 2,
    The plurality of first unit transistors are disposed in a first region,
    The electrostatic protection circuit, wherein the plurality of second unit transistors are arranged in a second region different from the first region.
  4. In claim 2 or 3,
    An electrostatic protection circuit, wherein a drain region of at least one unit transistor of the plurality of first unit transistors is arranged to face an impurity region for setting a well potential.
  5. A trigger circuit provided between a first power supply line to which a first power supply voltage is supplied and a second power supply line to which a second power supply voltage lower than the first power supply voltage is supplied;
    A discharge circuit having a first transistor and a second transistor, at least one of which is controlled based on the output of the trigger circuit;
    Including
    The first transistor and the second transistor are cascade-connected between the first power line and the second power line,
    The first transistor includes a plurality of first unit transistors,
    The second transistor includes a plurality of second unit transistors,
    Each first unit transistor of the plurality of first unit transistors is connected to one corresponding second unit transistor of the plurality of second unit transistors, and the other second unit transistors are An electrostatic protection circuit characterized by being disconnected.
  6. In any one of Claims 1 thru | or 5,
    A voltage obtained by adding the snapback hold voltage of the first transistor and the snapback hold voltage of the second transistor is larger than a voltage difference between the first power supply voltage and the second power supply voltage. An electrostatic protection circuit characterized by that.
  7. In any one of Claims 1 thru | or 6.
    The electrostatic protection circuit according to claim 1, wherein the first transistor and the second transistor are formed in the same well.
  8. In any one of Claims 1 thru | or 7,
    The electrostatic protection circuit according to claim 1, wherein the first transistor and the second transistor are N-type transistors.
  9. In claim 8,
    An electrostatic protection circuit, wherein an output of the trigger circuit is input to a gate of the first transistor and a gate of the second transistor.
  10. In claim 8,
    The gate of one transistor of the first transistor and the second transistor is connected to the first power supply line, and the output of the trigger circuit is input to the gate of the other transistor. ESD protection circuit.
  11. In any one of Claims 1 thru | or 7,
    An electrostatic protection circuit, wherein at least one of the first transistor and the second transistor is a P-type transistor.
  12. In any one of Claims 1 thru | or 6.
    The first transistor is a P-type transistor, the second transistor is an N-type transistor,
    An electrostatic protection circuit, wherein an output of the trigger circuit is input to a gate of the N-type transistor.
  13. In any one of Claims 1 to 12,
    The trigger circuit is
    A resistor and a capacitor provided in series between the first power supply line and the second power supply line;
    An inverter having a connection node of the resistor and the capacitor as an input node;
    An electrostatic protection circuit comprising:
  14.   A circuit device comprising the electrostatic protection circuit according to claim 1.
  15.   An electronic apparatus comprising the circuit device according to claim 14.
JP2015039014A 2015-02-27 2015-02-27 Electrostatic protection circuit, circuit device and electronic device Active JP6589296B2 (en)

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JPH0897362A (en) * 1994-09-28 1996-04-12 Nittetsu Semiconductor Kk Power supply protection circuit of semiconductor integrated circuit
JP4000096B2 (en) * 2003-08-04 2007-10-31 株式会社東芝 ESD protection circuit
JP2005260039A (en) * 2004-03-12 2005-09-22 Matsushita Electric Ind Co Ltd Semiconductor integrated circuit device
JP2010010419A (en) * 2008-06-27 2010-01-14 Nec Electronics Corp Semiconductor device
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