JP6539372B2 - Liquid crystal display - Google Patents

Description

  Embodiments of the present invention relate to a liquid crystal display device.

  In recent years, a liquid crystal display device using a horizontal electric field (including a fringe electric field) such as an IPS (In-Plane Switching) mode or an FFS (Fringe Field Switching) mode has been put to practical use. Such a liquid crystal display device in a transverse electric field mode includes a pixel electrode and a common electrode formed on one of the substrates.

  In such a horizontal electric field mode liquid crystal display device, the characteristics of the pixels of each color display are made uniform by the configuration in which the pixels of each color have different pixel areas for each color and the area ratio of the pixel electrode to each pixel area is different Technology is known. In addition to the red, green, and blue subpixels, a white subpixel is added, and the area of each of the red and blue subpixels is approximately twice that of each of the green and white subpixels. There is known a technique for reducing the decrease in resolution without increasing the number of wirings by applying a layout in which the number of each sub-pixel is twice that of each of the red and blue sub-pixels.

JP, 2009-109820, A JP 2012-118538 A

  An object of the present embodiment is to provide a liquid crystal display device capable of improving display quality.

According to this embodiment,
First and second switching elements, a gate wiring extending in a first direction and electrically connected to the first and second switching elements, and a second extending in a second direction intersecting the first direction A first source line electrically connected to the switching element, and extending in the second direction, spaced apart from the first source line in the first direction, and electrically connected to the second switching element A first contact portion electrically connected to the first switching element, and a first strip-shaped electrode having a first length extending in the second direction from the first contact portion; A second strip-shaped electrode having a second length different from the first length and extending in the second direction from one pixel electrode, a second contact portion electrically connected to the second switching element, and the second contact portion With And a second substrate facing the first substrate, wherein the gate wiring is separated from the second strip electrode at a position corresponding to the second pixel electrode. The second source line is located between the first contact portion and the second contact portion, and the first contact portion and the second contact portion are A display device is provided, which is disposed in the second direction in a plan view.
According to this embodiment,
A first gate line extending in a first direction, and a second gate line extending in the first direction and spaced apart in a second direction intersecting the first direction with the first gate line; A source wiring extending in the second direction, a first switching element electrically connected to the first gate wiring and the source wiring, and a second electrically connected to the second gate wiring and the source wiring A first pixel electrode having a switching element, a first contact portion electrically connected to the first switching element, and a first strip-shaped electrode having a first length extending in the second direction from the first contact portion A second contact portion electrically connected to the second switching element, and a second strip electrode having a second length different from the first length and extending in the second direction from the second contact portion; 2 pixel electrode , And a second substrate facing the first substrate, wherein the first gate line is disposed between the first pixel electrode and the second pixel electrode, A display device is provided, which has a bending portion bent toward a second pixel electrode, and the first length is longer than the second length.

FIG. 1 is a view schematically showing a configuration and an equivalent circuit of a liquid crystal display panel LPN which constitutes a display device of the present embodiment. FIG. 2 is a schematic plan view of the first configuration example of the pixels in the array substrate AR shown in FIG. 1 as viewed from the opposite substrate side. FIG. 3 is a plan view schematically showing a structural example of the switching elements SW2 and SW3 shown in FIG. FIG. 4 is a plan view schematically showing an example of the layout of each pixel and a color filter in the present embodiment. FIG. 5 is a cross sectional view schematically showing a configuration of a liquid crystal display panel LPN including the pixels PX1 to PX6 shown in FIG. FIG. 6 is a schematic plan view of the second configuration example of the pixels in the array substrate AR shown in FIG. 1 as viewed from the opposite substrate side. FIG. 7 is a schematic plan view of the third configuration example of the pixels in the array substrate AR shown in FIG. 1 as viewed from the opposite substrate side.

  Hereinafter, the present embodiment will be described in detail with reference to the drawings. In the drawings, components having the same or similar functions are denoted by the same reference numerals, and redundant description will be omitted.

  FIG. 1 is a view schematically showing a configuration and an equivalent circuit of a liquid crystal display panel LPN which constitutes the liquid crystal display device of the present embodiment.

  That is, the liquid crystal display device includes an active matrix type liquid crystal display panel LPN. The liquid crystal display panel LPN includes an array substrate AR as a first substrate, a counter substrate CT as a second substrate disposed opposite to the array substrate AR, and a liquid crystal layer held between the array substrate AR and the counter substrate CT. And LQ. The liquid crystal display panel LPN has an active area ACT for displaying an image. The active area ACT corresponds to a region in which the liquid crystal layer LQ is held between the array substrate AR and the counter substrate CT, and has, for example, a rectangular shape, and is constituted by a plurality of pixels PX arranged in a matrix. .

  The array substrate AR includes gate wirings G (G1 to Gn), source wirings S (S1 to Sm), switching elements SW, pixel electrodes PE, common electrodes CE, and the like in the active area ACT. The gate wirings G (G1 to Gn) extend substantially along the first direction X, respectively, and are arranged in the second direction Y intersecting the first direction X. The source lines S (S1 to Sm) extend substantially in the second direction Y and are arranged in the first direction X, respectively. The gate wiring G and the source wiring S may be bent in accordance with the pixel layout or the pixel shape as described later. The switching element SW is electrically connected to the gate line G and the source line S in each pixel PX. The pixel electrode PE is electrically connected to the switching element SW in each pixel PX. The common electrode CE is commonly formed across the plurality of pixels PX in the active area ACT, and faces the respective pixel electrodes PE. The storage capacitance CS is formed, for example, between the common electrode CE and the pixel electrode PE.

  Each gate line G is drawn out of the active area ACT and connected to the first drive circuit GD. Each source wire S is drawn out of the active area ACT and connected to the second drive circuit SD. For example, at least a part of the first drive circuit GD and the second drive circuit SD is formed on the array substrate AR, and is connected to the drive IC chip 2. The drive IC chip 2 incorporates a controller that controls the first drive circuit GD and the second drive circuit SD, and functions as a signal supply source that supplies signals necessary to drive the liquid crystal display panel LPN. In the illustrated example, the drive IC chip 2 is mounted on the array substrate AR outside the active area ACT. The common electrode CE is drawn to the outside of the active area ACT, and is connected to the feeding portion VS. The feeding portion VS supplies a common potential to the common electrode CE.

  FIG. 2 is a schematic plan view of the first configuration example of the pixels in the array substrate AR shown in FIG. 1 as viewed from the opposite substrate side. Here, although the pixel structure to which the transverse electric field mode is applied is described as an example, only the main parts necessary for the description are illustrated in the drawing.

  The array substrate AR includes gate lines G1 to G2, source lines S1 to S4, switching elements SW1 to SW6, a common electrode CE, pixel electrodes PE1 to PE6, a first alignment film AL1, and the like.

  The gate lines G1 to G2 extend along the first direction X, respectively. The source lines S1 to S4 extend substantially along the second direction Y, and intersect the gate lines G1 to G2. The pitch PT1 of the source wiring S1 and the source wiring S2 and the pitch PT2 of the source wiring S2 and the source wiring S3 are substantially equal. The pitch PT3 between the source wiring S3 and the source wiring S4 is larger than the pitch PT1 and the pitch PT2.

  The pixels PX1 to PX3 arranged in the first direction X are color pixels of different colors, and the pixels PX4 to PX6 are also color pixels of different colors. The pixels PX1 and PX4 arranged in the second direction Y are pixels of the same color, for example, red (R) pixels. The pixels PX2 and PX5 arranged in the second direction Y are pixels of the same color, for example, green (G) pixels. The pixels PX3 and PX6 arranged in the second direction Y are pixels of different colors, for example, the pixel PX3 is a blue (B) pixel and the pixel PX6 is a white (W) pixel. The pixel PX1 and the pixel PX4 are located between the source line S1 and the source line S2. The pixel PX2 and the pixel PX5 are located between the source line S2 and the source line S3. The pixel PX3 and the pixel PX6 are located between the source line S3 and the source line S4.

  The pixels PX1 to PX3 extend in a first extending direction D1 intersecting at an acute angle clockwise with respect to the second direction Y. All of the source lines S1 to S4 located on both sides of each of the pixels PX1 to PX3 extend in the first extending direction D1. The pixels PX4 to PX6 extend in a second extending direction D2 that intersects the second direction Y counterclockwise at an acute angle. All of the source lines S1 to S4 positioned on both sides of the pixels PX4 to PX6 extend in the second extending direction D2. The angle θ1 between the second direction Y and the first extending direction D1 is substantially the same as the angle θ2 between the second direction Y and the second extending direction D2.

  The common electrode CE extends over substantially the entire area of the array substrate AR, and is formed in common to the pixels PX1 to PX6. That is, the common electrode CE extends in the second direction Y across the gate lines G1 to G2, and extends in the first direction X across the source lines S1 to S4, and the pixels PX1 to PX6 Are located at each of the. In each of the pixels PX1 to PX6, an opening for electrically connecting the pixel electrode and the switching element is formed in the common electrode CE.

  The pixel PX1 includes a switching element SW1 and a pixel electrode PE1. The switching element SW1 is electrically connected to the gate line G1 and the source line S1. The pixel electrode PE1 is located between the source line S1 and the source line S2, and is electrically connected to the switching element SW1.

  The pixel PX2 includes a switching element SW2 and a pixel electrode PE2. The switching element SW2 is electrically connected to the gate line G1 and the source line S2. The pixel electrode PE2 is located between the source line S2 and the source line S3 and is adjacent to the pixel electrode PE1. The pixel electrode PE2 is electrically connected to the switching element SW2.

  The pixel PX3 includes a switching element SW3 and a pixel electrode PE3. The switching element SW3 is electrically connected to the gate line G1 and the source line S3. The pixel electrode PE3 is located between the source line S3 and the source line S4, and is adjacent to the pixel electrode PE2. The pixel electrode PE3 is electrically connected to the switching element SW3.

  Similarly, the pixel PX4 includes a switching element SW4 electrically connected to the gate line G2 and the source line S1, and a pixel electrode PE4 electrically connected to the switching element SW4. The pixel PX5 includes a switching element SW5 electrically connected to the gate line G2 and the source line S2, and a pixel electrode PE5 electrically connected to the switching element SW5. The pixel PX6 includes a switching element SW6 electrically connected to the gate line G2 and the source line S3, and a pixel electrode PE6 electrically connected to the switching element SW6.

  The switching elements SW1 to SW6 are, for example, thin film transistors (TFTs).

The pixel electrodes PE1 to PE6 respectively face the common electrode CE.
The pixel electrodes PE1 to PE3 are each formed in an island shape corresponding to the pixel shape extended in the first extending direction D1. The pixel electrode PE1 has a contact portion CT1 electrically connected to the switching element SW1 and at least one strip electrode PA1 extending from the contact portion CT1. The pixel electrode PE2 has a contact portion CT2 electrically connected to the switching element SW2 and at least one strip electrode PA2 extending from the contact portion CT2. The pixel electrode PE3 has a contact portion CT3 electrically connected to the switching element SW3 and at least one strip electrode PA3 extending from the contact portion CT3.

  The contact portion CT2 is aligned with the contact portion CT1 on the same straight line along the first direction X. The contact portion CT3 is disposed at a position deviated from the same straight line as the contact portion CT1. The contact portion CT3 is located closer to the gate line G2 than the contact portions CT1 and CT2. In the illustrated example, the contact portion CT3 is located on the opposite side to the contact portions CT1 and CT2 across the gate wiring G1.

  The strip electrodes PA1 to PA3 extend in the first extending direction D1. That is, the strip electrode PA1 extends from the contact portion CT1 toward the side away from the gate line G2. Similarly, the strip electrode PA2 extends from the contact portion CT2 toward the side away from the gate line G2. The strip electrode PA2 has the same length as the strip electrode PA1. The strip electrode PA3 extends from the contact portion CT3 toward the side away from the gate line G2. The strip electrode PA3 has a length different from that of the strip electrode PA1 or the like, and in the illustrated example, has a length longer than that of the strip electrode PA1. That is, the total length of the pixel electrode PE3 along the first extending direction D1 is longer than the total length of the pixel electrode PE1 and the pixel electrode PE2 along the first extending direction D1.

  The number of strip electrodes PA1 is the same as the number of strip electrodes PA2, and the number of strip electrodes PA3 is larger than the number of strip electrodes PA1. In the illustrated example, the pixel electrode PE1 has two strip electrodes PA1 aligned in the first direction X, the pixel electrode PE2 has two strip electrodes PA2 aligned in the first direction X, and the pixel electrode PE3 Has three strip electrodes PA3 aligned in the first direction X.

  The pixel electrodes PE4 to PE6 are each formed in an island shape corresponding to the pixel shape extended in the second extending direction D2. The pixel electrode PE4 has a contact portion CT4 electrically connected to the switching element SW4 and at least one strip electrode PB1 extended from the contact portion CT4. The pixel electrode PE5 has a contact portion CT5 electrically connected to the switching element SW5 and at least one strip electrode PB2 extending from the contact portion CT5. The pixel electrode PE6 has a contact portion CT6 electrically connected to the switching element SW6 and at least one strip electrode PB3 extending from the contact portion CT6. The contact portions CT1 to CT3 are arranged on the same straight line along the first direction X.

  The strip electrodes PB1 to PB3 respectively extend in the second extending direction D2. That is, the strip-shaped electrode PB1 extends from the contact portion CT4 toward the side closer to the gate wiring G1. Similarly, the strip electrode PB2 extends from the contact portion CT5 toward the side closer to the gate wiring G1. The strip electrode PB2 has a length equal to that of the strip electrode PB1. The strip electrode PB3 extends from the contact portion CT6 toward the side closer to the gate line G1. The strip electrode PB3 has a length different from that of the strip electrode PB1 or the like, and in the illustrated example, has a length shorter than that of the strip electrode PB1. That is, the total length of the pixel electrode PE6 in the second extending direction D2 is shorter than the total length of the pixel electrode PE4 and the pixel electrode PE5 in the second extending direction D2.

  The number of strip electrodes PB1 is the same as the number of strip electrodes PB2, and the number of strip electrodes PB3 is larger than the number of strip electrodes PB1. In the illustrated example, the pixel electrode PE4 has two strip electrodes PB1 aligned in the first direction X, the pixel electrode PE5 has two strip electrodes PB2 aligned in the first direction X, and the pixel electrode PE6 Has three strip electrodes PB3 aligned in the first direction X.

  The first alignment film AL1 is aligned along a direction intersecting an acute angle of 45 ° or less with respect to the first extending direction D1 and the second extending direction D2. For example, the alignment processing direction R1 of the first alignment film AL1 is a direction parallel to the second direction Y, and is a direction intersecting the first extension direction D1 or the second extension direction D2.

  FIG. 3 is a plan view schematically showing a structural example of the switching elements SW2 and SW3 shown in FIG. In the illustrated example, each of the switching elements SW2 and SW3 is formed of a thin film transistor having a double gate structure.

  That is, the switching element SW2 includes the semiconductor layer SC2 and the relay electrode RE2. The semiconductor layer SC2 is formed in a U-shape, and intersects with the gate wiring G1 at two places. One end side of the semiconductor layer SC2 is connected to the source wiring S2 via the contact hole CH11. The other end side of the semiconductor layer SC2 is connected to the relay electrode RE2 via the contact hole CH12. The relay electrode RE2 overlaps with the contact portion CT2 of the pixel electrode PE2, and is connected to the contact portion CT2 via the contact hole CH13.

  The switching element SW3 includes the semiconductor layer SC3 and the relay electrode RE3. The semiconductor layer SC3 is formed in a U-shape, and intersects with the gate wiring G1 at two places. One end side of the semiconductor layer SC3 is connected to the source wiring S3 via the contact hole CH21. The other end side of the semiconductor layer SC3 is connected to the relay electrode RE3 via the contact hole CH22. The relay electrode RE3 overlaps with the contact portion CT3 of the pixel electrode PE3, and is connected to the contact portion CT3 via the contact hole CH23.

  In the illustrated example, the semiconductor layer SC3 is formed in the opposite direction to the semiconductor layer SC2. That is, the semiconductor layer SC2 is folded back on the side closer to the pixel electrode PE2 than the gate line G1, and connected to the source line S2 and the relay electrode RE2 on the side separated from the pixel electrode PE2 than the gate line G1. On the other hand, the semiconductor layer SC3 is folded back on the side farther from the pixel electrode PE3 than the gate line G1, and connected to the source line S3 and the relay electrode RE3 on the side closer to the pixel electrode PE3 than the gate line G1. In other words, the contact holes CH11 and CH12 are located on the opposite side to the contact holes CH21 and CH22 across the gate wiring G1. The contact hole CH13 is also located on the opposite side to the contact hole CH23 with the gate wiring G1 interposed therebetween. Alternatively, from another viewpoint, an imaginary straight line connecting the contact hole CH13 provided in the contact portion CT2 of the pixel electrode PE2 and the contact hole CH23 provided in the contact portion CT3 of the pixel electrode PE3 of the adjacent pixel is It intersects with the gate wiring G1.

  The semiconductor layers SC2 and SC3 are formed of, for example, polycrystalline silicon (p-Si), but may be formed of amorphous silicon (a-Si), an oxide semiconductor, or the like.

  FIG. 4 is a plan view schematically showing an example of the layout of each pixel and a color filter in the present embodiment.

  A unit pixel UP for realizing color display is constituted by a plurality of different color pixels. The unit pixel UP is a minimum unit constituting a color image displayed in the active area. The unit pixel UP is composed of, for example, six color pixels. The unit pixel UP is configured by the pixel PX1, the pixel PX2, the pixel PX3, the pixel PX4, the pixel PX5, and the pixel PX6. In the drawing, each pixel is indicated by an alternate long and short dash line.

  As described above, the pixel PX1 and the pixel PX4 are red pixels, the pixel PX2 and the pixel PX5 are green pixels, the pixel PX3 is a blue pixel, and the pixel PX6 is a white pixel. In such a configuration, the areas of the pixel PX1, the pixel PX2, the pixel PX4, and the pixel PX5 are substantially equal. The area of the pixel PX3 is larger than the area of the pixel PX1 or the like.

  The counter substrate CT includes a light shielding layer BM, color filters CF1 to CF4, a second alignment film AL2, and the like.

  The light shielding layer BM is disposed at the boundary of each pixel. That is, the light shielding layer BM is located above the wiring portion such as the source wiring, the gate wiring, and the switching element shown in FIG. In the example shown in FIG. 2, the position of the contact portion CT3 (or switching element SW3) is deviated from the same straight line position where the contact portion CT1 (or switching element SW1) and the contact portion CT2 (or switching element SW2) are arranged. . Therefore, in the light shielding layer BM shown in the drawing, the portion extending in the first direction X is meandered in correspondence with the layout of the array substrate AR. The light shielding layer BM may be disposed at the boundary between pixels of different colors, but not at the boundary between pixels of the same color.

  The color filter CF1 is formed in a strip extending along the second direction Y. The color filter CF2 is formed in a strip shape adjacent to the color filter CF1 in the first direction X and extending along the second direction Y. The color filter CF3 is formed in an island shape adjacent to the color filter CF2 in the first direction X. The color filter CF4 is adjacent to the color filter CF3 in the second direction Y, and adjacent to the color filter CF2 in the first direction X, and is formed in an island shape. The color filters CF3 and the color filters CF4 are alternately and repeatedly arranged along the second direction Y.

  The color filter CF1 is disposed corresponding to the pixel PX1 and the pixel PX4. The color filter CF2 is disposed corresponding to the pixel PX2 and the pixel PX5. The color filter CF3 is disposed corresponding to the pixel PX3. The color filter CF4 is disposed corresponding to the pixel PX6. In the illustrated example, the color filter CF1 is a red (R) color filter, the color filter CF2 is a green (G) color filter, the color filter CF3 is a blue (B) color filter, and the color filter CF4 is white (W) It is a color filter. Adjacent end portions of the color filters CF1 to CF4 overlap the light shielding layer BM.

  The second alignment film AL2 is subjected to alignment processing in a direction parallel to the alignment processing direction R1 of the first alignment film AL1. The alignment processing direction R2 of the second alignment film AL2 is, for example, opposite to the alignment processing direction R1 of the first alignment film AL1.

  FIG. 5 is a cross sectional view schematically showing a configuration of a liquid crystal display panel LPN including the pixels PX1 to PX6 shown in FIG.

  The array substrate AR is formed using a transparent first insulating substrate 10 such as a glass substrate or a resin substrate. The array substrate AR is formed on the side of the first insulating substrate 10 facing the counter substrate CT, with the source lines S1 to S4, the common electrode CE, the pixel electrodes PE1 to PE6, the first insulating film 11, the second insulating film 12, and The insulating film 13 and the first alignment film AL1 are provided. Here, illustration of the switching element and the gate wiring is omitted.

  The source lines S1 to S4 are formed on the first insulating film 11 and covered with the second insulating film 12. The gate wiring is formed between the first insulating substrate 10 and the first insulating film 11. The common electrode CE is formed on the second insulating film 12 and covered by the third insulating film 13. The common electrode CE is formed of a transparent conductive material, such as indium tin oxide (ITO) or indium zinc oxide (IZO).

  The pixel electrodes PE1 to PE6 are formed on the third insulating film 13 and face the common electrode CE. That is, the strip electrodes PA1 to PA3 and the strip electrodes PB1 to PB3 are located above the common electrode CE with the third insulating film 13 interposed therebetween. The third insulating film 13 corresponds to an interlayer insulating film interposed between the common electrode CE and the pixel electrodes PE1 to PE6. The pixel electrode PE1 and the pixel electrode PE4 are located between the source line S1 and the source line S2. The pixel electrode PE2 and the pixel electrode PE5 are located between the source line S2 and the source line S3. The pixel electrode PE3 and the pixel electrode PE6 are located between the source line S3 and the source line S4. The pixel electrodes PE1 to PE6 are all formed of a transparent conductive material, such as ITO or IZO. The pixel electrodes PE1 to PE6 are covered by the first alignment film AL1. The first alignment film AL1 also covers the third insulating film 13. The first alignment film AL1 is formed of a material exhibiting horizontal alignment, and is disposed on the surface of the array substrate AR in contact with the liquid crystal layer LQ.

  On the other hand, the counter substrate CT is formed using a transparent second insulating substrate 20 such as a glass substrate or a resin substrate. The counter substrate CT includes a light shielding layer BM, color filters CF1 to CF4, an overcoat layer OC, a second alignment film AL2 and the like on the side of the second insulating substrate 20 facing the array substrate AR.

  The light shielding layer BM is formed on the inner surface of the second insulating substrate 20. The light shielding layer BM is located above the source lines S1 to S4. The light shielding layer BM is formed of a black resin material or a light shielding metal material.

  Each of the color filters CF1 to CF4 is formed on the inner surface of the second insulating substrate 20. The color filter CF1 is opposed to the pixel electrode PE1 and the pixel electrode PE4. The color filter CF2 is opposed to the pixel electrode PE2 and the pixel electrode PE5. The color filter CF3 faces the pixel electrode PE3. The color filter CF4 is opposed to the pixel electrode PE6. The color filter CF1 is formed of a resin material colored in red. The color filter CF2 is formed of a resin material colored in green. The color filter CF3 is formed of a resin material colored in blue. The color filter CF4 is formed of a white (or transparent) resin material. The color filter CF4 may be omitted or may not be a strictly achromatic color filter, or may be a light-colored (for example, light yellow or light blue colored) color filter. The boundary between the color filters of different colors overlaps the light shielding layer BM above the source line S.

  The overcoat layer OC covers the color filters CF1 to CF4. The overcoat layer OC flattens the unevenness of the surfaces of the color filters CF1 to CF4. The overcoat layer OC is formed of a transparent resin material. The overcoat layer OC is covered by the second alignment film AL2. The second alignment film AL2 is formed of a material exhibiting horizontal alignment, and is disposed on the surface of the counter substrate CT in contact with the liquid crystal layer LQ.

  The array substrate AR and the counter substrate CT as described above are arranged such that the first alignment film AL1 and the second alignment film AL2 face each other. At this time, a predetermined cell gap is formed between the array substrate AR and the counter substrate CT by the columnar spacer formed on one of the substrates. The array substrate AR and the counter substrate CT are pasted together by a sealing material in a state where the cell gap is formed. The liquid crystal layer LQ is formed of a liquid crystal material including liquid crystal molecules LM enclosed between the first alignment film AL1 and the second alignment film AL2.

  A backlight BL is disposed on the back side of the liquid crystal display panel LPN having such a configuration. Although various forms are applicable as the backlight BL, the description of the detailed structure is omitted here.

  On an outer surface 10B of the first insulating substrate 10, a first optical element OD1 including a first polarizing plate PL1 is disposed. On the outer surface 20B of the second insulating substrate 20, the second optical element OD2 including the second polarizing plate PL2 is disposed. The first polarizing plate PL1 and the second polarizing plate PL2 are arranged, for example, in a positional relationship of crossed Nicols in which respective polarization axes are orthogonal to each other.

The operation of the liquid crystal display device having the above configuration will be described below.
When no voltage is applied to form a potential difference between the pixel electrode PE and the common electrode CE, no voltage is applied to the liquid crystal layer LQ. That is, no electric field is formed between the pixel electrode PE and the common electrode CE. For this reason, as shown by the solid line in FIG. 2, the liquid crystal molecules LM contained in the liquid crystal layer LQ are in the second direction Y in the XY plane by the alignment control force of the first alignment film AL1 and the second alignment film AL2. Initial orientation. That is, the initial alignment direction of the liquid crystal molecules LM is parallel to the second direction Y. At the time of OFF, part of the backlight light from the backlight BL passes through the first polarizing plate PL1 and is incident on the liquid crystal display panel LPN. The light incident on the liquid crystal display panel LPN is, for example, linearly polarized light orthogonal to the first absorption axis of the first polarizing plate PL1. The polarization state of such linearly polarized light hardly changes when passing through the liquid crystal display panel LPN at the time of OFF. Therefore, most of the linearly polarized light transmitted through the liquid crystal display panel LPN is absorbed by the second polarizing plate PL2 (black display).

  On the other hand, when a voltage is applied to form a potential difference between the pixel electrode PE and the common electrode CE, a voltage is applied to the liquid crystal layer LQ. That is, a fringe electric field is formed between the pixel electrode PE and the common electrode CE. For this reason, the liquid crystal molecules LM are aligned in an orientation different from the initial alignment direction in the XY plane, as indicated by a broken line in FIG. In the positive type liquid crystal material, for example, the liquid crystal molecule LM of the pixel PX3 rotates counterclockwise so as to align in a direction substantially parallel to the fringe electric field in the XY plane, and the liquid crystal molecule LM of the pixel PX6 is In the XY plane, it rotates clockwise so as to be oriented in a direction substantially parallel to the fringe electric field. At this time, the liquid crystal molecules LM are aligned in the direction according to the magnitude of the electric field. At the time of ON, linearly polarized light orthogonal to the first absorption axis of the first polarizing plate PL1 enters the liquid crystal display panel LPN, and the polarization state thereof corresponds to the alignment state of the liquid crystal molecules LM when passing through the liquid crystal layer LQ. Change. Therefore, at the time of the on-state, at least a part of the light having passed through the liquid crystal layer LQ is transmitted through the second polarizing plate PL2 (white display).

With such a configuration, a normally black mode is realized.
As described above, when the unit pixel UP is configured by six color pixels of 2 rows × 3 columns, these six color pixels are any of red pixels, green pixels, blue pixels, and white pixels. It is assigned. For example, two color pixels in the same column are assigned as red pixels, and two color pixels in the same column are assigned as green pixels. In addition, color pixels in the same column are respectively assigned as the blue pixel and the white pixel.

  That is, in the unit pixel UP of the layout described in the present embodiment, two color pixels are assigned to each of the red and green pixels, whereas each of the blue and white pixels is assigned to one color pixel. In the case where all the six color pixels have the same area, the blue luminance is insufficient. Therefore, the length of the blue pixel in the first direction X is longer than the length of each of the red pixel and the green pixel in the first direction X, thereby expanding the area of the blue pixel and setting the luminance necessary for the blue pixel. I have secured.

  On the other hand, when the length of the unit pixel UP in the first direction X is restricted due to the demand for higher definition, etc., the area of each color pixel is adjusted only by the length along the first direction X of each color pixel. There is a limit to For this reason, in order to maintain the optimal color balance, it is necessary to drive the red pixel and the green pixel with relatively low luminance in accordance with the luminance of the blue pixel. In addition, as the difference in length along the first direction X of each color pixel becomes larger, unit pixel UP is generated when a misalignment occurs in the first direction X in the step of bonding the array substrate AR and the counter substrate CT. This causes the area ratio of each color pixel to largely change, resulting in the problem that the color balance is broken.

  Therefore, according to the present embodiment, among the three pixel electrodes arranged in the first direction X, the contact portion of one pixel electrode is shifted from the same straight line with the contact portion of the other two pixel electrodes. Is located in For example, in the blue pixel, the pixel electrode and the switching element are electrically connected at a position shifted from the same straight line with the red pixel and the green pixel. At this time, the pixel electrode of the blue pixel protrudes to the side of the white pixel, and the contact portion thereof is close to the pixel electrode of the white pixel. This makes it possible to expand the area contributing to display in the blue pixel in the column direction (or the second direction Y). Therefore, it is possible to increase the luminance of blue pixels. As a result, in the unit pixel UP, it is possible to obtain an optimal color balance with high luminance. In addition, since the difference in length in the first direction X of each color pixel is not enlarged, it is possible to suppress the change in color balance due to the bonding deviation. Therefore, the display quality can be improved.

  Further, in the unit pixel UP, the area of each color pixel can be adjusted by the length of the first direction X and the length of the second direction Y, and the degree of freedom of layout can be improved.

  In the above embodiment, the odd-shaped layout has been described in which red pixels and green pixels have equal pitches, and blue pixels and white pixels have a larger pitch than red pixels and green pixels. May be a combination of color pixels different from the above, or the pitch may be different for all of the red pixels, the green pixels, the blue pixels, and the white pixels. The pixel electrodes disposed in each color pixel may have the strip electrodes of the number appropriately set in accordance with the pixel pitch, and the present invention is not limited to the above example.

Next, another configuration example will be described.
FIG. 6 is a schematic plan view of the second configuration example of the pixels in the array substrate AR shown in FIG. 1 as viewed from the opposite substrate side.

  The second configuration example shown here is different from the first configuration example shown in FIG. 2 in that a part of the gate wiring G1 is bent. The other configuration is the same as the first configuration example, and the description will be omitted.

  In the illustrated example, as in the first configuration example, the contact portions CT1 and CT2 are aligned on the same straight line along the first direction X, whereas the contact portion CT3 is on the same straight line as the contact portion CT1. The pixel electrode PE3 is disposed at a position deviated from the pixel electrode PE3 and extends in the second direction Y toward the pixel electrode PE6.

  The gate wiring G1 linearly extends along the first direction X corresponding to the contact portions CT1 and CT2, and is bent toward the pixel electrode PE6 corresponding to the contact portion CT3. Such gate wiring G1 is electrically connected to each of the switching elements SW1 to SW3. The switching elements SW1 to SW3 are electrically connected to the pixel electrodes PE1 to PE3, respectively.

  Also in such a second configuration example, the area contributing to the display of the pixel PX3 can be enlarged in the second direction Y, and the same effect as that of the above-described first configuration example can be obtained. In addition, in the second configuration example, even in the layout in which the contact portions CT1 to CT3 are not located on the same straight line, all of the switching elements SW1 to SW3 can be connected to the pixel electrodes PE1 to PE3 in the same direction. It becomes. That is, in the first configuration example, the switching element SW3 has a structure different from that of the other switching element SW2 or the like as described in FIG. 3, while in the second configuration example, each of the contact portions CT1 to CT3 It becomes possible to form switching elements SW1 to SW3 with the same structure regardless of the position of.

  FIG. 7 is a schematic plan view of the third configuration example of the pixels in the array substrate AR shown in FIG. 1 as viewed from the opposite substrate side.

  In the third configuration example shown here, the contact portions CT1 to CT3 are aligned on the same straight line along the first direction X, compared to the first configuration example shown in FIG. Are formed to be longer than the strip electrodes PA1 and PA2, and the contact portion CT6 is arranged at a position deviated from the same straight line from the contact portions CT4 and CT5.

  In the illustrated example, the contact portions CT4 and CT5 are aligned on the same straight line along the first direction X, while the contact portion CT6 is a position where the contact portions CT4 and CT5 are deviated from the same straight line The pixel electrode PE6 is distributed in the second direction Y toward the pixel electrode PE3. The strip electrodes PB1 and PB2 have equal lengths, while the strip electrode PB3 has a shorter length than the strip electrode PB1.

  The gate wiring G2 linearly extends along the first direction X corresponding to the contact portions CT4 and CT5, and is bent toward the pixel electrode PE3 corresponding to the contact portion CT6. Such gate line G2 is electrically connected to each of the switching elements SW4 to SW6. The switching elements SW4 to SW6 are electrically connected to the pixel electrodes PE4 to PE6, respectively.

  The gate lines G1 extend linearly along the first direction X in correspondence with the contact portions CT1 to CT3. Such gate wiring G1 is electrically connected to each of the switching elements SW1 to SW3. The switching elements SW1 to SW3 are electrically connected to the pixel electrodes PE1 to PE3, respectively.

  The illustrated unit pixel UP is repeatedly arranged in the second direction Y. That is, the tip of the strip electrode PA3 extends toward the bent portion of the gate wiring G2.

  Also in such a third configuration example, the area contributing to the display of the pixel PX3 can be expanded in the second direction Y, and the same effect as that of the above-described first configuration example can be obtained.

  As described above, according to the present embodiment, it is possible to provide a liquid crystal display device capable of improving display quality.

  While certain embodiments of the present invention have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and the gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

LPN: Liquid crystal display panel AR: Array substrate CT: Counter substrate LQ: Liquid crystal layer G: Gate wiring S: Source wiring SW: Switching element PE: Pixel electrode PA, PB: Strip electrode CE: Common electrode CF ... Color filter

Claims (13)

First and second switching elements, a gate wiring extending in a first direction and electrically connected to the first and second switching elements, and a second extending in a second direction intersecting the first direction A first source line electrically connected to the switching element, and extending in the second direction, spaced apart from the first source line in the first direction, and electrically connected to the second switching element A first contact portion electrically connected to the first switching element, and a first strip-shaped electrode having a first length extending in the second direction from the first contact portion; A second strip-shaped electrode having a second length different from the first length and extending in the second direction from one pixel electrode, a second contact portion electrically connected to the second switching element, and the second contact portion With A first substrate having a pixel electrode,
A second substrate facing the first substrate;
A liquid crystal layer held between the first substrate and the second substrate ;
The gate wiring has a bent portion which is bent to a side away from the second strip electrode at a position corresponding to the second pixel electrode.
The second source line is located between the first contact portion and the second contact portion.
The display device according to claim 1, wherein the first contact portion and the second contact portion are disposed to be shifted in the second direction in a plan view.   The display device according to claim 1, wherein the second length is longer than the first length.   The display device according to claim 1, wherein the number of the second strip electrodes is larger than the number of the first strip electrodes.   The first substrate further extends from a third switching element, a third contact portion electrically connected to the third switching element, and the third contact portion, and the first and second lengths are different from the first and second lengths. The display device according to any one of claims 1 to 3, further comprising: a third pixel electrode having a third strip electrode having a length of three. The third pixel electrode is disposed side by side with the second pixel electrode in the second direction,
The display device according to claim 4, wherein the gate line is located between the second pixel electrode and the third pixel electrode.   The display device according to claim 4, wherein the third length is shorter than the first and second lengths.   The display device according to claim 4, wherein the bent portion is bent toward the third pixel electrode at a position corresponding to the second pixel electrode. A first gate line extending in a first direction, and a second gate line extending in the first direction and spaced apart in a second direction intersecting the first direction with the first gate line; A source wiring extending in the second direction, a first switching element electrically connected to the first gate wiring and the source wiring, and a second electrically connected to the second gate wiring and the source wiring A first pixel electrode having a switching element, a first contact portion electrically connected to the first switching element, and a first strip-shaped electrode having a first length extending in the second direction from the first contact portion A second contact portion electrically connected to the second switching element, and a second strip electrode having a second length different from the first length and extending in the second direction from the second contact portion; 2 pixel electrode , A first substrate having a,
A second substrate facing the first substrate;
A liquid crystal layer held between the first substrate and the second substrate ;
The first gate line is disposed between the first pixel electrode and the second pixel electrode, and has a bent portion which is bent toward the second pixel electrode.
The display device, wherein the first length is longer than the second length.   The first substrate further extends from a third switching element electrically connected to the first gate wiring, a third contact portion electrically connected to the third switching element, and the third contact portion. 9. The display device according to claim 8, further comprising: a third pixel electrode having a third strip electrode of a third length different from the first and second lengths. The third pixel electrode is disposed side by side with the first pixel electrode in the first direction.
The display device according to claim 9, wherein the first contact portion and the third contact portion are arranged to be shifted in the second direction in plan view.   The display device according to claim 9, wherein the third length is shorter than the first length and longer than the second length. The display device according to claim 4, wherein the first switching element, the second switching element, and the third switching element have the same structure. The display device according to claim 9, wherein the first switching element, the second switching element, and the third switching element have the same structure.

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