JP6436921B2 - Multilayer ceramic capacitor - Google Patents

Multilayer ceramic capacitor Download PDF

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JP6436921B2
JP6436921B2 JP2016002749A JP2016002749A JP6436921B2 JP 6436921 B2 JP6436921 B2 JP 6436921B2 JP 2016002749 A JP2016002749 A JP 2016002749A JP 2016002749 A JP2016002749 A JP 2016002749A JP 6436921 B2 JP6436921 B2 JP 6436921B2
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internal electrode
margin
multilayer ceramic
ceramic capacitor
thickness
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JP2017118083A (en
Inventor
加藤 洋一
洋一 加藤
高太郎 水野
高太郎 水野
幸宏 小西
幸宏 小西
美徳 田中
美徳 田中
裕介 小和瀬
裕介 小和瀬
翔平 北村
翔平 北村
由 牧野
由 牧野
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太陽誘電株式会社
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Priority claimed from KR1020160016318A external-priority patent/KR101884392B1/en
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01GCAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
    • H01G4/00Fixed capacitors; Processes of their manufacture
    • H01G4/002Details
    • H01G4/228Terminals
    • H01G4/232Terminals electrically connecting two or more layers of a stacked or rolled capacitor
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01GCAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
    • H01G4/00Fixed capacitors; Processes of their manufacture
    • H01G4/002Details
    • H01G4/005Electrodes
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01GCAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
    • H01G4/00Fixed capacitors; Processes of their manufacture
    • H01G4/002Details
    • H01G4/018Dielectrics
    • H01G4/06Solid dielectrics
    • H01G4/08Inorganic dielectrics
    • H01G4/12Ceramic dielectrics
    • H01G4/1209Ceramic dielectrics characterised by the ceramic dielectric material
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01GCAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
    • H01G4/00Fixed capacitors; Processes of their manufacture
    • H01G4/30Stacked capacitors

Description

  The present invention relates to a multilayer ceramic capacitor in which leakage current between an external electrode and an internal electrode is suppressed while having a thin side margin.

  A multilayer ceramic capacitor (MLCC) generally includes a multilayer body in which dielectric layers and internal electrode layers having different polarities are alternately stacked, and the external electrode is provided on a pair of surfaces in which the internal electrode layers are alternately drawn. It has a structure in which electrodes are formed. FIG. 7 shows a schematic perspective view of a typical multilayer ceramic capacitor 100. In general, the surfaces from which the internal electrode layers are drawn to the left and right external electrodes 104 are referred to as end faces 102a and b, and the internal electrode layers and the dielectric layers The upper and lower surfaces in the stacking direction are referred to as main surfaces 102c and d, and the remaining pair of surfaces are referred to as side surfaces 102e and f.

  In general, a pair of side margins constituting a pair of side surfaces are provided for the purpose of preventing the internal electrode layer from being exposed to the outside and being destroyed or damaged.

  Here, in patent document 1, examination which secures the maximum effective area which can ensure the capacity | capacitance of an internal electrode pattern is performed. It is described in this document that when the effective area is ensured in such a manner, the thickness of the margin portion becomes thin and the internal electrode pattern is short-circuited or short-circuited.

  In order to solve this problem, the document proposes forming a laminated body of a dielectric layer and an internal electrode pattern, and then forming a side margin portion using a predetermined ceramic slurry. Thus, it is stated that the side margin is reduced to ensure an effective area, and the short circuit or the short circuit is prevented.

  By the way, in recent years, there is a high demand for miniaturization of electronic components accompanying the increase in the density of electronic circuits used in digital electronic devices such as mobile phones and tablet terminals, and the miniaturization and large capacity of the multilayer ceramic capacitors constituting the circuits. The process is progressing rapidly.

  The capacitance of a multilayer ceramic capacitor is proportional to the dielectric constant of the constituent material of the dielectric layer constituting the capacitor, the number of laminated dielectric layers, and the effective area which is the overlapping part of the internal electrode layers drawn alternately to the external electrodes. However, it is inversely proportional to the thickness per dielectric layer.

JP 2012-195555 A

  When the thickness of the side margin of the multilayer ceramic capacitor is large, the area of the internal electrode layer is reduced correspondingly, and as a result, the effective area is also reduced, and the capacitance of the capacitor is reduced.

  Therefore, the present inventors have studied to make the side margin thin. As a result, it is possible to reduce the thickness to 30 μm or less. However, because the side margin is thin, the internal margin close to the wraparound portion of the external electrode is newly obtained. A problem has been found that the leakage current between the electrode layer and the electrode layer increases.

  This point will be described in more detail with reference to FIG. FIG. 8 is a schematic cross-sectional view of the multilayer ceramic capacitor 100 at a position parallel to the main surfaces 102c and d where the internal electrode layer 106 can be seen. The monolithic ceramic capacitor 100 has a pair of external electrodes 104 on both end faces for connection to a substrate, etc., but this external electrode 104 generally wraps around other four faces other than both end faces ( A so-called five-face electrode) can be connected to a substrate or the like on any surface. In FIG. 8, the internal electrode layer 106 is connected to the right external electrode 104, is not connected to the left external electrode 104, takes a certain distance, and is in an insulated state. However, when the side margin 108 becomes as thin as 30 μm or less, the thickness of the side margin 108 becomes smaller than the distance. For this reason, at the edge near the external electrode 104 on the left side of the internal electrode layer 106, the internal electrode layer It has been clarified that a leak current is generated between the interface portion 106 and the side margin 108 and the external electrode 104 that wraps around the side surface.

  Therefore, an object of the present invention is to suppress leakage current in a multilayer ceramic capacitor having a side margin as thin as 30 μm or less.

  As a result of intensive studies to solve the above-mentioned problems, the inventors of the present invention have a configuration in which the external electrode does not wrap around even when the side margin becomes a thin layer of 30 μm or less. The present inventors have found that the problem can be solved and have completed the present invention.

  That is, the present invention is a multilayer ceramic capacitor comprising a substantially rectangular parallelepiped body having a pair of main surfaces, a pair of end surfaces and a pair of side surfaces, wherein dielectric layers and internal electrode layers having different polarities are alternately stacked. And a pair of side margins having a thickness of 30 μm or less are formed on a pair of side surfaces of the element body, and external electrodes are formed on at least one of the pair of end surfaces of the element body and the pair of main surfaces. It is a multilayer ceramic capacitor.

  From the viewpoint of improving the productivity of the multilayer ceramic capacitor, the thickness of the pair of side margins is preferably 1 μm or more.

  When the external electrode is formed on the pair of end surfaces and one main surface of the element body, the number of internal electrode layers can be increased by the amount of external electrodes on the other main surface. This is preferable from the viewpoint of increasing the capacity of the ceramic capacitor.

  Similarly, from the viewpoint of increasing the capacity of the multilayer ceramic capacitor, it is preferable to reduce the thickness of the dielectric layer to 0.8 μm or less and increase the number of stacked internal electrode layers.

  According to the present invention, it is possible to provide a multilayer ceramic capacitor excellent in reliability by suppressing a leakage current in a multilayer ceramic capacitor having a thin side margin of 30 μm or less.

1 is a schematic perspective view of a multilayer ceramic capacitor of the present invention. It is a schematic diagram of the cross section parallel to the side surfaces 12e and f of the multilayer ceramic capacitor 10 of this invention. FIG. 6 is a conceptual diagram when obtaining the thickness of the side margin 24. 2 is a schematic diagram of a cross section of the multilayer ceramic capacitor 10 at a position parallel to the main surfaces 12c and d where the internal electrode layer 18 can be seen. FIG. It is a schematic diagram which shows an example of the formation method of a side margin. It is a schematic diagram which shows an example of the formation method of a side margin. 1 is a schematic perspective view of a typical multilayer ceramic capacitor. 2 is a schematic diagram of a cross section of the multilayer ceramic capacitor 100 at a position parallel to the main surfaces 102c and d where the internal electrode layer 106 can be seen. FIG.

  Hereinafter, a multilayer ceramic capacitor according to an embodiment of the present invention will be described. FIG. 1 is a schematic perspective view of a multilayer ceramic capacitor 10 of the present invention. Also in the present invention, as in the prior art, the surfaces from which the internal electrode layers are drawn to the left and right external electrodes 14 are referred to as end surfaces 12a and b, and the upper and lower surfaces in the stacking direction of the internal electrode layers and the dielectric layers are the main surfaces 12c and d. The remaining pair of surfaces are referred to as side surfaces 12e and f.

[Multilayer ceramic capacitor]
FIG. 2 shows a schematic diagram of a cross section parallel to the side surfaces 12e and f of the multilayer ceramic capacitor 10 of the present invention. The multilayer ceramic capacitor 10 is formed on an element body 16 having a chip size and shape (for example, a substantially rectangular parallelepiped of 1.0 × 0.5 × 0.5 mm) defined by a standard, and mainly on both end face sides of the element body 16. And a pair of external electrodes 14. The element body 16 is mainly composed of particle crystals such as BaTiO 3 , CaTiO 3 , SrTiO 3 , and CaZrO 3, and a laminated body 20 in which dielectric layers 17 and internal electrode layers 18 are alternately laminated, And a cover layer 22 formed as outermost layers in the stacking direction. Further, although not shown, there is a side margin 24 that covers the stacked body 20 (internal electrode layer 18 thereof) so as not to be exposed to the outside and forms a pair of side surfaces 12e and f (see FIG. 1).

  In the laminate 20, the thickness of the dielectric layer 17 sandwiched between the internal electrode layer 18 and the two internal electrode layers 18 is set within a predetermined range according to specifications such as capacitance and required breakdown voltage. It has a high-density multilayer structure with a total number of layers of several hundred to 1,000.

  The cover layer 22 and the side margin 24 formed around the multilayer body 20 protect the dielectric layer 17 and the internal electrode layer 18 from contamination such as moisture and contamination from the outside, and prevent their deterioration over time.

  In addition, the internal electrode layer 18 has its edges alternately drawn out and electrically connected to a pair of external electrodes 14 having different polarities at both ends in the length direction of the dielectric layer 17.

  In the multilayer ceramic capacitor 10 of the present invention, the thickness of the side margin 24 is as extremely thin as 30 μm or less. In addition, if the thickness of the side margin 24 is too thin, the production becomes extremely difficult, or the internal electrode layer 18 may be contaminated or damaged from the outside. Preferably there is. In the present invention, the thickness of the side margin 24 is determined as follows.

  FIG. 3 is a conceptual diagram when the thickness of the side margin 24 is obtained. As shown in FIG. 3A, the element body 16 is cut at the center, right side, and left side of the main surface 12c of the element body 16, and three cross sections 26a, b, c parallel to the end faces 12a, b are created. 26a and 26c, the distance to the near end faces: the distance to the center = 2: 3, and there is a cross-section 26b in the center, and FIG. 3 (b) is a schematic diagram of these cross-sections). Observe at magnifying power 3000 times. As shown in FIG. 3B, the field of view is the upper part of the side margin 24 (the upper end of the upper cover layer 22 (the upper and lower cover layers 22 in FIG. 3B) and the cross section 26a, b, c obtained). The center of the field of view is the point moved 100 um below the upper right corner of the frame shape formed by the left and right side margins 24) and the center (the middle point of the upper and lower cover layers 22 is the center of the field of view). Center) and lower part (the center of the visual field is near the point moved 100um above the lower end of the lower cover layer 22 (the lower right corner of the frame shape)). Make observations. That is, 3 (field of view) × 2 (both sides) × 3 (cross section) = 18 fields of view are observed per element body 16. FIG. 3 (c) shows an enlarged image of the field of view (schematic diagram of SEM observation image) labeled IIIc in (b).

  Within these respective fields of view, the length from the end of the internal electrode layer 18 in contact with the side margin 24 through the side margin 24 to the interface with the outside of the element body 16 (the side margin 24 and The interface with the laminated body 20 is defined as the effective cover thickness in the field of view (which may be a straight line as shown in the schematic diagram of FIG. The effective thickness of each of the 18 visual fields is obtained. This is performed with respect to the three element bodies 16, and the average value of the cover effective thicknesses of a total of 54 fields is set as the thickness of the side margin 24 of the multilayer ceramic capacitor 10 under each manufacturing condition.

  In the multilayer ceramic capacitor 10 of the present invention, since the thickness of the side margin 24 defined as described above is as extremely thin as 30 μm, the effective area of the internal electrode layer 18 is increased correspondingly to increase the capacity of the capacitor. Can do.

  However, when the side margin is reduced in this way, as explained in the above [Problems to be Solved by the Invention], the internal electrode layer has an internal edge at the edge near the external electrode on the opposite side from which it is drawn. Leakage current is generated between the interface portion of the electrode layer and the side margin and the external electrode that wraps around the side surface.

  Therefore, in order to solve such a problem, the present invention forms the external electrode 14 on the pair of end faces 12a, 12b and at least one of the pair of main faces 12c, d, and has an L-shape. It is a two-sided electrode or a U-shaped three-sided electrode. Thus, by forming the external electrode 14 so that the external electrode is not formed on the pair of side surfaces 12e and 12f, the above-described problem of leakage current can be prevented.

  Note that not being formed on the pair of side surfaces 12e and f includes not only the case where the external electrode 14 is not present on the side surfaces 12e and f but also a case where the external electrodes 14 are formed to a certain extent. Specifically, FIG. 4 is a schematic diagram of a cross section of the multilayer ceramic capacitor 10 at a position parallel to the main surfaces 12c and d where the internal electrode layer 18 is visible. For example, from the intersection of the side surface 12f and the end surface 12a. The external electrode 14 may be formed on the side surface 12f up to a position 30 corresponding to the terminal end on the end surface 12a side of the internal electrode layer 18 drawn out to the end surface 12b side. This is because no leak current occurs up to this point. The same applies to the end face 12b and the side face 12e on the opposite side.

  In the present invention, since the external electrode 14 is formed on at least one of the pair of main surfaces 12c, d, for example, the external electrode 14 may not be formed on the one main surface 12c. The external electrode 14 is not formed on one main surface 12c in this case, as in the case of the side surfaces 12e and f, not only when there is no external electrode 14 on the main surface 12c, but for example, the main surface This includes the case where the external electrode 14 is formed on the cover layer 22 from the intersection of the end surface 12c and the end surface 12a to a position corresponding to the end of the internal electrode layer 18 drawn to the end surface 12b side on the end surface 12a side. The same applies to the end face 12b on the opposite side.

  In the present invention, the external electrode 14 is preferably formed on one of the pair of main surfaces 12c, d. This is because the number of stacked internal electrode layers 18 can be increased by the amount of the external electrode on the other main surface, and the capacity of the multilayer ceramic capacitor 10 can be increased. In addition, in the main surface in which the external electrode 14 is formed, the external electrode 14 does not cover the entire main surface, and is formed separately on the end surface 12a side and the end surface 12b side at a certain distance. .

  From the viewpoint of increasing the capacity of the multilayer ceramic capacitor 10, the thickness of the dielectric layer 17 is preferably 0.8 μm or less. This is because the capacitance can be increased by reducing the thickness of the dielectric layer 17, and the number of stacked internal electrode layers 18 can be increased as the dielectric layer 17 is thinner.

  Similarly, from the viewpoint of increasing the multilayer ceramic capacitor 10 by increasing the number of laminated internal electrode layers 18, the thickness of the external electrode 14 formed on one main surface 12 d is preferably 1 to 30 μm. . In FIG. 2, the thickness of the external electrode 14 is the length from the main surface 12d to the end of the external electrode 14 on the normal line 32 (a plurality of surfaces) of the main surface 12d passing through the external electrode 14 portion. Let T be the maximum value. In FIG. 2, there is no clear starting point of the main surface 12d. In such a case, the main surface 12d is defined from the end of the curved portion of the end surface 12a.

  In addition, in the multilayer ceramic capacitor 10 of the present invention, the thickness of the cover layer 22 and the thickness of the internal electrode layer 18 are not particularly limited, but the thickness of the cover layer 22 is usually 5 to 40 μm, The thickness of the electrode layer 18 is usually 0.2 to 1.0 μm.

[Manufacturing method of multilayer ceramic capacitor]
Next, a method for manufacturing the multilayer ceramic capacitor of the present invention described above will be described.
First, raw material powder for forming a dielectric layer is prepared. As the raw material powder, various powders that can form a ceramic sintered body such as BaTiO 3 , CaTiO 3 , SrTiO 3 , and CaZrO 3 can be used.

  These can be synthesized by reacting various metal raw materials. As the synthesis method, various methods are conventionally known, and for example, a solid phase method, a sol-gel method, a hydrothermal method, and the like are known. Any of these can be used in the present invention.

  A predetermined amount of a compound serving as an auxiliary component may be added to the obtained raw material powder according to the purpose. Subcomponents include Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er rare earth oxides, and Mg, Mn, Ni, Co, Fe, Cr, Cu, Al, Mo, W, V, and Si. An oxide is mentioned.

  For example, the raw material powder obtained as described above may be pulverized as necessary to adjust the particle size, or may be combined with a classification treatment to adjust the particle size.

  Then, a binder such as polyvinyl butyral (PVB) resin, an organic solvent such as ethanol and toluene, and a plasticizer such as dioctyl phthalate (DOP) are added to the raw material powder and wet mixed. Using the obtained slurry, for example, by the die coater method or the doctor blade method, the belt-like slurry is applied on a substrate and dried to obtain a dielectric green sheet having a thickness of 1.2 μm or less. Then, by printing a metal conductive paste containing an organic binder on the surface of the obtained dielectric green sheet by screen printing or gravure printing, a pattern of internal electrode layers that are alternately drawn to a pair of external electrodes having different polarities is obtained. Deploy. As the metal, nickel is widely adopted from the viewpoint of cost.

  Thereafter, the dielectric green sheet on which the internal electrode layer pattern is printed is punched to a predetermined size, and the internal electrode layer and the dielectric layer are separated from the punched dielectric green sheet in a state where the substrate is peeled off. A predetermined number of layers (for example, 100) so that the internal electrode layers are alternately staggered and the edges are alternately exposed at both end faces in the length direction of the dielectric layer and alternately drawn out to a pair of external electrodes having different polarities. ˜1000 layers). A cover sheet to be a cover layer is pressure-bonded on the top and bottom of the laminated dielectric green sheets and cut into predetermined chip dimensions (for example, the size after firing is 1.2 mm × 0.7 mm × 0.7 mm).

  Here, as a method for forming the side margin, various conventionally known methods can be employed without any limitation as long as the side margin having the thickness defined in the present invention can be formed. For example, when cutting to the predetermined chip size, it is not cut at the position of the internal electrode layer just so as to include a portion of the dielectric layer that is slightly covered with the internal electrode layer and not covered with the internal electrode layer. By cutting, a side margin having a thickness of 30 μm or less is formed on both side surfaces of the laminate, and an element precursor that becomes the element body 16 can be obtained by firing.

  In such a method, a plurality of printed internal electrode layers exist in the element precursor in a printed shape, but it is difficult to make the printed shape of the internal electrode layers completely the same. Also, when laminating dielectric green sheets on which internal electrode layers are printed, it is difficult to stack the plurality of staggered internal electrode layers so that they completely overlap each other. May be laminated. Therefore, in the element precursor, as shown in FIG. 3C, the interface between the stacked body 20 of the plurality of internal electrode layers 18 and the dielectric layers 17 and the side margin 24 is not a straight line. In this case, it is considered that the side margin 24 is extremely thin locally, and the internal electrode layer 18 is likely to be contaminated or damaged from the outside at that portion.

  In order to prevent such a situation, in the present invention, the side margin can be formed as follows. That is, as shown in FIG. 5A, a predetermined interval (this is the difference between the external electrode 14 and the edge of the internal electrode layer 18 drawn to the external electrode 14 opposite to the external electrode 14 in FIG. A plurality of dielectric green sheets on which the internal electrode patterns 200 are printed in stripes with a gap between the central portion of the stripes and the interval between the internal electrode patterns 200. Laminate to overlap.

This is cut so as to cross the stripe-shaped internal electrode pattern 200 as indicated by the C 1 -C 1 line, and a bar shape in a portion excluding the pair of opposing side margins 204 shown in FIG. 5B. The laminate 202 is obtained. Here, the cutting width (distance between cross sections generated by cutting) is
It corresponds to the size of the multilayer ceramic capacitor to be manufactured, that is, the distance between the pair of side surfaces 12e, f of the element body 16.

A side margin 204 is formed on the side surface of the obtained rod-shaped laminate 202 so that the thickness after firing is 30 μm or less (the side margin is usually formed of the same material as that of the dielectric layer 17), and C 2 -C cut into individual chip size as shown by two-wire (C 2 -C 2 wire passes through a central portion of the central portion or the internal electrode pattern 200 to each other spacing of the internal electrode pattern 200), the individual A laminated chip 206 is obtained (FIG. 5C). In the chip 206, internal electrodes are alternately drawn in the cross section generated by the cutting, and the chip 206 is an element precursor that becomes the element body 16 by firing.

  As another method, the side margin can be formed as follows. That is, as shown in FIG. 6, in the laminate of dielectric green sheets, the laminate chip 300 obtained by cutting at the position of the internal electrode layer just or inside thereof is obtained (the internal electrode layer is exposed on the side surface). Are arranged on the assembly stage 302 with their side surfaces facing up. Then, a plurality of block members 304 a to 304 d that can slide in the direction indicated by the arrow on the assembly stage 302 are slid in the arrow direction on the assembly stage 302. In this way, an assembly having a rectangular planar shape in which a plurality of laminate chips 300 are in close contact with each other can be obtained.

  In this state, a ceramic paste (usually the same material as the material for forming the dielectric layer 17) is applied by using the squeegee 306 to form a ceramic paste layer having a predetermined thickness on the upper surface of the aggregate, and this is dried. Let This thickness can be adjusted by adjusting the difference between the height of the laminated chip 300 arranged and the height of the block material 304.

  The ceramic paste layer is formed on the entire surface of the multilayer chip 300, so that the roller is pressed from the upper surface of the aggregate and travels, or the blade is pressed to a position corresponding to the boundary of the multilayer chip 300. As a result, the ceramic paste layer is divided so as to correspond to the individual multilayer chips 300.

  As described above, the side margin is formed on one side surface of the multilayer chip 300, and the same operation as described above is repeated by inverting this, thereby forming the same side margin on the other side surface. An element precursor that becomes the body 16 can be obtained.

  Further, after forming the cover layer and the side margin, the corner portion of the element precursor may be chamfered, and the connecting portion of each surface of the element precursor may be curved. Thereby, the chip | tip of the corner | angular part of an element | base_body precursor can be suppressed.

  In order to obtain such a shape, for example, by putting water, a plurality of element precursors and a polishing medium in a sealed rotating pot made of a material such as polyethylene, and rotating the sealed rotating pot, What is necessary is just to chamfer the corner | angular part of the said element | base_body precursor.

Element body comprising a laminate of dielectric layers and internal electrode layers, a cover layer covering the upper and lower main surfaces of the laminate, and side margins covering both side surfaces of the laminate, obtained as described above. The precursor is debindered in an N 2 atmosphere at 250 to 500 ° C., and then fired in a reducing atmosphere at 1100 to 1300 ° C. for 10 minutes to 2 hours, whereby each compound constituting the dielectric green sheet is fired. Knotted and densified. Thus, the element body 16 in the multilayer ceramic capacitor 10 of the present invention is obtained.

  In the present invention, the reoxidation treatment may be further performed at 600 to 1000 ° C.

  Then, external electrodes 14 are formed on both end surfaces and at least one main surface of the obtained element body 16. In order to form the external electrode at such a specific position, for example, the following method can be employed.

  Alignment so that the main surface or side surface of the element body 16 is in contact with the lower surface, and external electrode paste composed of metal particles such as Cu and an organic binder such as ethyl cellulose, a dispersant, and a solvent is printed on one or both main surfaces. Application and drying are performed, and external electrodes are formed on the main surfaces (when external electrodes are formed on both main surfaces, a U-shaped three-surface electrode is formed, and when formed on one main surface, an L-shaped two-surface electrode is formed). Thereafter, the same paste is dipped on both end faces of the element body 16, dried and baked. Thereafter, a plating film of Ni and Sn is formed.

  The external electrode 14 can be formed on the main surface by using a cover sheet having an external electrode pattern printed on the surface in advance in forming the cover layer 22.

  Further, the external electrode 14 can be formed by sputtering or vapor deposition on both the main surface and the end surface.

  In this manner, the multilayer ceramic according to the present invention has the external electrodes 14 formed on at least one of the pair of end surfaces of the element body 16 and the pair of main surfaces, and has a side margin of 30 μm or less on the pair of side surfaces. The capacitor 10 is manufactured.

  Hereinafter, the present invention will be described in more detail with reference to examples. However, the present invention is not limited to these examples.

[Manufacture of multilayer ceramic capacitors]
To 100 mol of barium titanate having an average particle size of 0.1 μm, 1.0 mol each of Dy and Mg, 0.5 mol each of V and Mn were added, and an organic solvent mainly composed of alcohol, polyvinyl butyral resin, A dispersing slurry and a plasticizer were mixed and dispersed to prepare a coating slurry. Then, this slurry was coated on a substrate with a die coater to produce a dielectric green sheet. At this time, the sheet thickness was controlled by adjusting the amount of slurry supplied to the die coater.

  Subsequently, screen printing is performed on the dielectric green sheet using a conductive paste in which Ni powder having an average particle size of 200 nm and an organic solvent mainly composed of alcohol, ethyl cellulose resin, a dispersant, and a plasticizer are mixed and dispersed. The internal electrode printed dielectric green sheet was prepared. At this time, the solid content concentration of the conductor paste was adjusted by the amount of the paste solvent, and the thickness of the internal electrode was controlled.

  A plurality of layers of dielectric green sheets (for forming a cover layer) and a plurality of layers of internal electrode printed dielectric green sheets were laminated, crimped, and cut to produce individual unfired laminates.

  The unfired laminate was aligned so that the side margin surface (side surface) was the upper surface. To 100 mol of barium titanate with an average particle size of 0.1 μm, 1.0 mol of Dy and Mg and 0.5 mol of V and Mn are added, and an organic solvent mainly composed of alcohol, ethyl cellulose resin, dispersion The ceramic paste was prepared by mixing and dispersing the agent and the plasticizer. And this ceramic paste was apply | coated and dried on the upper surface of the aligned unbaking laminated body, and the side margin part was formed. At this time, the side margin thickness was controlled by changing the coating thickness of the paste. Moreover, the same process was performed on the opposing side margin surfaces to obtain an element body precursor.

  Water, a plurality of the element precursors, and polishing media were put in a sealed rotating pot, and the corners of the element precursor were chamfered by rotating the sealed rotating pot.

Element body comprising a laminate of dielectric layers and internal electrode layers, a cover layer covering the upper and lower main surfaces of the laminate, and side margins covering both side surfaces of the laminate, obtained as described above. The precursor was debindered in an N 2 atmosphere at 250 to 500 ° C., and then fired at 1100 to 1300 ° C. for 10 minutes to 2 hours in a reducing atmosphere.

  The main body obtained is aligned so that the main surface or side surface is in contact with the lower surface, external electrode paste composed of Cu particles and ethyl cellulose, a dispersant, a solvent is printed on one or both main surfaces, dried, External electrodes were formed on the main surface. Thereafter, the same paste was dipped on both end faces of the element body, dried and baked. Thereafter, a plating film of Ni and Sn was formed.

  In addition, about the 5-surface electrode used as a comparative example, the element body is aligned in a state where the heights of one end face are matched, and the end face, both main faces, and a part of both side faces are immersed in the same manner as described above. The external electrode paste was dipped and dried. Similarly, an external electrode was formed on the other end face and then baked. Thereafter, a plating film of Ni and Sn was formed.

As described above, a multilayer ceramic capacitor having the following configuration was manufactured.
Chip dimensions (vertical x horizontal x height) 1.0 mm x 0.5 mm x 0.5 mm
Dielectric layer thickness 0.5μm, 0.8μm
Number of dielectric layers 300 layers Internal electrode layer thickness 0.7μm
Number of internal electrode layers 301 layers Cover layer thickness 35μm
Side margin thickness 1.2μm ~ 39.1μm
External electrode thickness (including plating) 30μm
End margin thickness 50μm
* End margin thickness is the minimum value of the distance between the external electrode side edge from which the internal electrode layer is not drawn and the external electrode.

  The thicknesses of the dielectric layer and internal electrode layer were measured as follows. That is, with respect to the multilayer ceramic capacitor, three cross sections parallel to the end face are prepared by equally dividing one end face to the other end face, and the thickness of 20 layers of any dielectric layer and internal electrode layer in each cross section is set. Measurements were made and the average values thereof were obtained, respectively, as the dielectric layer thickness and internal electrode layer thickness.

[Measurement of leakage current]
For each of the obtained multilayer ceramic capacitors of Examples and Comparative Examples, leakage current was measured.

Equipment: ADCMT-5451 Digital ultra-high resistance / micro ammeter Conditions: Room temperature (4 V applied, after 60 seconds), Number of measurements: 10 Threshold value: Lower value than 5-sided electrode (multilayer ceramic capacitor of comparative example)

  Using a 5451 digital ultrahigh resistance / microammeter manufactured by ADCMT, the value of current flowing through the capacitor was measured when a DC voltage was applied to the external electrodes at both ends of the multilayer ceramic capacitors of Examples and Comparative Examples. The measurement was performed at room temperature, the applied voltage was 4 V, and the measurement was 60 seconds after the start of voltage application. Under this condition, 10 capacitors were measured for each capacitor, and the average value was obtained. The results are shown in Tables 1 and 2 below.

  As can be seen from Tables 1 and 2, when the side margin thickness is larger than 30 μm, the current value of the five-sided electrode of the comparative example tends to be slightly larger. Even in a ceramic capacitor, the current value is approximately the same, and no leakage current is generated.

  On the other hand, in the multilayer ceramic capacitor of the five-faced electrode of the comparative example, when the side margin thickness is reduced, the current value increases accordingly. (This is the leakage current.) Especially when the side margin thickness is 30 μm or less, the increase in the leakage current becomes remarkable with respect to the decrease in the side margin thickness. On the other hand, in the multilayer ceramic capacitor of the present invention which is an L-shaped or U-shaped electrode with no external electrode formed on the side surface, an increase in current with respect to a decrease in side margin thickness was not observed as much as a five-surface electrode. .

  Therefore, according to the present invention, even if the thickness of the side margin is 30 μm or less, it is possible to suppress the leakage current at the side surface due to the thin side margin and to keep the insulation resistance of the multilayer ceramic capacitor high. is there.

DESCRIPTION OF SYMBOLS 10 Multilayer ceramic capacitor 12a, b End surface 12c, d Main surface 12e, f Side surface 14 External electrode 16 Element body 17 Dielectric layer 18 Internal electrode layer 20 Laminated body 22 Cover layer 24 Side margin 26a, b, c Cross section 30 Internal electrode layer 32 Normal line of main surface d 100 Multilayer ceramic capacitor 102a, b End surface 102c, d Main surface 102e, f Side surface 104 External electrode 106 Internal electrode layer 108 Side margin 200 Internal electrode pattern 202 Rod-shaped multilayer body 204 Side margin 206 Laminated body chip 300 Laminated body chip 302 Assembly stage 304a-d Block material 306 Squeegee

Claims (4)

  1. A dielectric ceramic layer and internal electrode layers having different polarities are alternately laminated, and a multilayer ceramic capacitor comprising a substantially rectangular parallelepiped element having a pair of main surfaces, a pair of end surfaces, and a pair of side surfaces,
    A pair of side margins having a thickness of 30 μm or less on a pair of side surfaces of the element body;
    A multilayer ceramic capacitor in which external electrodes are formed on a pair of end faces of the element body and at least one of the pair of main surfaces, and no external electrodes are formed on a pair of side surfaces of the element body .
  2.   The multilayer ceramic capacitor according to claim 1, wherein a thickness of the pair of side margins is 1 μm or more.
  3.   The multilayer ceramic capacitor according to claim 1, wherein the external electrode is formed on a pair of end faces and one main surface of the element body.
  4.   The multilayer ceramic capacitor according to claim 1, wherein the dielectric layer has a thickness of 0.8 μm or less.
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