JP6429197B2 - Logical physical address conversion table control method and memory device - Google Patents

Description

  The present invention relates to a method for controlling a logical-physical address conversion table used for access control of a NAND flash memory, and a memory device using the control method.

  The NAND flash memory can read and write data in units of pages, and includes a plurality of pages. However, since it is a memory that cannot be overwritten, the NAND flash memory has a logical physical address conversion table as a driver even if file system management information such as FAT is not stored. It is stored in RAM and used as a logical physical address conversion table for converting addresses to physical addresses.

  The conventional logical-physical address conversion table converts logical addresses and physical addresses in units of pages. As shown in FIG. 8, conversion data for all pages of the NAND flash memory is written in the RAM. It was. According to such a configuration, there is a problem that a large capacity RAM is required. Particularly in recent years, with the evolution of the NAND flash memory process, the capacity of the NAND flash memory has been increased, and in order to cope with this, an extremely large capacity RAM is required.

  On the other hand, as shown in FIG. 9, it is known that a part of conversion data is extracted from conversion data for all pages of a NAND flash memory and written in a RAM as a logical physical address conversion table. According to this, the capacity of the RAM can correspond to a part of all pages of the NAND flash memory, and a small capacity RAM can be used.

  However, when the logical / physical address conversion table as described above is used, there is a case where the set of logical address and physical address used when accessing the NAND flash memory does not exist in the logical / physical address conversion table. The problem is how to reduce cases.

  In Patent Document 1, a nonvolatile storage device is divided into a plurality of areas for the purpose of increasing the access speed to a frequently accessed area with a limited RAM capacity, and an address conversion table is expanded in a RAM in units of areas. The address conversion table of at least one area is expanded in the RAM according to the access frequency, and for at least one other area, the area is determined based on the access history, and the address conversion table is expanded in the RAM. Is disclosed.

  Further, in Patent Document 2, the cache memory entry size is set to 1 / N (integer) of the actual page size and the data size actually handled, thereby increasing the hit rate and reducing the access overhead. Is disclosed.

Japanese Patent Application No. 2003-256269 Japanese Patent Application No. 2007-34944

  According to the technique of the above-mentioned patent document 1, since the area storing FAT or the like with high access frequency is expanded in the RAM, the access speed can be increased, and the area accessed most recently by the history is discarded from the RAM. Therefore, it is possible to eliminate the waste that the address conversion table of the unnecessary area exists in the RAM.

  However, although there is no restriction on the size of the divided areas, an area that is known to have a high access frequency in which FAT is stored is used as one area. It is an address conversion table for one area and requires a RAM having a certain amount of capacity.

  However, not destroying the address conversion table of an area known to have a high access frequency does not absolutely guarantee that the address conversion table of an area with a high access frequency actually remains in the RAM. In addition, since the most recently accessed area is discarded from the RAM, there is a possibility that the most recently accessed area is discarded from the RAM regardless of whether the most recently accessed area is subsequently accessed.

  Further, according to the invention of Patent Document 2, since the size of the cache memory entry is 1 / N (integer) of the actual page size, there is an advantage that it is not necessary to increase the capacity of the address conversion table. However, the address conversion table is not designed in consideration of the access history and frequency, and there is a problem that the number of mishits increases and the access overhead increases.

  The present invention has been made in view of the current state of a logical-physical address translation table control method used for access control of the NAND flash memory as described above and a memory device using the control method. A method of controlling a logical / physical address translation table capable of reducing the capacity of a RAM for storing a logical / physical address translation table and reducing access overhead, and a memory using the control method Is to provide a device.

The logical / physical address conversion table control method according to the present invention converts a logical address into a physical address for use in accessing a NAND flash memory having a plurality of pages composed of a plurality of sectors. In the conversion table control method, an address set including a sector address indicating one sector of a page is used as an address set for converting one logical address to one physical address in the logical physical address conversion table in the RAM. , M (an integer less than the total number of pages) set , and for each set of the address set, the elapsed time from the previous reference and the reference count are used as reference frequency information, and the elapsed time from the previous reference Based on the reference count of the longest address set, the overlap of each address set reference count Performed with, by determining the target replaced based on the result of the weighting, and controlling the switching of the address set for each set.

  In the control method of the logical-physical address conversion table according to the present invention, the address set whose weighting result exceeds the threshold is to be replaced, and when there is no address set exceeding the threshold, the elapsed time from the last reference time is the longest. A long address set is determined as a replacement target.

A memory device according to the present invention stores a NAND flash memory having a plurality of pages composed of a plurality of sectors, and a logical physical address conversion table for converting a logical address into a physical address used for accessing the NAND flash memory. And a controller for controlling access to the NAND flash memory, the RAM includes one sector of a page as an address set for converting one logical address to one physical address. A logical-physical address conversion table in which M (an integer smaller than the total number of pages) set of address sets including a sector address instructing is stored is stored, and an elapsed time from the previous reference time is stored for each set of the address sets. And reference frequency as reference frequency information Based on the reference number of the longest address sets the elapsed time from the previous reference, performs weighting of each address set number of references by determining a target replaced based on the result of the weighting, the address set for each set It is characterized by comprising a table control means for controlling the exchange of.

In the memory device according to the present invention, the table control means replaces an address set whose weighting result exceeds a threshold value, and when there is no address set exceeding the threshold value, the elapsed time from the previous reference time is the longest. A long address set is determined as a replacement target.

  According to the present invention, an address set including a sector address indicating one sector of a certain page as an address set for converting one logical address to one physical address in the logical-physical address conversion table in the RAM, Since the set is stored (an integer smaller than the total number of pages), the capacity of the RAM for storing the logical physical address conversion table can be reduced. In addition, since the replacement of the address set for each set is controlled based on the reference frequency information for each set of address sets, it is possible to reduce the access overhead.

1 is a block diagram showing a configuration of a memory device according to an embodiment of the present invention. The figure which shows the relationship between the block of NAND type flash memory, a page, and a sector. The figure which shows the structure of the logical physical address conversion table with which the memory device which concerns on embodiment of this invention is equipped. The figure which shows the reference frequency information used with the control method of the logical physical address conversion table which concerns on embodiment of this invention. The figure which shows the reference frequency information used with the control method of the logical physical address conversion table which concerns on embodiment of this invention. The figure which shows the weight obtained by the weight regarding the reference frequency information used with the control method of the logical physical address conversion table which concerns on embodiment of this invention. 6 is a flowchart showing processing of a logical physical address conversion table control method according to an embodiment of the present invention. The figure which shows the structure of the logical physical address conversion table by the conventional whole surface expansion | deployment. The figure which shows the structure of the logical physical address conversion table by the conventional partial expansion.

  Embodiments of a logical-physical address conversion table control method and a memory device using the control method according to the present invention will be described below with reference to the accompanying drawings. In the drawings, the same components are denoted by the same reference numerals, and redundant description is omitted. FIG. 1 is a block diagram of a memory device according to the embodiment. The memory device includes a NAND flash memory 1 and a controller 2 that controls the NAND flash memory 1.

  As shown in FIG. 2, the NAND flash memory 1 is provided with blocks # 0 to #n which are erase units, and each block # 0 to #n is composed of a plurality of pages # 00 to # 0 nm. Has been. Each page # 00- # nm is a read / write unit. Furthermore, each page # 00- # nm is composed of a plurality of sectors # 000- # nmk. For example, the number of sectors k per page can be set to 8.

  The controller 2 is provided with a logical / physical address conversion table 21 constituted by a RAM. This RAM is a memory for storing a logical / physical address conversion table 21 for converting a logical address into a physical address used for accessing the NAND flash memory 1. Further, the controller 2 has an interface function with the host, and the memory device is connected to the host (computer) by the interface function of the controller 2.

  The logical-physical address conversion table 21 converts logical addresses into physical addresses for use in accessing a NAND flash memory having a plurality of pages composed of a plurality of sectors. As shown in FIG. 3, the logical / physical address conversion table 21 of the RAM has an M (an integer smaller than the total number of pages) set in which an address set for converting one logical address into a sector address indicating one sector of a page is set. It is configured in the RAM as being included. That is, a physical address of one address set is composed of page addresses (physical sectors in a page are continuous).

  The controller 2 is provided with table control means 22 realized by the operation of a processor (not shown) in the controller 2. The table control means 22 controls the replacement of the address set for each set based on the reference frequency information for each set of the address set.

  The table control means 22 controls the reference frequency information as an elapsed time from the previous reference time. For example, an address set having the longest elapsed time since the previous reference is set as a replacement target. Therefore, for example, when there is a data access request from the host, the logical-physical address conversion table 21 is referred to using the given logical address, but if it does not hit, it is stored in the NAND flash memory 1. Referring to the aforementioned file management information (information that converts a logical address to a physical address used for accessing the NAND flash memory 1 and is referred to as FAT (FILE ALLOCATION TABLE), etc.) A physical address is obtained and accessed, and the logical physical address conversion table 21 is updated.

  The table control means 22 may control the reference frequency information as the number of references. For example, the table control means 22 increments a counter of the address set referred to for each reference to the logical physical address conversion table 21 by one. If no hit is found when referring to the logical / physical address conversion table 21, the address set having the smallest count value of the counter may be replaced. That is, the address set having the smallest counter value can be erased, and the address set of the file management information used for access can be written instead of this address set.

  Address sets # 1, # 2, # 3,..., #M are stored in the logical / physical address conversion table 21 (RAM). At some point, as shown in FIG. 4, if the reference counts are 33, 43, 5,..., 67 and “5” of address set # 3 is the smallest, address set # 3 can be deleted, and a new address set of the aforementioned file management information used for access can be written in place of this address set # 3.

  The table control means 22 may use the reference frequency information as the elapsed time from the previous reference and the reference count. For example, the table control means 22 increments the address set counter referenced for each reference to the logical / physical address conversion table 21 and provides a timer for each address set to write the logical / physical address conversion table 21. Sometimes it can be started, and if there is a reference, it can be reset.

  When determining a replacement target, an address set whose elapsed time from the previous reference exceeds a threshold value is obtained, and in the case of a plurality of addresses, the address set with the smallest number of references can be targeted. Alternatively, an address set having a reference count smaller than a threshold value is obtained, and in the case of a plurality of address sets, an address set having the longest elapsed time from the previous reference can be targeted. Alternatively, for each address set, the elapsed time from the previous reference can be divided by the reference count, and the address set having the minimum value can be targeted.

  In addition, the address set reference count is weighted based on the reference count of the address set having the longest elapsed time since the previous reference as a reference (standard value), and the replacement target is determined based on the weighting result. Also good. For example, an address set having the smallest value obtained by subtracting the reference value from each address set reference count or a value obtained by dividing each address set reference count by the reference value can be determined as a replacement target.

  Further, the table control means 22 increments the counter of the address set referred to for each reference to the logical / physical address conversion table 21 and decrements the counter of the address set not referred to by one, and for each address set. A timer may be provided to start the process when the logical / physical address conversion table 21 is written, and reset when a reference is made.

  When the reference frequency information is the elapsed time and the number of references since the previous reference as described above, the reference count of the address set with the longest elapsed time since the previous reference is used as the standard, as follows: Thus, it is possible to weight each address set reference count and determine a replacement target based on the weighting result.

  For example, as shown in FIG. 5, the logical-physical address conversion table 21 stores an address set from A to E, and the elapsed time from the previous reference time is 10 seconds, 30 seconds, 50 seconds, 20 seconds. , 40 seconds, the reference order is 1, 3, 5, 2, 4. Further, it is assumed that the counter value of the reference count as described above is +10, −5, +20, +9, and +50 in order from A to E.

  Therefore, the reference for weighting as described above is the address set C having the longest elapsed time. In the weighting process, the count value of each address set is subtracted from the count value “+20” of the reference address set C to obtain the “weight” as the weighting result. As shown in FIG. 6, the “weights” that are the result of the address set weighting from A to E are +10, +25, 0, +11, and −30, respectively.

  Each of the above “weights” is compared with a threshold (in this case, +20), and an address set of “weight” exceeding the threshold is determined as a replacement target. In this example, since the address set B exceeds the threshold value (+20), it is determined as a replacement target. When there is no “weight” address set that exceeds the threshold, the reference address set is determined as a replacement target. Also, if there are multiple “weight” address sets that exceed the threshold, the one with the larger “weight” is replaced, and if the “weight” is the same, the higher (or lower) logical address is replaced. Can be the target of.

  For example, when a data access request is made from the host, the memory device including the table control unit 22 that performs the processing as described above operates according to a program corresponding to the flowchart shown in FIG.

  The process is started by a data access request, and the logical / physical address conversion table 21 is accessed based on the given logical address (S11). Whether a hit is detected by access is detected (S12). If a hit is found, the NAND flash memory 1 is accessed by the physical address obtained from the logical-physical address conversion table 21 (S13). At this time, the reference frequency information (reference count) is updated (S14).

  On the other hand, when a miss hit is detected in step S12, the file management information stored in the NAND flash memory 1 is referred to obtain a required physical address for access (S15). Further, the reference frequency is updated as reference frequency information, and the elapsed time from the previous reference time is obtained (S16).

  Subsequent to step S16, a replacement target address set is obtained based on the reference frequency information (S17), and the target address set is deleted from the logical physical address conversion table 21 (S18). Further, the address set used at the access in step S15 is stored in the erased RAM area (S19), and the process is ended.

  As described above, according to the control method of the logical / physical address conversion table of the present embodiment and the memory device using the control method, one logical address is converted into one physical address in the logical / physical address conversion table 21. As an address set to be converted, an address set including a sector address indicating one sector of a page is stored in an M (an integer smaller than the total number of pages) set RAM, so the capacity of the RAM is the capacity of the NAND flash memory. It can be smaller.

  In addition, since the address set for converting one logical address to one physical address indicates one sector of a page, discontinuous physical addresses are stored in the logical physical address conversion table 21 in units of sectors. In addition, since the switching of the address set for each set is controlled based on the reference frequency information for each set of address sets, the logical physical address conversion table 21 has a probability of hitting in the logical address conversion. High address sets are stored, and random sectors of the NAND flash memory can be accessed at high speed.

DESCRIPTION OF SYMBOLS 1 NAND type flash memory 2 Controller 21 Logical physical address conversion table 22 Table control means

Claims (4)

In a method for controlling a logical-physical address conversion table for converting a logical address into a physical address for use in accessing a NAND flash memory having a plurality of pages composed of a plurality of sectors,
As an address set for converting one logical address to one physical address in the logical physical address conversion table in the RAM, an address set including a sector address indicating one sector of a page is represented by M (from the total number of pages). Less integers) set stored,
For each set of the address sets, each address set is based on the number of references of the address set having the longest elapsed time since the previous reference, using the elapsed time and the reference count from the previous reference as reference frequency information. Weigh the reference count,
A logical-physical address conversion table control method, comprising: controlling a replacement of an address set for each set by determining a replacement target based on the weighting result . It is characterized in that an address set whose weighting result exceeds a threshold is subject to replacement, and if there is no address set exceeding the threshold, the address set having the longest elapsed time since the previous reference is determined as the subject of replacement. The method of controlling a logical physical address conversion table according to claim 1. A NAND flash memory comprising a plurality of pages composed of a plurality of sectors;
A controller that stores a logical address as a logical-physical address conversion table that converts a logical address into a physical address used for accessing the NAND flash memory, and that controls access to the NAND flash memory;
In a memory device comprising:
In the RAM, as an address set for converting one logical address to one physical address, an address set including a sector address indicating one sector of a page is provided as an M (an integer smaller than the total number of pages) set. Stored logical physical address conversion table,
For each set of the address sets, each address set is based on the number of references of the address set having the longest elapsed time since the previous reference, using the elapsed time and the reference count from the previous reference as reference frequency information. A memory device comprising table control means for controlling replacement of an address set for each set by weighting a reference count and determining a replacement target based on a weighting result. The table control means replaces an address set whose weighting result exceeds a threshold value, and if there is no address set exceeding the threshold value, replaces an address set having the longest elapsed time since the previous reference. 4. The memory device according to claim 3, wherein the memory device is determined.

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