JP6420222B2 - Optical receiver circuit and optical receiver module - Google Patents

Optical receiver circuit and optical receiver module Download PDF

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JP6420222B2
JP6420222B2 JP2015200210A JP2015200210A JP6420222B2 JP 6420222 B2 JP6420222 B2 JP 6420222B2 JP 2015200210 A JP2015200210 A JP 2015200210A JP 2015200210 A JP2015200210 A JP 2015200210A JP 6420222 B2 JP6420222 B2 JP 6420222B2
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light receiving
receiving element
bias
optical receiver
circuit
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JP2017073691A (en
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俊英 吉松
俊英 吉松
史人 中島
史人 中島
哲一郎 大野
哲一郎 大野
英二 吉田
英二 吉田
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日本電信電話株式会社
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Description

  The present invention relates to an optical receiver circuit and an optical receiver module that convert a high-speed optical signal into an electrical signal.

  Conventionally, one terminal (for example, the anode) of the light receiving element is connected to a load such as a transimpedance amplifier (TIA) or an external electric receiving circuit, and the other terminal (for example, the cathode) of the light receiving element has a high frequency. In general, an optical receiver circuit that is grounded (short-circuited) and connected to an external bias application terminal in terms of direct current is common. In this optical receiver circuit, in order to obtain a good ground for the high frequency signal of the other terminal of the light receiving element, it is necessary to arrange a bias separation circuit for separating the low frequency component and the high frequency component in the immediate vicinity of the light receiving element (patent) Reference 1).

  An example of a conventional optical receiving circuit including a light receiving element, an electric line, and a bias separation circuit is shown in FIGS. The optical receiving circuit includes a PD (photodiode) chip 100 and a submount 101. In the example of FIG. 11, in addition to the light receiving element 102 and the electric line 103, a bias separation circuit 104 is provided in the PD chip 100. The electric line 103 is connected to a signal output terminal 105 formed on the submount 101. A load resistor 108 is connected to the signal output terminal 105 via an inductor 107. A DC bias is applied to the cathode of the light receiving element 102 from a bias application terminal 106 formed on the submount 101 via a bias separation circuit 104.

  On the other hand, in the example of FIG. 12, the bias separation circuit 104 is arranged outside the PD chip 100 by connecting the cathode of the light receiving element 102 and the bias separation circuit 104 with an electric line 109. The electric line 109 is connected to a bias application terminal 106 formed on the submount 101. A bias separation circuit 104 is connected to the bias application terminal 106 via an inductor 110. A direct current bias is applied to the cathode of the light receiving element 102 from the external bias application terminal 111 through the bias separation circuit 104, the inductor 110, the bias application terminal 106 of the submount 101, and the electric line 109.

Japanese Patent No. 5291144

  The bias separation circuit 104 shown in FIGS. 11 and 12 requires a capacitor 1040 to ground the cathode of the light receiving element 102 at a high frequency. The required reverse bias voltage of a pin-PD generally used as a light receiving element for optical communication is about 2 to 10V. Therefore, if a pin-PD is used as the light receiving element 102 shown in FIG. 11, a capacitor having a withstand voltage of about 5 to 10 V formed on the semiconductor substrate in the PD chip 100 is connected to the bias separation circuit 104 in the PD chip 100. The capacitor 1040 can be used.

  However, since the required reverse bias voltage of an avalanche photodiode (APD) having a light receiving sensitivity characteristic higher than that of the pin-PD is about 20V to 100V, even if the APD is used for the light receiving element 102, the APD Since the required reverse bias voltage exceeds the withstand voltage of the capacitor in the PD chip 100, it is difficult to apply the APD to the optical receiving circuit shown in FIG. In addition, when the TIA is a load, there is a product including a bias separation circuit in the TIA chip. However, as in the PD chip, since a capacitor with a withstand voltage of about 5 to 10 V formed on the semiconductor substrate is used, it is difficult to apply the required reverse bias voltage of the APD to this capacitor.

  In the example of FIG. 12 in which the bias separation circuit 104 is disposed outside the PD chip 100, a high withstand voltage chip capacitor made of ceramic and metal can be used as the capacitor 1040 of the bias separation circuit 104, and the APD as the light receiving element 102. Can be used. However, when the electric line 109 is shortened and the bias separation circuit 104 is arranged in the immediate vicinity of the PD chip 100, the high withstand voltage chip capacitor 1040 in the bias separation circuit 104 becomes space with other optical components, electric components, electric wirings, and the like. May interfere. Therefore, particularly in a multi-channel optical receiver circuit, the light receiving element 102 may not be disposed at a position most suitable for optical coupling, or the degree of freedom of layout of electrical components and optical components may be impaired. There was a problem.

  On the other hand, when the bias separation circuit 104 is arranged away from the PD chip 100, the longer the electric line 109 is, the more the variation in the frequency characteristics of the gain of the optical reception circuit and the variation in the group delay frequency are shifted to the lower frequency side. However, when the influence of this fluctuation reaches the signal band, there is a problem that the waveform of the electric signal output from the optical receiving circuit is deteriorated.

13A is a diagram illustrating a result of calculating the frequency characteristics of the gain of the optical receiver circuit of FIG. 12, and FIG. 13B is a diagram illustrating a result of calculating the frequency characteristics of the group delay of the optical receiver circuit of FIG. It is. Here, the characteristic impedances of the electric lines 103 and 109 are Z A and Z B , the inductances of the inductors 107 and 110 are L A and L B , respectively, and the impedance of the load resistor 108 is Z L, and Z A = Z L = 50Ω. Z B = 25Ω, L A = L B = 0.1 nH. In addition, assuming that a 25 Gb / s NRZ (Non-Return-to-Zero) optical signal is received, a model capable of obtaining a 3 dB band of 22.7 GHz at a load of 50Ω was used for the light receiving element 102. The electrical length (electric length) of the electric line 103 was 1.5 mm. The electrical length of the electric line 109 was set to three types: 0 mm, 1.5 mm, and 3 mm. Reference numerals 200, 201, and 202 in FIG. 13A indicate gains when the electrical length of the electric line 109 is 0 mm, 1.5 mm, and 3 mm, respectively. Reference numerals 203, 204, and 205 in FIG. The group delay is shown when the electrical length is 0 mm, 1.5 mm, and 3 mm.

  As is clear from FIGS. 13A and 13B, the frequency region in which the frequency characteristics of the gain of the optical receiver circuit and the frequency characteristics of the group delay fluctuate as the electrical length of the electrical line 109 increases. Migrate to 22.7 GHz, which is a 3 dB band of the light receiving element 102, corresponds to an electrical length of 13.2 mm. However, if the electrical length of the electric line 109 is longer than 1.5 mm, which is about 1/10 of the electrical length, the light receiving element 102 It can be seen that this affects the 3 dB band. When the electrical length of the electrical line 109 is 3 mm, a gain fluctuation of 5 dB on the plus side and 25 dB on the minus side occurs in the 3 dB band of the light receiving element 102. Further, the group delay variation in the 3 dB band of the light receiving element reaches 170 ps, which corresponds to about four times 40 ps, which is a 1-bit period of the 25 Gb / s NRZ optical signal. Along with the gain fluctuation and the group delay fluctuation as described above, the waveform of the electric signal output from the optical receiver circuit of FIG. 12 deteriorates.

  The present invention has been made to solve the above-described problem, and an optical receiver circuit capable of suppressing fluctuations in frequency characteristics within the signal band of the optical receiver circuit even when the bias separation circuit is moved away from the light receiving element. And an optical receiver module.

An optical receiver circuit according to the present invention includes a light receiving element that converts an optical signal into an electric signal, a first electric line that connects between an anode of the light receiving element and a signal output terminal, and a cathode of the light receiving element. A bias separation circuit for applying a DC bias voltage to the cathode, a second electric line inserted between the cathode of the light receiving element and the bias separation circuit, the cathode of the light receiving element, and the bias A bias resistor inserted in series with the second electric line between the second circuit and the separation circuit, wherein the resistance value of the bias resistor is R B , the characteristic impedance of the second electric line is Z B , and the signal output when the impedance of the load connected to the terminal is set to Z L, the resistance R B of the bias resistor | a / 2 or less and then, and the characteristic impedance Z B of the second electric line | Z L Serial made equal to the resistance R B of the bias resistor is characterized in that to said bias resistor and impedance matching.

The optical receiver module of the present invention includes an optical receiver circuit and an amplifier circuit chip serving as a load connected to a signal output terminal of the optical receiver circuit, and the optical receiver circuit includes at least the first and the first elements. A submount including two electric lines and the bias resistor, and a light receiving element chip including the light receiving element mounted on the submount. A capacitor for grounding the cathode in an AC manner is disposed on the same carrier as the amplifier circuit chip, and the first terminal receiving the DC bias voltage from the outside is the bias resistor and the second electric line. Are connected to the cathode of the light receiving element through the second terminal, and the second terminal is grounded.
The optical receiver module of the present invention includes an optical receiver circuit and an amplifier circuit chip serving as a load connected to a signal output terminal of the optical receiver circuit, and the optical receiver circuit includes at least the first and the first elements. And a light receiving element chip including the light receiving element mounted on the submount, and the cathode of the light receiving element in the bias separation circuit is connected in an alternating manner. The capacitor for grounding and the bias resistor are disposed on the same carrier as the amplifier circuit chip, and the capacitor has a first terminal that receives supply of the DC bias voltage from the outside, and the bias resistor and the first resistor The second terminal is connected to the cathode of the light receiving element via two electric lines, and the second terminal is grounded.

Also, one configuration example of the optical receiver module of the present invention is characterized in that a composite component in which the capacitor and the bias resistor are connected is provided instead of separately providing the capacitor and the bias resistor. It is.
Moreover, in one configuration example of the optical receiver module of the present invention, the submount further includes a high-frequency ground disposed on the same plane as the first and second electric lines, and the high-frequency ground includes the amplification circuit. It is connected to the ground pad of the chip.

  According to the present invention, even when the bias separation circuit is moved away from the light receiving element, it is possible to suppress fluctuations in the frequency characteristics of the gain and group delay in the signal band of the optical reception circuit, and the output from the optical reception circuit. The deterioration of the waveform of the electrical signal can be suppressed. In the present invention, it is possible to provide a chip capacitor with a high withstand voltage as a capacitor of the bias separation circuit at a position away from the light receiving element, and to realize a highly sensitive optical receiving circuit using the light receiving element made of APD. It becomes possible. Further, according to the present invention, since the degree of freedom of the layout of the bias separation circuit can be increased, the light receiving element is arranged at a position most suitable for optical coupling, particularly in a multi-channel optical receiving circuit having a plurality of light receiving elements. In addition, since the degree of freedom in the layout of electrical components and optical components can be improved, it is possible to realize a mounting form that achieves both optical characteristics and electrical characteristics.

It is a figure which shows the structural example of the optical receiver circuit which concerns on embodiment of this invention. It is an equivalent circuit diagram of the optical receiver circuit according to the embodiment of the present invention. It is a figure which shows the example of the frequency characteristic of the gain of the optical receiver circuit which concerns on embodiment of this invention, and group delay. It is a figure which shows the example of the frequency characteristic of the gain of the optical receiver circuit which concerns on embodiment of this invention, and group delay. It is sectional drawing of the optical receiver module carrying the optical receiver circuit which concerns on embodiment of this invention. FIG. 6 is a side view of the PD chip and the submount of FIG. 5 viewed from the light incident direction. It is a top view which shows the example of mounting of the optical receiver module which concerns on embodiment of this invention. It is a top view which shows the other mounting example of the optical receiver module which concerns on embodiment of this invention. It is a top view which shows the other mounting example of the optical receiver module which concerns on embodiment of this invention. It is a top view which shows the other mounting example of the optical receiver module which concerns on embodiment of this invention. It is a figure which shows the structural example of the conventional optical receiver circuit. It is a figure which shows the other structural example of the conventional optical receiver circuit. It is a figure which shows the example of the frequency characteristic of the gain of a conventional optical receiver circuit, and group delay.

  The details of the embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram illustrating a configuration example of an optical receiver circuit according to an embodiment of the present invention. The optical receiver circuit according to the present embodiment includes a PD chip 1 (light receiving element chip), a submount 2 and a bias separation circuit 3. The PD chip 1 includes a light receiving element 4 such as an APD and an electric line 5 made of a conductor having one end connected to the anode of the light receiving element 4.

  The submount 2 made of an insulator is a member for mounting the PD chip 1, but can also be used as a circuit board. On the submount 2, the electric line 5, the electric line 6 made of a conductor inserted between the cathode of the light receiving element 4 of the PD chip 1 and the bias separation circuit 3, and the cathode of the light receiving element 4 and the bias separation circuit 3, a bias resistor 7 inserted in series with the electric line 6 is formed. An end portion of the electric line 5 formed on the submount 2 is connected to a signal output terminal 8 on the submount 2. A load resistor 11 is connected to the signal output terminal 8 via an inductor 10.

  A bias separation circuit 3 is connected to a bias application terminal 9 formed on the submount 2 via an inductor 12. The bias separation circuit 3 grounds the cathode of the light receiving element 4 in an AC manner and applies a DC bias voltage to the cathode. That is, a chip capacitor 30 for grounding the cathode of the light receiving element 4 in an alternating manner is provided in the bias separation circuit 3. A DC bias voltage is applied to the cathode of the light receiving element 4 from an external bias application terminal 13 through the bias separation circuit 3, the inductor 12, the bias resistor 7, and the electric line 6.

  In FIG. 1, the electric line 5 is described as a single line, but in practice, the electric line on the PD chip 1 and the electric line on the submount 2 are connected at the connection point between the PD chip 1 and the submount 2. By connecting the line, it becomes one line. The inductor 10 equivalently represents an inductance component such as a wire between the submount 2 and the load resistor 11, and the inductor 12 has an inductance such as a wire between the submount 2 and the bias separation circuit 3. It is an equivalent representation of the components.

In the present embodiment, when the resistance value of the bias resistor 7 is R B , the characteristic impedance of the electric line 6 is Z B , and the impedance of the load resistor 11 is Z L , the resistance value R B of the bias resistor 7 is | Z L. | / 2 or less, and the characteristic impedance Z B of the electric line 6 is made equal to the resistance value R B of the bias resistor 7 so as to be impedance matched with the bias resistor 7.

Hereinafter, the effect by the characteristic of this Embodiment is demonstrated. First, the relationship between the 3 dB band of the optical receiver circuit and the resistance value R B of the bias resistor 7 will be described using the small signal equivalent circuit of FIG. Here, the junction capacitance of the light receiving element 4 is C PD (F), the series resistance of the light receiving element 4 is R PD (Ω), and the effective carrier transit time is τ PD (s). The resistance value of the load resistor 11 is R L (Ω). For the sake of simplicity, the characteristic impedance Z A of the electric line 5 is assumed to be equal to the resistance value R L (Ω) of the load resistor 11, and the characteristic impedance of the electric line 6 is set to Z B = R B (Ω ) And the inductances 10 and 12 are assumed to be negligibly small.

The optical receiving circuit of FIG. 1 (the length of the electric line 6) is defined as f A, which is the ideal high-frequency cutoff frequency of the optical receiving circuit in which the electric line 6 is short enough to be electrically ignored and R B = 0 (Ω). is can not be ignored, the resistance value R B of the bias resistor 7 to a high cutoff frequency of greater than zero light receiving circuit) and f B. The high cut-off frequencies f A and f B can be expressed by the following equations, respectively.
1 / (2πf A ) 2 = (C PD (R PD + R L )) 2 + τ PD 2 (1)
1 / (2πf B ) 2 = (C PD (R PD + R L + R B )) 2 + τ PD 2 (2)

Therefore, the higher the resistance value R B of the bias resistor 7, the lower the high-frequency cutoff frequency f B of the optical receiver circuit in FIG. Here, the resistance value R B of the bias resistor 7 is provided with a condition as shown in the equation (3).
R B ≦ R L / 2 (3)

When the condition of the expression (3) is provided, the following expression is established.
((C PD (R PD + R L )) 2 + τ PD 2 )
/ ((C PD (R PD + 1.5R L )) 2 + τ PD 2 ) × f A 2 ≦ f B 2 ≦ f A 2 (4)
That is, it is possible to suppress the reduction of the high cutoff frequency f B.

As an example, when the junction capacitance C PD of the light receiving element 4 is 70 fF, the series resistance R PD of the light receiving element 4 is 20Ω, the resistance value R L of the load resistor 11 is 50Ω, and the carrier transit time τ PD is 5 ps, it is ideal. The high-frequency cutoff frequency f A of the optical receiving circuit is 22.7 GHz, and 0.841 × f A ≦ f B ≦ f A is established. That is, according to the optical receiver circuit of the present embodiment, it can be seen that a band of 84% of the high-frequency cutoff frequency f A of the ideal optical receiver circuit can be secured. Furthermore, as described in Patent Document 1, it is possible to design to minimize the decrease in the high-frequency cutoff frequency f B by utilizing the band improvement effect by the optimized design of inductance and line impedance. .

Note that generalizing equation (3) gives the following equation.
R B ≦ | Z L | / 2 (5)
As described above, Z L is the impedance of the load resistor 11.

FIG. 3A is a diagram illustrating a result of calculating the frequency characteristics of the gain of the optical receiver circuit of the present embodiment, and FIG. 3B is a diagram illustrating the frequency characteristics of the group delay of the optical receiver circuit of the present embodiment. FIGS. 4 (A) and 4 (B) showing the results are enlarged views of FIGS. 3 (A) and 3 (B), respectively. Here, in order to simplify the calculation, Z A = Z L = 50Ω and Z B = R B = 25Ω. Further, the inductance L A of the inductor 10, the inductor 12 inductance L B are both set to 0.1 nH.

  Similar to FIGS. 13A and 13B shown as calculation examples of the frequency characteristics of the conventional example, the light receiving element 4 uses a model that can obtain a 3 dB band of 22.7 GHz under a load of 50Ω. The electrical length of 5 was 1.5 mm, and the electrical length of the electrical line 6 was 0 mm, 1.5 mm, and 3 mm. Reference numerals 300, 301, and 302 in FIG. 3A and FIG. 4A indicate gains when the electrical length of the electrical line 6 is 0 mm, 1.5 mm, and 3 mm, respectively. , 303, 304, and 305 indicate group delays when the electrical length of the electrical line 6 is 0 mm, 1.5 mm, and 3 mm, respectively.

  As is apparent from FIGS. 3A, 3B, 4A, and 4B, according to the present embodiment, the gain fluctuation and the group delay fluctuation are the same as those in the conventional example shown in FIG. (A) is clearly less than FIG. 13 (B).

  FIG. 5 is a cross-sectional view of an optical receiver module on which the optical receiver circuit of this embodiment is mounted. The PD chip 1 is flip-chip mounted on the submount 2. The submount 2 is fixed to a PLC (Planar Lightwave Circuit) carrier 15 via a fixing component 14. A PLC 16 is mounted on the PLC carrier 15. An optical signal propagating through the optical waveguide 17 formed in the PLC 16 passes through the microlens array 18 and enters the light receiving element 4 of the PD chip 1.

  On the other hand, a TIA chip 21 (amplifier circuit chip) and a chip capacitor 30 of the bias separation circuit 3 are formed on a TIA carrier 20 mounted on the same base plate 19 as the PLC carrier 15. The TIA chip 21 amplifies the current signal output from the signal output terminal (signal output terminal 8 in FIG. 1) of the optical receiving circuit and simultaneously converts it into a voltage signal. That is, in the configuration of FIG. 5, the TIA chip 21 is a load of the optical receiving circuit.

  In the example of the present embodiment, as shown in FIG. 1, the bias separation circuit 3 is configured only by the chip capacitor 30. A bonding wire 22 is electrically connected between the submount 2 and the TIA chip 21 and between the submount 2 and the first terminal of the chip capacitor 30. A DC bias voltage is supplied to the first terminal of the chip capacitor 30 from the outside via a bonding wire (not shown). Further, the second terminal of the chip capacitor 30 is grounded to the TIA carrier 20 via a bonding wire (not shown) or an electrode formed on the back surface of the chip capacitor 30.

  Here, it is assumed that the optical receiver circuit receives a multi-channel optical signal and outputs a multi-channel electrical signal. As described above, the technique of mounting the multi-channel PD chip 1 on the submount 2 and electrically connecting the multi-channel TIA chip 21 is described in the document “S. Tsunashima, et al.,“ Silica-based, compact and variable-optical attenuator integrated coherent receiver with stable optoelectronic coupling system ", Optics Express, Vol. 20, Issue 24, pp. 27174-27179, 2012".

  6 is a side view of the PD chip 1 and the submount 2 of FIG. 5 as viewed from the light incident direction, and FIG. 7 is a plan view of the light reception module of FIG. Here, an example of the PD chip 1 including the light receiving elements 4 for four channels will be described. However, in FIG. 7, the configuration on the PLC carrier 15 side in FIG. 5 is simplified and only the microlens array 18 is illustrated.

  The submount 2 includes a high-frequency ground 23 made of a conductor together with the electric lines 5 and 6 and the bias resistor 7, a high-frequency ground 23 on the surface of the submount 2 (the surface on which the PD chip 1 is mounted), and a high-frequency ground on the back surface. A through-hole via 24 that is electrically connected is formed. As described above, the PD chip 1 is flip-chip mounted on the submount 2, whereby the anode of the light receiving element 4 is connected to the electric line 5 of the submount 2, and the cathode of the light receiving element 4 is the electric line 6 of the submount 2. Connected.

  An end portion (signal output terminal 8 in FIG. 1) of the electric line 5 of the submount 2 is electrically connected to a signal input pad 25 on the TIA chip 21 by a bonding wire 22a. The end of the electric line 6 of the submount 2 (the bias applying terminal 9 in FIG. 1) is electrically connected to the first terminal of the chip capacitor 30 by the bonding wire 22b. The high frequency ground 23 of the submount 2 is electrically connected to the ground pad 26 on the TIA carrier 20 or the TIA chip 21 by a bonding wire 22c.

  When the high frequency ground 23 of the submount 2 is not electrically connected to the TIA carrier 20 but is electrically connected to the TIA chip 21, the high frequency ground 23 of the submount 2 is galvanically insulated from other wirings. Since the DC potential does not have to be 0 V, as shown in FIG. 8, the bias pad 27 on the TIA chip 21 connected to the bias separation circuit 3a in the TIA chip 21 and the high frequency ground 23 are connected to the bonding wire 22d. It is also possible to connect by. The bias separation circuit 3a is a circuit that is conventionally mounted in the TIA chip 21, but in the present invention, the bias separation circuit 3 (chip capacitor 30) provided outside the TIA chip 21 is used. A bias voltage is not supplied to the light receiving element 4 from the separation circuit 3a. Since a bias voltage (for example, about 3 V) for supply to the light receiving element 4 is generated in the bias separation circuit 3a, this bias voltage is applied to the high frequency ground 23 via the bias pad 27. 23 is merely raised, and the light receiving element 4 is not affected.

  The bias resistor 7 may be arranged on the submount 2 or outside the submount 2 as shown in FIGS. 1 and 6, and the bias resistor 7, the inductor 12, and the bias separation circuit 3. Are electrically equivalent if they are close together within a distance that can be regarded as a lumped constant. When the bias resistor 7 is disposed on the submount 2, it is sufficient to form a resistor on the substrate. Since such a technique is common, the realization is easy.

  On the other hand, when the bias resistor 7 is disposed outside the submount 2, for example, a chip resistor disposed on the TIA carrier 20 is used as the bias resistor 7 as shown in FIG. One end of the bias resistor 7 may be electrically connected by the bonding wire 22b, and the other end of the bias resistor 7 and the first terminal of the chip capacitor 30 may be electrically connected by the bonding wire 22e.

  Alternatively, as shown in FIG. 10, a composite component 28 in which the bias resistor 7 and the chip capacitor 30 are electrically connected is arranged on the TIA carrier 20, and the end of the electric line 6 of the submount 2 and the bias resistor 7 are arranged. One end of each may be electrically connected by a bonding wire 22b.

  In FIGS. 9 and 10, the case where the present invention is applied to a configuration in which the high-frequency ground 23 of the submount 2 and the ground pad 26 on the TIA chip 21 are connected is described. However, the present invention is not limited to this. The bias resistor 7 and the chip capacitor 30 described in FIG. 10 may be applied to a configuration (FIG. 8) in which the high-frequency ground 23 and the bias pad 27 on the TIA chip 21 are connected.

  As described above, in this embodiment, even if the bias separation circuit 3 is moved away from the light receiving element 4, it is possible to suppress fluctuations in frequency characteristics within the signal band of the optical receiving circuit. In the present embodiment, since fluctuations in the frequency characteristics within the signal band of the optical receiver circuit can be suppressed, it is possible to provide a high withstand voltage chip capacitor as the capacitor 30 of the bias separation circuit 3 outside the PD chip 1. Thus, it is possible to realize a highly sensitive light receiving circuit using the light receiving element 4 made of APD. Further, in this embodiment, since the degree of freedom of the layout of the bias separation circuit 3 can be increased, the light receiving element is located at the most suitable position for optical coupling, particularly in a multi-channel optical receiving circuit including a plurality of light receiving elements 4. 4 can be arranged, and the degree of freedom in the layout of electrical components and optical components can be improved, so that a mounting form in which both optical characteristics and electrical characteristics are compatible is possible.

  The present invention can be applied to an optical receiving module that converts an optical signal into an electric signal.

  DESCRIPTION OF SYMBOLS 1 ... PD chip, 2 ... Submount, 3 ... Bias separation circuit, 4 ... Light receiving element, 5, 6 ... Electric line, 7 ... Bias resistance, 8 ... Signal output terminal, 9, 13 ... Bias application terminal, 10, 12 DESCRIPTION OF SYMBOLS ... Inductor, 11 ... Load resistance, 14 ... Fixed component, 15 ... PLC carrier, 16 ... PLC, 17 ... Optical waveguide, 18 ... Microlens array, 19 ... Base plate, 20 ... TIA carrier, 21 ... TIA chip, 22 DESCRIPTION OF SYMBOLS Bonding wire, 23 ... High frequency ground, 24 ... Through-hole via, 25 ... Signal input pad, 26 ... Ground pad, 27 ... Bias pad, 28 ... Composite component, 30 ... Chip capacitor

Claims (6)

  1. A light receiving element that converts an optical signal into an electrical signal;
    A first electrical line connecting between the anode of the light receiving element and the signal output terminal;
    A bias separation circuit for grounding the cathode of the light receiving element in an alternating manner and applying a DC bias voltage to the cathode;
    A second electrical line inserted between the cathode of the light receiving element and the bias separation circuit;
    A bias resistor inserted in series with the second electric line between the cathode of the light receiving element and the bias separation circuit;
    When the resistance value of the bias resistor is R B , the characteristic impedance of the second electric line is Z B , and the impedance of the load connected to the signal output terminal is Z L , the resistance value R B of the bias resistor is | Z L | / 2 or less, and the characteristic impedance Z B of the second electric line is made equal to the resistance value R B of the bias resistor so as to be impedance matched with the bias resistor.
  2. An optical receiver circuit according to claim 1;
    An amplifier circuit chip serving as a load connected to the signal output terminal of the optical receiver circuit;
    The optical receiving circuit is:
    A submount comprising at least the first and second electric lines and the bias resistor;
    A light receiving element chip including the light receiving element, which is mounted on the submount;
    A capacitor for grounding the cathode of the light receiving element in an AC manner in the bias separation circuit is disposed on the same carrier as the amplifier circuit chip, and receives a supply of the DC bias voltage from the outside. Is connected to the cathode of the light receiving element via the bias resistor and the second electric line, and the second terminal is grounded.
  3. An optical receiver circuit according to claim 1;
    An amplifier circuit chip serving as a load connected to the signal output terminal of the optical receiver circuit;
    The optical receiving circuit is:
    A submount including at least the first and second electric lines;
    A light receiving element chip including the light receiving element, which is mounted on the submount;
    Of the bias separation circuit, a capacitor for grounding the cathode of the light receiving element in an alternating manner and the bias resistor are disposed on the same carrier as the amplifier circuit chip,
    In the capacitor, a first terminal that receives the supply of the DC bias voltage from the outside is connected to the cathode of the light receiving element via the bias resistor and the second electric line, and a second terminal is grounded. An optical receiver module.
  4. The optical receiver module according to claim 3, wherein
    Instead of providing the capacitor and the bias resistor separately, an optical receiver module comprising a composite component in which the capacitor and the bias resistor are connected internally.
  5. The optical receiver module according to any one of claims 2 to 4,
    The submount further includes a high frequency ground arranged on the same plane as the first and second electric lines,
    The high-frequency ground is connected to a ground pad of the amplifier circuit chip.
  6. The optical receiver module according to any one of claims 2 to 4,
    The submount further includes a high frequency ground arranged on the same plane as the first and second electric lines,
    The optical receiver module, wherein the high-frequency ground is connected to a bias pad of the amplifier circuit chip.
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