JP6373052B2 - Liquid crystal display - Google Patents

Liquid crystal display Download PDF

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Publication number
JP6373052B2
JP6373052B2 JP2014091847A JP2014091847A JP6373052B2 JP 6373052 B2 JP6373052 B2 JP 6373052B2 JP 2014091847 A JP2014091847 A JP 2014091847A JP 2014091847 A JP2014091847 A JP 2014091847A JP 6373052 B2 JP6373052 B2 JP 6373052B2
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electrode
liquid crystal
pixel electrode
crystal display
common
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JP2015148790A (en
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荒井 則博
則博 荒井
小林 君平
君平 小林
水迫 亮太
亮太 水迫
旬平 大畠
旬平 大畠
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株式会社 オルタステクノロジー
株式会社 オルタステクノロジー
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    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
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    • G02F1/134309Electrodes characterised by their geometrical arrangement
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    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
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    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
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    • G02F1/134381Hybrid switching mode, i.e. for applying an electric field with components parallel and orthogonal to the substrates
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    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362Active matrix addressed cells
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    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
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    • G02F1/136286Wiring, e.g. gate line, drain line
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    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
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    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
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    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
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Description

本発明は、液晶表示装置に関する。   The present invention relates to a liquid crystal display device.

液晶表示パネルにおいては、TN(Twisted Nematic)モード、VA(Vertical Alignment)モード、及びIPS(In-Plane Switching)/FFS(Fringe Field Switching)モードなどが用いられているが、広視野角、高コントラストの要求から、VAモード、及びIPS/FFSモードが主流となっている。しかし、VAモード、及びIPS/FFSモードは応答性が十分でなく、動画表示には問題がある。また、応答性を改善して動画表示に対応できるOCB(Optically Compensated Bend)モード、及びTBA(Transverse Bend Alignment)モードも提案されている。   Liquid crystal display panels use TN (Twisted Nematic) mode, VA (Vertical Alignment) mode, IPS (In-Plane Switching) / FFS (Fringe Field Switching) mode, etc., but have a wide viewing angle and high contrast. Therefore, VA mode and IPS / FFS mode have become mainstream. However, the VA mode and the IPS / FFS mode are not sufficiently responsive, and there is a problem in displaying moving images. In addition, an OCB (Optically Compensated Bend) mode and a TBA (Transverse Bend Alignment) mode that can cope with moving image display with improved responsiveness have been proposed.

OCBモードは、高速な応答性を示す一方で、電源投入時に、初期配向であるスプレイ配向から駆動(例えば電圧10V以上を印加)時のベンド配向への転移操作が必要となり、通常の駆動回路の他に初期転移用駆動回路が必要になる。このため、OCBモードは、コストアップにつながるとともに、電源に制約があるモバイル機器には適さないという問題がある。   While the OCB mode shows high-speed response, when the power is turned on, a transition operation from the splay alignment, which is the initial alignment, to the bend alignment at the time of driving (for example, applying a voltage of 10 V or more) is required. In addition, an initial transition drive circuit is required. For this reason, the OCB mode has a problem that it leads to an increase in cost and is not suitable for a mobile device with a limited power source.

また、TBAモードは、カラーフィルター基板側の共通電極上に誘電体膜が設けられるため、この誘電体膜に起因したDCアンバランスにより焼き付きが発生しやすいという問題がある。また、通常の駆動電圧(例えば5V程度)では斜め電界が弱いため、透過率が低くなるという問題がある。   Further, the TBA mode has a problem that burn-in is likely to occur due to DC imbalance caused by the dielectric film because a dielectric film is provided on the common electrode on the color filter substrate side. In addition, the normal drive voltage (for example, about 5V) has a problem that the transmittance is lowered because the oblique electric field is weak.

特開2010−217853号公報JP 2010-217853 A

本発明は、応答速度、及び透過率を向上させることが可能な液晶表示装置を提供する。   The present invention provides a liquid crystal display device capable of improving response speed and transmittance.

本発明の一態様に係る液晶表示装置は、対向配置された第1及び第2基板と、前記第1及び第2基板間に挟持され、p型の液晶材料からなり、電界を印加しない状態で垂直配向をとる液晶層と、前記第1基板に設けられ、第1方向に延びる画素電極と、前記第1基板に設けられ、それぞれが前記第1方向に延びる第1及び第2電極部分を含み、前記第1及び第2電極部分は、前記第1方向に直交する第2方向における前記画素電極の両側に間隔を空けて配置される、第1共通電極と、前記第2基板に設けられ、それぞれが前記第1方向に延びる第3乃至第5電極部分を含む第2共通電極とを具備する。前記第3及び第4電極部分はそれぞれ、平面投影において前記第1及び第2電極部分と少なくとも一部が重なり、前記第5電極部分は、平面投影において前記画素電極と少なくとも一部が重なる。 A liquid crystal display device according to one embodiment of the present invention includes a first substrate and a second substrate which are arranged to face each other, and a p-type liquid crystal material which is sandwiched between the first and second substrates, in a state where no electric field is applied. wherein a liquid crystal layer takes a vertical orientation, is provided on the first substrate, a pixel electrode extending in a first direction, provided on the first substrate, the first and second electrode portions each extending in the first direction The first and second electrode portions are provided on the second substrate , the first common electrode being disposed on both sides of the pixel electrode in a second direction orthogonal to the first direction, and spaced apart from each other . And a second common electrode including third to fifth electrode portions each extending in the first direction . Each of the third and fourth electrode portions overlaps at least partially with the first and second electrode portions in planar projection, and the fifth electrode portion overlaps at least partially with the pixel electrode in planar projection.

本発明の一態様に係る液晶表示装置は、対向配置された第1及び第2基板と、前記第1及び第2基板間に挟持され、p型の液晶材料からなり、電界を印加しない状態で垂直配向をとる液晶層と、前記第1基板に設けられ、第1方向に延びる画素電極と、前記第1基板に設けられ、それぞれが前記第1方向に延びる第1及び第2電極部分を含み、前記第1及び第2電極部分は、前記第1方向に直交する第2方向における前記画素電極の両側に間隔を空けて配置される、第1共通電極と、前記第2基板に設けられ、それぞれが前記第1方向に延びる第3及び第4電極部分を含み、前記第3及び第4電極部分はそれぞれ、平面投影において前記第1及び第2電極部分と少なくとも一部が重なる、第2共通電極とを具備する。前記第3電極部分と前記画素電極との距離は、前記第1電極部分と前記画素電極との距離より小さく、前記第4電極部分と前記画素電極との距離は、前記第2電極部分と前記画素電極との距離より小さい。A liquid crystal display device according to one embodiment of the present invention includes a first substrate and a second substrate which are arranged to face each other, and a p-type liquid crystal material which is sandwiched between the first and second substrates, in a state where no electric field is applied. A liquid crystal layer having vertical alignment; a pixel electrode provided on the first substrate; extending in a first direction; and first and second electrode portions provided on the first substrate, each extending in the first direction. The first and second electrode portions are provided on the second substrate, the first common electrode being disposed on both sides of the pixel electrode in a second direction orthogonal to the first direction, and spaced apart from each other. Each includes third and fourth electrode portions extending in the first direction, and each of the third and fourth electrode portions is at least partially overlapped with the first and second electrode portions in a planar projection. Electrode. The distance between the third electrode portion and the pixel electrode is smaller than the distance between the first electrode portion and the pixel electrode, and the distance between the fourth electrode portion and the pixel electrode is equal to the second electrode portion and the pixel electrode. It is smaller than the distance to the pixel electrode.

本発明によれば、応答速度及び透過率を向上させることが可能な液晶表示装置を提供することができる。   ADVANTAGE OF THE INVENTION According to this invention, the liquid crystal display device which can improve a response speed and the transmittance | permeability can be provided.

本発明の第1実施形態に係る液晶表示装置のブロック図。1 is a block diagram of a liquid crystal display device according to a first embodiment of the present invention. 図1に示した液晶表示パネルに含まれる画素アレイの回路図。FIG. 2 is a circuit diagram of a pixel array included in the liquid crystal display panel shown in FIG. 1. 第1実施形態に係る液晶表示パネルの模式的な断面図。1 is a schematic cross-sectional view of a liquid crystal display panel according to a first embodiment. 液晶表示パネルのレイアウト図。The layout diagram of a liquid crystal display panel. 反射膜を除いた液晶表示パネルのレイアウト図。The layout figure of the liquid crystal display panel except a reflecting film. 図4に示したA−A´線に沿った液晶表示パネルの断面図。Sectional drawing of the liquid crystal display panel along the AA 'line shown in FIG. 図4に示したB−B´線に沿った液晶表示パネルの断面図。Sectional drawing of the liquid crystal display panel along the BB 'line shown in FIG. 液晶層側から見たCF基板のレイアウト図及び断面図。The layout view and sectional drawing of CF board | substrate seen from the liquid crystal layer side. 液晶層の配向状態を説明する図。6A and 6B illustrate an alignment state of a liquid crystal layer. 実施例に係る液晶表示パネルの応答速度を説明するグラフ。The graph explaining the response speed of the liquid crystal display panel which concerns on an Example. 第1比較例における応答速度を説明するグラフ。The graph explaining the response speed in a 1st comparative example. 第2比較例における応答速度を説明するグラフ。The graph explaining the response speed in a 2nd comparative example. 本発明の第2実施形態に係るCF基板のレイアウト図及び断面図。The layout drawing and sectional drawing of CF board concerning a 2nd embodiment of the present invention. 液晶層の配向状態を説明する図。6A and 6B illustrate an alignment state of a liquid crystal layer. 本発明の第3実施形態に係るTFT基板のレイアウト図。The layout figure of the TFT substrate which concerns on 3rd Embodiment of this invention. 液晶層側から見たCF基板のレイアウト図。FIG. 3 is a layout diagram of a CF substrate viewed from the liquid crystal layer side. 図15及び図16に示したC−C´線に沿った液晶表示パネルの断面図。Sectional drawing of the liquid crystal display panel along CC 'line shown in FIG.15 and FIG.16. 本発明の第4実施形態に係る液晶表示パネルの模式的な断面図。FIG. 6 is a schematic cross-sectional view of a liquid crystal display panel according to a fourth embodiment of the present invention. 第4実施形態に係るA−A´線に沿った液晶表示パネルの断面図。Sectional drawing of the liquid crystal display panel along the AA 'line which concerns on 4th Embodiment. 第4実施形態に係るB−B´線に沿った液晶表示パネルの断面図。Sectional drawing of the liquid crystal display panel along the BB 'line which concerns on 4th Embodiment. 共通電極及び画素電極の距離に関するパラメータを説明する図。The figure explaining the parameter regarding the distance of a common electrode and a pixel electrode. 比較例に係る液晶分子の配向状態を説明する図。The figure explaining the orientation state of the liquid crystal molecule which concerns on a comparative example. 第4実施形態に係る液晶分子の配向状態を説明する図。The figure explaining the orientation state of the liquid crystal molecule which concerns on 4th Embodiment. 第5実施形態に係るA−A´線に沿った液晶表示パネルの断面図。Sectional drawing of the liquid crystal display panel along the AA 'line which concerns on 5th Embodiment. 第5実施形態に係るB−B´線に沿った液晶表示パネルの断面図。Sectional drawing of the liquid crystal display panel along the BB 'line which concerns on 5th Embodiment.

以下、実施形態について図面を参照して説明する。ただし、図面は模式的または概念的なものであり、各図面の寸法および比率等は必ずしも現実のものと同一とは限らないことに留意すべきである。また、図面の相互間で同じ部分を表す場合においても、互いの寸法の関係や比率が異なって表される場合もある。特に、以下に示す幾つかの実施形態は、本発明の技術思想を具体化するための装置および方法を例示したものであって、構成部品の形状、構造、配置等によって、本発明の技術思想が特定されるものではない。なお、以下の説明において、同一の機能及び構成を有する要素については同一符号を付し、重複説明は必要な場合にのみ行う。   Hereinafter, embodiments will be described with reference to the drawings. However, it should be noted that the drawings are schematic or conceptual, and the dimensions and ratios of the drawings are not necessarily the same as the actual ones. Further, even when the same portion is represented between the drawings, the dimensional relationship and ratio may be represented differently. In particular, the following embodiments exemplify an apparatus and a method for embodying the technical idea of the present invention, and the technical idea of the present invention depends on the shape, structure, arrangement, etc. of components. Is not specified. In the following description, elements having the same function and configuration are denoted by the same reference numerals, and redundant description will be given only when necessary.

[第1実施形態]
[1.液晶表示装置の回路構成]
まず、液晶表示装置10の回路構成の一例について説明する。図1は、本発明の第1実施形態に係る液晶表示装置10のブロック図である。本実施形態では、アクティブマトリクス型の液晶表示装置10を例に挙げて説明する。
[First Embodiment]
[1. Circuit configuration of liquid crystal display device]
First, an example of the circuit configuration of the liquid crystal display device 10 will be described. FIG. 1 is a block diagram of a liquid crystal display device 10 according to the first embodiment of the present invention. In the present embodiment, the active matrix type liquid crystal display device 10 will be described as an example.

液晶表示装置10は、液晶表示パネル11、走査ドライバ(走査線駆動回路)12、信号ドライバ(信号線駆動回路)13、共通電圧供給回路14、電圧発生回路15、及び制御回路16を備える。   The liquid crystal display device 10 includes a liquid crystal display panel 11, a scanning driver (scanning line driving circuit) 12, a signal driver (signal line driving circuit) 13, a common voltage supply circuit 14, a voltage generation circuit 15, and a control circuit 16.

液晶表示パネル11には、それぞれがロウ方向(X方向)に延びる複数の走査線GLと、それぞれがカラム方向(Y方向)に延びる複数の信号線SLとが配設される。複数の走査線GLと複数の信号線SLとの交差領域の各々には、画素17が配置される。複数の画素17は、マトリクス状に配置される。   The liquid crystal display panel 11 is provided with a plurality of scanning lines GL each extending in the row direction (X direction) and a plurality of signal lines SL each extending in the column direction (Y direction). A pixel 17 is disposed in each of the intersecting regions of the plurality of scanning lines GL and the plurality of signal lines SL. The plurality of pixels 17 are arranged in a matrix.

図2は、図1に示した液晶表示パネル11に含まれる画素アレイの回路図である。図2では、4つの画素を抽出して示している。画素17は、スイッチング素子18、液晶容量Clc、及び蓄積容量Csを備える。スイッチング素子18としては、例えばTFT(Thin Film Transistor)が用いられる。   FIG. 2 is a circuit diagram of a pixel array included in the liquid crystal display panel 11 shown in FIG. In FIG. 2, four pixels are extracted and shown. The pixel 17 includes a switching element 18, a liquid crystal capacitor Clc, and a storage capacitor Cs. For example, a TFT (Thin Film Transistor) is used as the switching element 18.

TFT18のソースは、信号線SLに電気的に接続される。TFT18のゲートは、走査線GLに電気的に接続される。TFT18のドレインは、液晶容量Clcに電気的に接続される。液晶容量Clcは、画素電極と、共通電極と、これらに挟まれた液晶層とにより構成される。   The source of the TFT 18 is electrically connected to the signal line SL. The gate of the TFT 18 is electrically connected to the scanning line GL. The drain of the TFT 18 is electrically connected to the liquid crystal capacitor Clc. The liquid crystal capacitor Clc includes a pixel electrode, a common electrode, and a liquid crystal layer sandwiched between them.

蓄積容量Csは、液晶容量Clcに並列接続される。蓄積容量Csは、画素電極に生じる電位変動を抑制するとともに、画素電極に印加された駆動電圧を次の信号に対応する駆動電圧が印加されるまでの間保持する機能を有する。蓄積容量Csは、画素電極と、蓄積電極(蓄積容量線)と、これらに挟まれた絶縁膜とにより構成される。共通電極及び蓄積電極には、共通電圧供給回路14により共通電圧Vcomが印加される。   The storage capacitor Cs is connected in parallel to the liquid crystal capacitor Clc. The storage capacitor Cs has a function of suppressing the potential fluctuation generated in the pixel electrode and holding the drive voltage applied to the pixel electrode until the drive voltage corresponding to the next signal is applied. The storage capacitor Cs includes a pixel electrode, a storage electrode (storage capacitor line), and an insulating film sandwiched between them. A common voltage Vcom is applied to the common electrode and the storage electrode by the common voltage supply circuit 14.

図1において、走査ドライバ12は、複数の走査線GLに接続され、制御回路16から垂直制御信号Vsを受ける。走査ドライバ12は、垂直制御信号Vsに基づいて、TFT18のオン及びオフを制御するための走査信号を走査線GLに印加する。   In FIG. 1, the scanning driver 12 is connected to a plurality of scanning lines GL and receives a vertical control signal Vs from the control circuit 16. The scanning driver 12 applies a scanning signal for controlling on / off of the TFT 18 to the scanning line GL based on the vertical control signal Vs.

信号ドライバ13は、複数の信号線SLに接続され、制御回路16から水平制御信号Hs、及び表示データD2を受ける。信号ドライバ13は、水平制御信号Hsに基づいて、表示データD2に対応する階調信号(駆動電圧)を信号線SLに印加する。共通電圧供給回路14は、共通電圧Vcomを生成してこれを液晶表示パネル11に供給する。   The signal driver 13 is connected to the plurality of signal lines SL, and receives the horizontal control signal Hs and the display data D2 from the control circuit 16. The signal driver 13 applies a gradation signal (drive voltage) corresponding to the display data D2 to the signal line SL based on the horizontal control signal Hs. The common voltage supply circuit 14 generates a common voltage Vcom and supplies it to the liquid crystal display panel 11.

制御回路16は、外部から画像データD1を受ける。制御回路16は、画像データD1から表示データD2を生成する。また、制御回路16は、交流駆動(反転駆動)を行うために、所定期間(例えば、1フレーム、1フィールド、又は1ライン)毎に反転信号Polを生成する。そして、制御回路16は、垂直制御信号Vsを走査ドライバ12に送り、水平制御信号Hs、表示データD2、及び反転信号Polを信号ドライバ13に送り、反転信号Polを共通電圧供給回路14に送る。これに対応して、信号ドライバ13は、反転信号Polが入力される毎に、駆動電圧の極性を反転させる。同様に、共通電圧供給回路14は、反転信号Polが入力される毎に、共通電圧Vcomの極性を反転させる。これにより、液晶表示パネル11の交流駆動を実現することができる。   The control circuit 16 receives image data D1 from the outside. The control circuit 16 generates display data D2 from the image data D1. Further, the control circuit 16 generates an inversion signal Pol every predetermined period (for example, one frame, one field, or one line) in order to perform AC driving (inversion driving). Then, the control circuit 16 sends the vertical control signal Vs to the scanning driver 12, sends the horizontal control signal Hs, display data D 2, and the inverted signal Pol to the signal driver 13, and sends the inverted signal Pol to the common voltage supply circuit 14. In response to this, the signal driver 13 inverts the polarity of the drive voltage every time the inverted signal Pol is input. Similarly, the common voltage supply circuit 14 inverts the polarity of the common voltage Vcom every time the inverted signal Pol is input. Thereby, the alternating current drive of the liquid crystal display panel 11 is realizable.

電圧発生回路15は、走査信号を生成するために必要なゲート電圧を生成してこれを走査ドライバ12に供給する。また、電圧発生回路15は、画素を駆動するために必要な駆動電圧を生成してこれを信号ドライバ13に供給する。この他にも必要に応じて、電圧発生回路15は、液晶表示装置10の動作に必要な各種電圧を生成して各回路部に供給する。   The voltage generation circuit 15 generates a gate voltage necessary for generating a scanning signal and supplies it to the scanning driver 12. The voltage generation circuit 15 generates a drive voltage necessary for driving the pixel and supplies the drive voltage to the signal driver 13. In addition, the voltage generation circuit 15 generates various voltages necessary for the operation of the liquid crystal display device 10 and supplies them to each circuit unit as necessary.

このように構成された液晶表示装置10において、任意の画素17に含まれるTFT18がオン状態となると、駆動電圧が信号線SLを介して画素電極に印加され、駆動電圧と共通電圧Vcomとの電圧差に応じて液晶の配向状態が変化する。これにより、光源から液晶表示パネル11に入射する光の透過状態が変化して画像表示が行われる。   In the liquid crystal display device 10 configured as described above, when the TFT 18 included in an arbitrary pixel 17 is turned on, a driving voltage is applied to the pixel electrode via the signal line SL, and the voltage between the driving voltage and the common voltage Vcom is determined. The alignment state of the liquid crystal changes according to the difference. Thereby, the transmission state of the light incident on the liquid crystal display panel 11 from the light source is changed, and image display is performed.

[2.液晶表示パネルの構成]
図3は、本発明の第1実施形態に係る液晶表示パネル11の模式的な断面図である。
液晶表示パネル11の表示面と反対面には、面光源(バックライト)20が対向配置される。このバックライト20は、例えば、サイドライト型(エッジライト型)のバックライト装置が用いられる。すなわち、バックライト20は、LED(発光ダイオード)等からなる複数の発光素子が導光板の端面から入射するように構成され、導光板の一方の板面から画素アレイへ向けて光が出射される。例えば、バックライト20は、反射シート、導光板、拡散シート、及びプリズムシートが積層されて構成される。
[2. Configuration of LCD panel]
FIG. 3 is a schematic cross-sectional view of the liquid crystal display panel 11 according to the first embodiment of the present invention.
A surface light source (backlight) 20 is disposed opposite to the surface opposite to the display surface of the liquid crystal display panel 11. For the backlight 20, for example, a sidelight type (edge light type) backlight device is used. That is, the backlight 20 is configured such that a plurality of light emitting elements such as LEDs (light emitting diodes) are incident from the end face of the light guide plate, and light is emitted from one plate surface of the light guide plate toward the pixel array. . For example, the backlight 20 is configured by laminating a reflection sheet, a light guide plate, a diffusion sheet, and a prism sheet.

液晶表示パネル11は、スイッチング素子としてのTFT、及び画素電極などが形成されるTFT基板21と、カラーフィルター及び共通電極などが形成されかつTFT基板21に対向配置されたカラーフィルター基板(CF基板)22と、TFT基板21及びCF基板22間に挟持された液晶層23とを備える。TFT基板21及びCF基板22の各々は、透明基板(例えば、ガラス基板)から構成される。   The liquid crystal display panel 11 includes a TFT substrate 21 on which TFTs as switching elements, pixel electrodes, and the like are formed, and a color filter substrate (CF substrate) on which a color filter and a common electrode are formed and disposed opposite to the TFT substrate 21. 22 and a liquid crystal layer 23 sandwiched between the TFT substrate 21 and the CF substrate 22. Each of the TFT substrate 21 and the CF substrate 22 is composed of a transparent substrate (for example, a glass substrate).

液晶層23は、TFT基板21及びCF基板22間を貼り合わせるシール材(図示せず)によって封入された液晶材料により構成される。また、液晶層23のセルギャップは、液晶層23内に設けられたスペーサー(図示せず)によって制御される。液晶材料は、電界に応じて液晶分子の配向が制御されて光学特性が変化する。本実施形態では、液晶層23は、ポジ型(p型)液晶材料からなり、電圧(電界)を印加していない状態(初期配向状態)で基板面に対してほぼ垂直に配向させる(垂直配向に設定される)。よって、本実施形態の液晶層23では、無電圧(無電界)時には、液晶分子の長軸(ダイレクタ)が垂直に配向し、電圧印加(電界印加)時には、液晶分子のダイレクタが電界方向に向かって傾く。   The liquid crystal layer 23 is made of a liquid crystal material sealed with a sealing material (not shown) that bonds the TFT substrate 21 and the CF substrate 22 together. The cell gap of the liquid crystal layer 23 is controlled by a spacer (not shown) provided in the liquid crystal layer 23. In the liquid crystal material, the orientation of liquid crystal molecules is controlled according to the electric field, and the optical characteristics change. In this embodiment, the liquid crystal layer 23 is made of a positive (p-type) liquid crystal material, and is aligned substantially perpendicular to the substrate surface in a state where no voltage (electric field) is applied (initial alignment state) (vertical alignment). To be set). Therefore, in the liquid crystal layer 23 of the present embodiment, the major axis (director) of the liquid crystal molecules is aligned vertically when there is no voltage (no electric field), and the director of the liquid crystal molecules faces the electric field direction when a voltage is applied (electric field application). Lean.

TFT基板21の液晶層23側には、画素17ごとに、TFT18、及び画素電極24が設けられる。また、TFT基板21には、画素電極24を挟む又は囲むように形成された共通電極25(共通電極25−1、25−2を含む)が設けられる。さらに、TFT基板21には、画素電極24、及び共通電極25−1、25−2を覆うように配向膜26が設けられる。   A TFT 18 and a pixel electrode 24 are provided for each pixel 17 on the liquid crystal layer 23 side of the TFT substrate 21. The TFT substrate 21 is provided with a common electrode 25 (including common electrodes 25-1 and 25-2) formed so as to sandwich or surround the pixel electrode 24. Further, an alignment film 26 is provided on the TFT substrate 21 so as to cover the pixel electrode 24 and the common electrodes 25-1 and 25-2.

CF基板22の液晶層23側には、カラーフィルター27が設けられる。カラーフィルター27は、複数の着色フィルター(着色部材)を備え、具体的には、複数の赤フィルター27−R、複数の緑フィルター27−G、及び複数の青フィルター27−Bを備える。一般的なカラーフィルターは光の三原色である赤(R)、緑(G)、青(B)で構成される。隣接したR、G、Bの三色のセットが表示の単位(ピクセル、又は画素と呼ぶ)となっており、1つの画素中のR、G、Bのいずれか単色の部分はサブピクセル(サブ画素)と呼ばれる最小駆動単位である。TFT18及び画素電極24は、サブピクセルごとに設けられる。以下の説明では、画素とサブ画素との区別が特に必要な場合を除き、サブ画素を画素と呼ぶものとする。   A color filter 27 is provided on the liquid crystal layer 23 side of the CF substrate 22. The color filter 27 includes a plurality of coloring filters (coloring members), and specifically includes a plurality of red filters 27-R, a plurality of green filters 27-G, and a plurality of blue filters 27-B. A general color filter is composed of three primary colors of light, red (R), green (G), and blue (B). A set of three colors R, G, and B adjacent to each other is a display unit (referred to as a pixel or a pixel), and any single color portion of R, G, or B in one pixel is a subpixel (subpixel). This is a minimum drive unit called a pixel. The TFT 18 and the pixel electrode 24 are provided for each subpixel. In the following description, a subpixel is referred to as a pixel unless it is particularly necessary to distinguish between a pixel and a subpixel.

画素(サブ画素)の境界部分には、遮光用のブラックマトリクス(遮光膜)BMが設けられる。例えば、ブラックマトリクスBMは、網目状に形成される。ブラックマトリクスBMは、例えば、着色部材間の不要な光を遮蔽し、コントラストを向上させるために設けられる。   A black matrix (light-shielding film) BM for light shielding is provided at the boundary between the pixels (sub-pixels). For example, the black matrix BM is formed in a mesh shape. The black matrix BM is provided, for example, to shield unnecessary light between the coloring members and improve contrast.

カラーフィルター27及びブラックマトリクスBM上には、平面投影(平面視)において共通電極25−1、25−2に重なるように形成された共通電極28(共通電極28−1、28−2を含む)が設けられる。すなわち、CF基板22側の共通電極28は、平面状に形成されておらず、直線状、又は格子状に形成される。CF基板22上には、共通電極28−1、28−2を覆うように配向膜29が設けられる。   On the color filter 27 and the black matrix BM, the common electrode 28 (including the common electrodes 28-1 and 28-2) formed so as to overlap the common electrodes 25-1 and 25-2 in a planar projection (plan view). Is provided. That is, the common electrode 28 on the CF substrate 22 side is not formed in a planar shape, but is formed in a linear shape or a lattice shape. An alignment film 29 is provided on the CF substrate 22 so as to cover the common electrodes 28-1 and 28-2.

円偏光板30、33は、TFT基板21及びCF基板22を挟むように設けられる。円偏光板30は、バックライト20からの入射光を円偏光させる。円偏光板33は、表示面からの入射光を円偏光させるとともに、液晶層23を透過した透過光を直線偏光させる。円偏光板30は、位相差板31、及び偏光板32から構成される。円偏光板33は、位相差板34、及び偏光板35から構成される。   The circularly polarizing plates 30 and 33 are provided so as to sandwich the TFT substrate 21 and the CF substrate 22. The circularly polarizing plate 30 circularly polarizes incident light from the backlight 20. The circularly polarizing plate 33 circularly polarizes incident light from the display surface and linearly polarizes transmitted light transmitted through the liquid crystal layer 23. The circularly polarizing plate 30 includes a retardation plate 31 and a polarizing plate 32. The circularly polarizing plate 33 includes a retardation plate 34 and a polarizing plate 35.

偏光板32、35は、光の進行方向に直交する平面内において、互いに直交する透過軸及び吸収軸を有する。偏光板32、35は、ランダムな方向の振動面を有する光のうち、透過軸に平行な振動面を有する直線偏光(直線偏光した光成分)を透過し、吸収軸に平行な振動面を有する直線偏光(直線偏光した光成分)を吸収する。偏光板32、35は、互いの透過軸が直交するように、すなわち直交ニコル状態で配置される。   The polarizing plates 32 and 35 have a transmission axis and an absorption axis orthogonal to each other in a plane orthogonal to the light traveling direction. The polarizing plates 32 and 35 transmit linearly polarized light (linearly polarized light component) having a vibration surface parallel to the transmission axis out of light having vibration surfaces in random directions, and have a vibration surface parallel to the absorption axis. Absorbs linearly polarized light (linearly polarized light component). The polarizing plates 32 and 35 are disposed so that their transmission axes are orthogonal to each other, that is, in an orthogonal Nicol state.

位相差板31、34は、屈折率異方性を有しており、光の進行方向に直交する平面内において、互いに直交する遅相軸及び進相軸を有する。位相差板31、34は、遅相軸と進相軸とをそれぞれ透過する所定波長の光の間に所定のリタデーション(λを透過する光の波長としたとき、λ/4の位相差)を与える機能を有している。すなわち、位相差板31、34は、λ/4板から構成される。位相差板31の遅相軸は、偏光板32の透過軸に対して45°の角度をなすように設定される。位相差板34の遅相軸は、偏光板35の透過軸に対して45°の角度をなすように設定される。   The phase difference plates 31 and 34 have refractive index anisotropy, and have a slow axis and a fast axis that are perpendicular to each other in a plane perpendicular to the light traveling direction. The phase difference plates 31 and 34 have a predetermined retardation (a phase difference of λ / 4 when λ is a wavelength of light transmitted) between light of a predetermined wavelength that transmits the slow axis and the fast axis, respectively. Has the function to give. That is, the phase difference plates 31 and 34 are composed of λ / 4 plates. The slow axis of the phase difference plate 31 is set to form an angle of 45 ° with respect to the transmission axis of the polarizing plate 32. The slow axis of the phase difference plate 34 is set to make an angle of 45 ° with respect to the transmission axis of the polarizing plate 35.

[3.液晶表示パネル11の具体例]
次に、液晶表示パネル11のより具体的な構成例について説明する。以下に、半透過型液晶表示パネル11を例に挙げて説明する。半透過型液晶表示パネル11は、外光を反射することによって画像を表示する反射領域と、バックライト光を透過することによって画像を表示する透過領域とを1画素内に有する。
[3. Specific example of the liquid crystal display panel 11]
Next, a more specific configuration example of the liquid crystal display panel 11 will be described. Hereinafter, the transflective liquid crystal display panel 11 will be described as an example. The transflective liquid crystal display panel 11 has a reflection area for displaying an image by reflecting external light and a transmission area for displaying an image by transmitting backlight light in one pixel.

図4は、液晶表示パネル11のレイアウト図である。図4のレイアウト図は、TFT基板21の構成を主として示しており、また、1画素分のレイアウトを示している。図5は、図4から反射膜を除いた液晶表示パネル11のレイアウト図である。図6は、図4に示したA−A´線に沿った液晶表示パネル11の断面図である。図7は、図4に示したB−B´線に沿った液晶表示パネル11の断面図である。なお、図6及び図7の断面図では、図3に示した円偏光板30、33と、配向膜26、29との図示を省略している。   FIG. 4 is a layout diagram of the liquid crystal display panel 11. The layout diagram of FIG. 4 mainly shows the configuration of the TFT substrate 21 and shows the layout for one pixel. FIG. 5 is a layout diagram of the liquid crystal display panel 11 excluding the reflective film from FIG. FIG. 6 is a cross-sectional view of the liquid crystal display panel 11 taken along line AA ′ shown in FIG. FIG. 7 is a cross-sectional view of the liquid crystal display panel 11 along the line BB ′ shown in FIG. 6 and 7, the circularly polarizing plates 30 and 33 shown in FIG. 3 and the alignment films 26 and 29 are not shown.

TFT基板21上には、X方向に延びる走査線(ゲート電極)GLが設けられる。走査線GLは、TFT18のゲート電極として機能する。また、TFT基板21上には、X方向に延びる蓄積容量線40が設けられる。蓄積容量線40は、画素電極24との間で、図2に示す蓄積容量Csを構成する。TFT基板21上には、ゲート電極GL、及び蓄積容量線40を覆うように絶縁膜41が設けられる。ゲート電極GL上の絶縁膜41は、TFT18のゲート絶縁膜として機能する。   On the TFT substrate 21, a scanning line (gate electrode) GL extending in the X direction is provided. The scanning line GL functions as a gate electrode of the TFT 18. A storage capacitor line 40 extending in the X direction is provided on the TFT substrate 21. The storage capacitor line 40 constitutes the storage capacitor Cs shown in FIG. An insulating film 41 is provided on the TFT substrate 21 so as to cover the gate electrode GL and the storage capacitor line 40. The insulating film 41 on the gate electrode GL functions as a gate insulating film of the TFT 18.

ゲート電極GLの上方かつ絶縁膜41上には、半導体層42が設けられる。この半導体層42は、例えば、アモルファスシリコン、又はポリシリコンから構成される。ゲート電極GLの両側かつ絶縁膜41上には、ソース電極43及びドレイン電極44が設けられる。ソース電極43及びドレイン電極44はそれぞれ、半導体層42に部分的に接触する。TFT18は、ゲート電極GL、ゲート絶縁膜41、ソース電極43、及びドレイン電極44から構成される。   A semiconductor layer 42 is provided above the gate electrode GL and on the insulating film 41. The semiconductor layer 42 is made of, for example, amorphous silicon or polysilicon. A source electrode 43 and a drain electrode 44 are provided on both sides of the gate electrode GL and on the insulating film 41. Each of the source electrode 43 and the drain electrode 44 is in partial contact with the semiconductor layer 42. The TFT 18 includes a gate electrode GL, a gate insulating film 41, a source electrode 43, and a drain electrode 44.

また、絶縁膜41上には、Y方向に延びる信号線SLが設けられる。信号線SLは、ソース電極43に電気的に接続される。信号線SLは、ブラックマトリクスBKの下方に配置される。   A signal line SL extending in the Y direction is provided on the insulating film 41. The signal line SL is electrically connected to the source electrode 43. The signal line SL is disposed below the black matrix BK.

TFT18及び信号線SL上には、絶縁膜45が設けられる。絶縁膜45上には、TFT18を覆うように形成された反射膜46が設けられる。画素17の反射領域は、反射膜46が形成された領域に対応する。画素17の透過領域は、反射膜46及び蓄積容量線40が形成された領域以外の領域に対応する。反射膜46上には、絶縁膜47が設けられる。   An insulating film 45 is provided on the TFT 18 and the signal line SL. A reflective film 46 is provided on the insulating film 45 so as to cover the TFT 18. The reflective area of the pixel 17 corresponds to the area where the reflective film 46 is formed. The transmissive region of the pixel 17 corresponds to a region other than the region where the reflective film 46 and the storage capacitor line 40 are formed. An insulating film 47 is provided on the reflective film 46.

絶縁膜47上には、画素電極24、及び共通電極25が設けられる。画素電極24は、画素17の中央部をY方向に延びるように直線状に形成され、コンタクトプラグ48によってドレイン電極44に電気的に接続される。画素電極24の幅は、より細い方が望ましいが、製造方法による制約を勘案すると、実際には、2〜3μm程度に設定される。なお、図4の構成例では、ドレイン電極44は、半導体層42に部分的に接触する第1の電極部分と、この第1の電極部分からコンタクトプラグ48の下まで延びる第2の電極分とから構成される。   A pixel electrode 24 and a common electrode 25 are provided on the insulating film 47. The pixel electrode 24 is formed linearly so as to extend in the Y direction at the center of the pixel 17 and is electrically connected to the drain electrode 44 by a contact plug 48. The width of the pixel electrode 24 is preferably narrower, but is actually set to about 2 to 3 μm in consideration of restrictions due to the manufacturing method. In the configuration example of FIG. 4, the drain electrode 44 includes a first electrode portion that partially contacts the semiconductor layer 42, and a second electrode portion that extends from the first electrode portion to below the contact plug 48. Consists of

共通電極25は、所定の間隔を空けて画素電極24を挟む又は囲むように形成される。図4の構成例では、共通電極25は、画素電極24を囲むように形成される。具体的には、共通電極25は、画素電極24をX方向両側から所定の間隔を空けて挟むように配置されかつそれぞれがY方向に延びる直線状の共通電極25−1、25−2と、共通電極25−1、25−2を電気的に接続しかつそれぞれがX方向に延びる直線状の共通電極25−3、25−4とから構成される基本単位を含み、この基本単位が四方に格子状にかつ画素に対応するように配置されて構成される。画素電極24と共通電極25との間隔は、15μm以下が望ましく、さらに3〜4μm程度がより望ましい。また、共通電極25−1、25−2は、平面投影において、信号線SLを覆うように形成される。これにより、信号線SLに起因する不要な電界が液晶層23に印加されるのを防ぐことができる。   The common electrode 25 is formed so as to sandwich or surround the pixel electrode 24 with a predetermined interval. In the configuration example of FIG. 4, the common electrode 25 is formed so as to surround the pixel electrode 24. Specifically, the common electrode 25 is arranged so as to sandwich the pixel electrode 24 from both sides in the X direction at a predetermined interval, and each of the common electrodes 25 extends linearly in the Y direction. Including a basic unit that is electrically connected to the common electrodes 25-1 and 25-2 and includes linear common electrodes 25-3 and 25-4 each extending in the X direction. It is arranged in a grid pattern and corresponding to the pixels. The distance between the pixel electrode 24 and the common electrode 25 is preferably 15 μm or less, and more preferably about 3 to 4 μm. The common electrodes 25-1 and 25-2 are formed so as to cover the signal line SL in the planar projection. Thereby, it is possible to prevent an unnecessary electric field due to the signal line SL from being applied to the liquid crystal layer 23.

図8は、液晶層23側から見たCF基板22のレイアウト図及び断面図である。図8(a)がCF基板22のレイアウト図、図8(b)が図8(a)に示したC−C´線に沿ったCF基板22の断面図である。図8は、3画素分のレイアウトを示している。図8には、ストライプ配列のカラーフィルター27を一例として図示している。   FIG. 8 is a layout view and a sectional view of the CF substrate 22 as viewed from the liquid crystal layer 23 side. FIG. 8A is a layout diagram of the CF substrate 22, and FIG. 8B is a cross-sectional view of the CF substrate 22 taken along the line CC ′ shown in FIG. 8A. FIG. 8 shows a layout for three pixels. FIG. 8 illustrates a stripe-arranged color filter 27 as an example.

CF基板22上には、画素の境界に配置された格子状のブラックマトリクスBMが設けられる。CF基板22及びブラックマトリクスBM上には、カラーフィルター27(赤フィルター27−R、緑フィルター27−G、及び青フィルター27−Bを含む)が設けられる。   On the CF substrate 22, a grid-like black matrix BM arranged at the boundary of the pixels is provided. A color filter 27 (including a red filter 27-R, a green filter 27-G, and a blue filter 27-B) is provided on the CF substrate 22 and the black matrix BM.

カラーフィルター27上には、画素の境界に配置された格子状の共通電極28が設けられる。共通電極28は、TFT基板21側に形成された共通電極25とほぼ同じ平面形状を有し、また、平面投影において共通電極25に重なるように配置される。具体的には、共通電極28は、画素電極24をX方向両側から挟みかつY方向に延びる直線状の共通電極28−1、28−2と、共通電極28−1、28−2を電気的に接続しかつX方向に延びる直線状の共通電極28−3、28−4とから構成される基本単位を含み、この基本単位が四方に格子状にかつ画素に対応するように配置されて構成される。   On the color filter 27, a grid-like common electrode 28 disposed at a pixel boundary is provided. The common electrode 28 has substantially the same planar shape as the common electrode 25 formed on the TFT substrate 21 side, and is disposed so as to overlap the common electrode 25 in planar projection. Specifically, the common electrode 28 electrically connects the linear common electrodes 28-1 and 28-2 and the common electrodes 28-1 and 28-2 that sandwich the pixel electrode 24 from both sides in the X direction and extend in the Y direction. And includes a basic unit composed of linear common electrodes 28-3 and 28-4 extending in the X direction, and the basic units are arranged in a lattice shape in four directions and corresponding to the pixels. Is done.

なお、本実施形態において、共通電極25と共通電極28とが重なるという表現は、平面投影において共通電極25と共通電極28とが完全に重なる場合と、部分的に、すなわち一部が重なる場合とを含む。共通電極28の太さは、共通電極25の太さと同じであってもよいし、異なっていてもよい。共通電極25の太さと共通電極28の太さとが異なるように液晶表示パネル11を構成した場合、共通電極25と共通電極28とは、互いが対向する部分において少なくとも一部が重なるように形成される。また、共通電極25と共通電極28とが重なるという表現は、製造方法及び製造工程に起因する誤差や合わせずれに起因して互いがずれて形成され、互いの少なくとも一部が重なることを許容するものとする。   In the present embodiment, the expression that the common electrode 25 and the common electrode 28 overlap each other includes a case where the common electrode 25 and the common electrode 28 are completely overlapped in a planar projection and a case where the common electrode 25 and the common electrode 28 overlap partially. including. The thickness of the common electrode 28 may be the same as or different from the thickness of the common electrode 25. When the liquid crystal display panel 11 is configured so that the thickness of the common electrode 25 and the thickness of the common electrode 28 are different, the common electrode 25 and the common electrode 28 are formed so that at least a part thereof overlaps with each other in a portion facing each other. The In addition, the expression that the common electrode 25 and the common electrode 28 overlap each other is formed by being shifted from each other due to an error or misalignment caused by the manufacturing method and manufacturing process, and at least a part of each other is allowed to overlap. Shall.

画素電極24、コンタクトプラグ48、及び共通電極25、28は、透明電極から構成され、例えばITO(インジウム錫酸化物)が用いられる。絶縁膜41、45、47は、透明な絶縁材料から構成され、例えばシリコン窒化物(SiN)が用いられる。反射膜46としては、例えば、アルミニウム(Al)、銀(Ag)、又はこれらのいずれかを含む合金が用いられる。ソース電極43、ドレイン電極44、走査線GL、信号線SL、及び蓄積容量線40は、例えば、アルミニウム(Al)、モリブデン(Mo)、クロム(Cr)、タングステン(W)のいずれか、またはこれらの1種類以上を含む合金等が用いられる。   The pixel electrode 24, the contact plug 48, and the common electrodes 25 and 28 are made of transparent electrodes, and for example, ITO (indium tin oxide) is used. The insulating films 41, 45, and 47 are made of a transparent insulating material, and for example, silicon nitride (SiN) is used. As the reflective film 46, for example, aluminum (Al), silver (Ag), or an alloy containing any of these is used. The source electrode 43, the drain electrode 44, the scanning line GL, the signal line SL, and the storage capacitor line 40 are, for example, aluminum (Al), molybdenum (Mo), chromium (Cr), tungsten (W), or these An alloy containing one or more of the above is used.

なお、上記説明では、反射領域と透過領域とを含む半透過型液晶表示パネル11の構成例について説明している。しかし、反射領域を含まない透過型液晶表示パネル11に本実施形態を適用することも可能である。   In the above description, a configuration example of the transflective liquid crystal display panel 11 including the reflective region and the transmissive region has been described. However, the present embodiment can also be applied to the transmissive liquid crystal display panel 11 that does not include a reflective region.

透過型液晶表示パネル11は、半透過型液晶表示パネル11の構成から反射膜46を除いて構成され、すなわち、透過型液晶表示パネル11のレイアウト図は、図5と同じである。さらに、透過型液晶表示パネル11の断面図は、図7の反射膜46を除いた断面図と同じである。   The transmissive liquid crystal display panel 11 is configured by removing the reflective film 46 from the configuration of the transflective liquid crystal display panel 11, that is, the layout diagram of the transmissive liquid crystal display panel 11 is the same as FIG. Further, the cross-sectional view of the transmissive liquid crystal display panel 11 is the same as the cross-sectional view excluding the reflective film 46 of FIG.

[4.動作]
次に、上記のように構成された液晶表示装置10の動作について説明する。まず、液晶層23に電界を印加していない状態での表示について説明する。図9(a)は、液晶層23に電界を印加していない状態での液晶分子の配向状態を説明する図である。
[4. Operation]
Next, the operation of the liquid crystal display device 10 configured as described above will be described. First, display in a state where no electric field is applied to the liquid crystal layer 23 will be described. FIG. 9A is a diagram for explaining the alignment state of the liquid crystal molecules in the state where no electric field is applied to the liquid crystal layer 23.

共通電圧供給回路14は、共通電極25、28に共通電圧Vcom(例えば0V)を印加し、信号ドライバ13は、画素電極24に共通電圧Vcomを印加する。なお、半透過型液晶表示パネル11の場合、共通電圧供給回路14は、反射膜46にも共通電圧Vcomを印加する。これにより、反射膜46の下方の配線及び電極に起因する電界が液晶層23に印加されるのを防ぐことができる。   The common voltage supply circuit 14 applies a common voltage Vcom (for example, 0 V) to the common electrodes 25 and 28, and the signal driver 13 applies the common voltage Vcom to the pixel electrode 24. In the case of the transflective liquid crystal display panel 11, the common voltage supply circuit 14 also applies a common voltage Vcom to the reflective film 46. Thereby, it is possible to prevent an electric field due to the wiring and electrodes below the reflective film 46 from being applied to the liquid crystal layer 23.

図9(a)の電圧関係では、液晶層23に電界が印加されていない状態(オフ状態)となり、液晶分子は、初期配向を維持する。すなわち、本実施形態では、液晶分子が基板面に対してほぼ垂直に配向する。このオフ状態において、バックライト20からの入射光は、円偏光板30と、リタデーションがほぼゼロの状態の液晶層23とを順に透過した後、円偏光板33に吸収される。これにより、液晶表示装置10は、黒表示となる。   In the voltage relationship of FIG. 9A, no electric field is applied to the liquid crystal layer 23 (off state), and the liquid crystal molecules maintain the initial alignment. That is, in this embodiment, the liquid crystal molecules are aligned substantially perpendicular to the substrate surface. In this OFF state, incident light from the backlight 20 is sequentially absorbed by the circularly polarizing plate 33 after passing through the circularly polarizing plate 30 and the liquid crystal layer 23 having a substantially zero retardation. As a result, the liquid crystal display device 10 displays black.

次に、液晶層23に電界を印加した状態での表示について説明する。図9(b)は、液晶層23に電界を印加した状態での液晶分子の配向状態を説明する図である。共通電圧供給回路14は、共通電極25、28に共通電圧Vcom(例えば0V)を印加し、信号ドライバ13は、画素電極24に共通電圧Vcomより高い駆動電圧(例えば5V)を印加する。   Next, display in a state where an electric field is applied to the liquid crystal layer 23 will be described. FIG. 9B is a diagram for explaining the alignment state of the liquid crystal molecules in the state where an electric field is applied to the liquid crystal layer 23. The common voltage supply circuit 14 applies a common voltage Vcom (for example, 0 V) to the common electrodes 25 and 28, and the signal driver 13 applies a drive voltage (for example, 5 V) higher than the common voltage Vcom to the pixel electrode 24.

図9(b)の電圧関係(オン状態)では、液晶層23には、画素電極24と共通電極25との間に生じる横電界と、画素電極24と共通電極28との間に生じる斜め電界とが印加される。これにより、液晶層23は、ハーフベンド配向(ベンド配向の片側半分)をとり、液晶分子は、画素電極24の中心を通る垂線に対して共通電極25、28の方向に向かって傾く。具体的には、画素電極24及び共通電極25に近いほど液晶分子の傾きが大きくなり、画素電極24から共通電極28に近づくにつれて液晶分子の傾きが小さくなる。また、共通電極28を画素電極24から斜め方向に配置したことで、液晶層23に斜め電界をより大きく印加できる。これにより、画素電極24の上方の液晶分子も傾けることができるため、透過率を向上させることができる。   In the voltage relationship (ON state) of FIG. 9B, the liquid crystal layer 23 has a lateral electric field generated between the pixel electrode 24 and the common electrode 25 and an oblique electric field generated between the pixel electrode 24 and the common electrode 28. Are applied. As a result, the liquid crystal layer 23 takes half-bend alignment (one side half of the bend alignment), and the liquid crystal molecules are inclined in the direction of the common electrodes 25 and 28 with respect to the normal passing through the center of the pixel electrode 24. Specifically, the closer to the pixel electrode 24 and the common electrode 25, the larger the inclination of the liquid crystal molecules, and the closer the pixel electrode 24 to the common electrode 28, the smaller the inclination of the liquid crystal molecules. Further, since the common electrode 28 is disposed obliquely from the pixel electrode 24, a larger oblique electric field can be applied to the liquid crystal layer 23. Thereby, the liquid crystal molecules above the pixel electrode 24 can also be tilted, so that the transmittance can be improved.

このオン状態において、バックライト20からの入射光は、円偏光板30を透過した後、液晶層23を透過して所定のリタデーションが付与され、さらに液晶層23を透過した透過光は、円偏光板33を透過する。これにより、液晶表示装置10は、白表示(実際には、カラーフィルターに対応したカラー表示)となる。   In this ON state, incident light from the backlight 20 passes through the circularly polarizing plate 30 and then passes through the liquid crystal layer 23 to be given a predetermined retardation. Further, the transmitted light that passes through the liquid crystal layer 23 is circularly polarized light. It passes through the plate 33. As a result, the liquid crystal display device 10 performs white display (actually, color display corresponding to the color filter).

[5.効果]
以上詳述したように第1実施形態では、液晶層23は、p型(ポジ型)液晶材料からなり、また、電界が印加されていない状態で液晶分子をほぼ垂直に配向させる。また、TFT基板21に、直線状の画素電極24と、この画素電極24を所定の間隔を空けて囲む又は挟むように形成された共通電極25を設ける。さらに、CF基板22に、共通電極25とほぼ同じ平面形状を有し、共通電極25と少なくとも一部が重なるように形成された共通電極28を設ける。
[5. effect]
As described above in detail, in the first embodiment, the liquid crystal layer 23 is made of a p-type (positive) liquid crystal material, and aligns liquid crystal molecules substantially vertically in the state where an electric field is not applied. Further, the TFT substrate 21 is provided with a linear pixel electrode 24 and a common electrode 25 formed so as to surround or sandwich the pixel electrode 24 with a predetermined interval. Further, the CF substrate 22 is provided with a common electrode 28 having substantially the same planar shape as the common electrode 25 and formed so as to at least partially overlap the common electrode 25.

従って第1実施形態によれば、液晶層23に電界を印加した場合、液晶分子がベンド配向(具体的には、ハーフベンド配向)をとるようになるため、VA(Vertical Alignment)モード、及びIPS(In-Plane Switching)/FFS(Fringe Field Switching)モードなどに比べて、液晶表示パネル11の応答速度をより高速化することができる。   Therefore, according to the first embodiment, when an electric field is applied to the liquid crystal layer 23, the liquid crystal molecules take a bend alignment (specifically, a half bend alignment), and therefore, a VA (Vertical Alignment) mode and IPS Compared with (In-Plane Switching) / FFS (Fringe Field Switching) mode, the response speed of the liquid crystal display panel 11 can be further increased.

図10は、本実施形態に係る液晶表示パネル11の応答速度を説明するグラフである。図10のX軸は元階調、Y軸は先階調、Z軸は応答速度(msec)を表している。元階調とは、階調を変化させる前の階調を意味する。先階調とは、階調を変化させた後の階調を意味する。X軸及びY軸の数字は、階調を表しており、ここでは、64階調(0階調〜63階調)を表示する場合の応答速度を示している。0階調が黒(BK)、63階調が白(W)である。   FIG. 10 is a graph for explaining the response speed of the liquid crystal display panel 11 according to the present embodiment. In FIG. 10, the X axis represents the original gradation, the Y axis represents the previous gradation, and the Z axis represents the response speed (msec). The original gradation means the gradation before changing the gradation. The previous gradation means a gradation after changing the gradation. The numbers on the X axis and the Y axis represent gradations, and here, the response speed when displaying 64 gradations (0 gradations to 63 gradations) is shown. The 0 gradation is black (BK) and the 63 gradation is white (W).

図10のグラフの見方は、第1階調(元階調)から第2階調(先階調)へ表示を変化させる場合、X軸(元階調)に記載された第1階調の数字と、Y軸(先階調)に記載された第2階調の数字とが交差する位置の棒グラフの高さで応答速度が分かるようになっている。   The graph shown in FIG. 10 is obtained when the display is changed from the first gradation (original gradation) to the second gradation (destination gradation) in the first gradation described on the X axis (original gradation). The response speed can be understood from the height of the bar graph at the position where the numeral and the numeral of the second gradation described on the Y-axis (first gradation) intersect.

図11は、VAモードの液晶表示パネル(第1比較例)における応答速度を説明するグラフである。図12は、FFSモードの液晶表示パネル(第2比較例)における応答速度を説明するグラフである。図10に示した本実施形態の液晶表示パネル11は、第1比較例(図11)及び第2比較例(図12)と比べて、応答速度が向上しているのが理解できる。   FIG. 11 is a graph for explaining the response speed in the VA mode liquid crystal display panel (first comparative example). FIG. 12 is a graph for explaining the response speed in the FFS mode liquid crystal display panel (second comparative example). It can be understood that the liquid crystal display panel 11 of the present embodiment shown in FIG. 10 has an improved response speed compared to the first comparative example (FIG. 11) and the second comparative example (FIG. 12).

また、CF基板22側の共通電極28上に、従来のTBA(Transverse Bend Alignment)モードで必要とされる、液晶層23に印加される電界を調整するための誘電体膜を形成する必要がない。これにより、DC(direct current)アンバランスに起因して発生していた残像(いわゆる、焼き付き)を抑制できる。   Further, it is not necessary to form a dielectric film for adjusting the electric field applied to the liquid crystal layer 23, which is required in the conventional TBA (Transverse Bend Alignment) mode, on the common electrode 28 on the CF substrate 22 side. . Thereby, an afterimage (so-called burn-in) caused by DC (direct current) imbalance can be suppressed.

また、CF基板22側の共通電極28を、TFT基板21側の共通電極25と平面投影において重なるように配置したことにより、TFT基板21側の画素電極24とCF基板22側の共通電極28との間で斜め電界がより強く生じる。これにより、所望のハーフベンド配向になるように液晶分子を傾けることができるため、透過率を向上させることができる。   Further, by arranging the common electrode 28 on the CF substrate 22 side so as to overlap the common electrode 25 on the TFT substrate 21 side in the planar projection, the pixel electrode 24 on the TFT substrate 21 side and the common electrode 28 on the CF substrate 22 side An oblique electric field is generated more strongly between the two. Thereby, since the liquid crystal molecules can be tilted so as to have a desired half-bend alignment, the transmittance can be improved.

また、TBAモードでは透過率が低いために、セルギャップを通常の4μm程度から小さくすることが困難であった。しかし、本実施形態の構造を採用することで、セルギャップを3μm程度まで小さくすることが可能となり、さらなる応答速度の高速化が可能となる。   In addition, since the transmittance is low in the TBA mode, it is difficult to reduce the cell gap from the usual 4 μm. However, by adopting the structure of this embodiment, the cell gap can be reduced to about 3 μm, and the response speed can be further increased.

また、4μm程度のセルギャップでは、液晶層のリタデーションΔndの関係で、現状の円偏光板(偏光板及び位相差板(λ/4板)から構成される)では視野角が狭くなるため、円偏光板を使用することが困難であった。しかし、本実施形態の液晶表示パネル11では、セルギャップを小さくすることが可能であるため、視野角を劣化させることなく、円偏光板を使用することができる。また、円偏光板を液晶表示パネル11に配置することで、直線偏光板では取り出せなかった偏光板の軸方向に倒れている液晶分子があるエリアの光も取り出すことができ、透過率のさらなる向上が可能となる。さらに、反射表示の光学設計の最適化が可能となるため、半透過型液晶表示パネルにも対応できるようになる。   In addition, when the cell gap is about 4 μm, the viewing angle becomes narrow in the current circularly polarizing plate (consisting of a polarizing plate and a retardation plate (λ / 4 plate)) due to the retardation Δnd of the liquid crystal layer. It was difficult to use a polarizing plate. However, since the cell gap can be reduced in the liquid crystal display panel 11 of the present embodiment, a circularly polarizing plate can be used without deteriorating the viewing angle. Further, by arranging the circularly polarizing plate on the liquid crystal display panel 11, it is possible to take out light in an area where the liquid crystal molecules are tilted in the axial direction of the polarizing plate, which could not be taken out by the linear polarizing plate, and further improve the transmittance. Is possible. Furthermore, since the optical design of the reflective display can be optimized, it can be applied to a transflective liquid crystal display panel.

[第2実施形態]
図13は、本発明の第2実施形態に係るCF基板22のレイアウト図及び断面図である。図13(a)がCF基板22のレイアウト図、図13(b)が図13(a)に示したC−C´線に沿ったCF基板22の断面図である。図13は、3画素分のレイアウトを示している。図13には、ストライプ配列のカラーフィルター27を一例として図示している。
[Second Embodiment]
FIG. 13 is a layout view and a cross-sectional view of the CF substrate 22 according to the second embodiment of the present invention. FIG. 13A is a layout diagram of the CF substrate 22, and FIG. 13B is a cross-sectional view of the CF substrate 22 taken along the line CC ′ shown in FIG. FIG. 13 shows a layout for three pixels. FIG. 13 shows a stripe-arranged color filter 27 as an example.

カラーフィルター27上には、TFT基板21側に形成された共通電極25と平面投影において重なるように形成された電極部分と、TFT基板21側に形成された画素電極24と平面投影において重なるように形成された電極部分とを含む共通電極28が設けられる。具体的には、共通電極28は、画素電極24をX方向両側から挟みかつY方向に延びる直線状の共通電極28−1、28−2と、共通電極28−1、28−2を電気的に接続しかつX方向に延びる直線状の共通電極28−3、28−4と、共通電極28−1及び28−2の間に所定の間隔を空けて配置された共通電極28−5とから構成される基本単位を含み、この基本単位が四方に格子状にかつ画素に対応するように配置されて構成される。共通電極28−1〜28−4は、TFT基板21側に形成された共通電極25と平面投影において重なるように配置される。共通電極28−5は、TFT基板21側に形成された画素電極24と平面投影において重なるように配置される。   On the color filter 27, an electrode portion formed so as to overlap the common electrode 25 formed on the TFT substrate 21 side in the planar projection and a pixel electrode 24 formed on the TFT substrate 21 side so as to overlap in the planar projection. A common electrode 28 including the formed electrode portion is provided. Specifically, the common electrode 28 electrically connects the linear common electrodes 28-1 and 28-2 and the common electrodes 28-1 and 28-2 that sandwich the pixel electrode 24 from both sides in the X direction and extend in the Y direction. And linear common electrodes 28-3 and 28-4 extending in the X direction, and a common electrode 28-5 disposed at a predetermined interval between the common electrodes 28-1 and 28-2. The basic unit is configured, and the basic unit is arranged in a grid pattern on all sides and corresponding to the pixels. The common electrodes 28-1 to 28-4 are arranged so as to overlap with the common electrode 25 formed on the TFT substrate 21 side in the planar projection. The common electrode 28-5 is arranged so as to overlap with the pixel electrode 24 formed on the TFT substrate 21 side in a planar projection.

次に、上記のように構成された液晶表示装置10の動作について説明する。図14(a)は、液晶層23に電界を印加していない状態(オフ状態)での液晶分子の配向状態を説明する図である。共通電圧供給回路14は、共通電極25、28に共通電圧Vcom(例えば0V)を印加し、信号ドライバ13は、画素電極24に共通電圧Vcomを印加する。このオフ状態における液晶表示装置10の表示は、図9(a)の場合と同じである。   Next, the operation of the liquid crystal display device 10 configured as described above will be described. FIG. 14A is a diagram illustrating the alignment state of liquid crystal molecules in a state where no electric field is applied to the liquid crystal layer 23 (off state). The common voltage supply circuit 14 applies a common voltage Vcom (for example, 0 V) to the common electrodes 25 and 28, and the signal driver 13 applies the common voltage Vcom to the pixel electrode 24. The display of the liquid crystal display device 10 in the off state is the same as in the case of FIG.

図14(b)は、液晶層23に電界を印加した状態(オン状態)での液晶分子の配向状態を説明する図である。共通電圧供給回路14は、共通電極25、28に共通電圧Vcom(例えば0V)を印加し、信号ドライバ13は、画素電極24に共通電圧Vcomより高い駆動電圧(例えば5V)を印加する。   FIG. 14B is a diagram for explaining the alignment state of the liquid crystal molecules when an electric field is applied to the liquid crystal layer 23 (ON state). The common voltage supply circuit 14 applies a common voltage Vcom (for example, 0 V) to the common electrodes 25 and 28, and the signal driver 13 applies a drive voltage (for example, 5 V) higher than the common voltage Vcom to the pixel electrode 24.

このオン状態においても、第1実施形態と同様に、液晶層23は、ハーフベンド配向をとる。さらに、画素電極24と共通電極28−5との間には縦方向(垂直方向)の電界が印加されるため、画素電極24と共通電極28−5との間に存在する液晶分子は、垂直配向をとる。これにより、液晶層23全体の配向を安定させることができるため、液晶表示パネル11の表示面が押された際(面押しの際)に発生する表示不良を抑制できる。その他の効果は、第1実施形態と同じである。   Even in this on-state, the liquid crystal layer 23 takes half-bend alignment as in the first embodiment. Further, since an electric field in the vertical direction (vertical direction) is applied between the pixel electrode 24 and the common electrode 28-5, liquid crystal molecules existing between the pixel electrode 24 and the common electrode 28-5 are vertical. Take orientation. Thereby, since the orientation of the liquid crystal layer 23 as a whole can be stabilized, display defects that occur when the display surface of the liquid crystal display panel 11 is pressed (when the surface is pressed) can be suppressed. Other effects are the same as those of the first embodiment.

[第3実施形態]
第3実施形態は、画素17が直線状の複数の画素電極24を備える場合の液晶表示パネル11の構成例である。
[Third Embodiment]
The third embodiment is a configuration example of the liquid crystal display panel 11 when the pixels 17 include a plurality of linear pixel electrodes 24.

図15は、本発明の第3実施形態に係るTFT基板21のレイアウト図である。図16は、液晶層23側から見たCF基板22のレイアウト図である。図17は、図15及び図16に示したC−C´線に沿った液晶表示パネル11の断面図である。なお、図17の断面図では、図3に示した円偏光板30、33と、配向膜26、29との図示を省略している。   FIG. 15 is a layout diagram of the TFT substrate 21 according to the third embodiment of the present invention. FIG. 16 is a layout diagram of the CF substrate 22 as viewed from the liquid crystal layer 23 side. FIG. 17 is a cross-sectional view of the liquid crystal display panel 11 taken along the line CC ′ shown in FIGS. 15 and 16. In the cross-sectional view of FIG. 17, the circularly polarizing plates 30 and 33 and the alignment films 26 and 29 shown in FIG.

図15において、TFT基板21に設けられた画素電極24は、それぞれがY方向に延びる直線状の画素電極24−1、24−2と、画素電極24−1及び24−2を電気的に接続する接続部分24−3とから構成される。接続部分24−3は、コンタクトプラグ48によってドレイン電極44に電気的に接続される。   In FIG. 15, the pixel electrode 24 provided on the TFT substrate 21 is electrically connected to the linear pixel electrodes 24-1 and 24-2 and the pixel electrodes 24-1 and 24-2 each extending in the Y direction. Connecting portion 24-3. The connection portion 24-3 is electrically connected to the drain electrode 44 by the contact plug 48.

TFT基板21に設けられた共通電極25は、画素電極24−1、24−2をX方向両側から所定の間隔を空けて挟むように配置されかつそれぞれがY方向に延びる直線状の共通電極25−1、25−2と、共通電極25−1、25−2を電気的に接続しかつX方向に延びる直線状の共通電極25−3、25−4と、画素電極24−1及び24−2の間に所定の間隔を空けて配置されかつY方向に延びる直線状に形成されかつ共通電極25−4に電気的に接続された共通電極25−5とから構成される基本単位を含み、この基本単位が四方に格子状にかつ画素に対応するように配置されて構成される。すなわち、共通電極25−1及び25−5は、TFT基板21に設けられた画素電極24−1をX方向両側から所定の間隔を空けて挟むように配置され、共通電極25−2及び25−5は、TFT基板21に設けられた画素電極24−2を両側から挟むように配置される。また、共通電極25−1、25−2は、平面投影において、信号線SLを覆うように配置される。   The common electrode 25 provided on the TFT substrate 21 is arranged so as to sandwich the pixel electrodes 24-1 and 24-2 from both sides in the X direction with a predetermined interval, and each linear common electrode 25 extends in the Y direction. -1 and 25-2, the common electrodes 25-1 and 25-2 are electrically connected to each other, and the linear common electrodes 25-3 and 25-4 extending in the X direction and the pixel electrodes 24-1 and 24- Including a basic unit composed of a common electrode 25-5 which is arranged in a straight line extending in the Y direction and is electrically connected to the common electrode 25-4. The basic units are arranged in a grid pattern on all sides and corresponding to the pixels. That is, the common electrodes 25-1 and 25-5 are arranged so as to sandwich the pixel electrode 24-1 provided on the TFT substrate 21 from the both sides in the X direction with a predetermined interval, and the common electrodes 25-2 and 25-. 5 is arranged so as to sandwich the pixel electrode 24-2 provided on the TFT substrate 21 from both sides. Further, the common electrodes 25-1 and 25-2 are arranged so as to cover the signal line SL in the planar projection.

図16において、カラーフィルター27上には、TFT基板21側に形成された共通電極25とほぼ同じ平面形状を有し、平面投影において共通電極25と重なるように配置された共通電極28が設けられる。すなわち、共通電極28は、共通電極28−1〜28−5から構成され、共通電極28−1〜28−5はそれぞれ、平面投影において共通電極25−1〜25−5に重なるように配置される。   In FIG. 16, on the color filter 27, a common electrode 28 having substantially the same planar shape as the common electrode 25 formed on the TFT substrate 21 side and disposed so as to overlap the common electrode 25 in the planar projection is provided. . That is, the common electrode 28 includes common electrodes 28-1 to 28-5, and the common electrodes 28-1 to 28-5 are arranged so as to overlap the common electrodes 25-1 to 25-5 in the planar projection, respectively. The

なお、図15には、反射領域と透過領域とを含む半透過型液晶表示パネル11の構成例を示している。しかし、第1実施形態と同様に、反射領域を含まない透過型液晶表示パネル11に本実施形態を適用することも可能である。透過型液晶表示パネル11は、図15及び図17の反射膜46を除いて構成される。   FIG. 15 shows a configuration example of the transflective liquid crystal display panel 11 including a reflective region and a transmissive region. However, as in the first embodiment, it is also possible to apply this embodiment to the transmissive liquid crystal display panel 11 that does not include a reflective region. The transmissive liquid crystal display panel 11 is configured except for the reflective film 46 of FIGS. 15 and 17.

第3実施形態によれば、共通電極25−1と画素電極24−1との間、画素電極24−1と共通電極25−5との間、共通電極25−5と画素電極24−2との間、画素電極24−2と共通電極25−2との間のそれぞれにおいて、液晶層をハーフベンド配向に設定できる。このように、画素17が直線状の複数の画素電極24を備える場合でも、第1実施形態と同じ動作を実現できる。もちろん、画素17内に3つ以上の直線状の画素電極を配置してもよい。また、第3実施形態に第2実施形態を適用することも可能である。   According to the third embodiment, between the common electrode 25-1 and the pixel electrode 24-1, between the pixel electrode 24-1 and the common electrode 25-5, and between the common electrode 25-5 and the pixel electrode 24-2. In the meantime, the liquid crystal layer can be set to a half-bend alignment in each of the pixel electrode 24-2 and the common electrode 25-2. Thus, even when the pixel 17 includes a plurality of linear pixel electrodes 24, the same operation as in the first embodiment can be realized. Of course, three or more linear pixel electrodes may be arranged in the pixel 17. Moreover, it is also possible to apply 2nd Embodiment to 3rd Embodiment.

[第4実施形態]
第4実施形態は、CF基板22側の共通電極28と画素電極24との距離を、TFT基板21側の共通電極25と画素電極24との距離より小さくする。そして、共通電極28と画素電極24との間の斜め電界を、共通電極25と画素電極24との間の横電界より大きくする。これにより、液晶の配向不良を抑制することで、所望の配向状態を実現するようにしている。
[Fourth Embodiment]
In the fourth embodiment, the distance between the common electrode 28 on the CF substrate 22 side and the pixel electrode 24 is made smaller than the distance between the common electrode 25 on the TFT substrate 21 side and the pixel electrode 24. Then, the oblique electric field between the common electrode 28 and the pixel electrode 24 is made larger than the lateral electric field between the common electrode 25 and the pixel electrode 24. Accordingly, a desired alignment state is realized by suppressing alignment defects of the liquid crystal.

[1.液晶表示パネルの構成]
図18は、本発明の第4実施形態に係る液晶表示パネル11の模式的な断面図である。1画素分のレイアウト図は、第1実施形態で示した図4(半透過型)と同じである。図19は、図4に示したA−A´線に沿った液晶表示パネル11の断面図である。図20は、図4に示したB−B´線に沿った液晶表示パネル11の断面図である。なお、図19及び図20の断面図では、図18に示した円偏光板30、33と、配向膜26、29との図示を省略している。
[1. Configuration of LCD panel]
FIG. 18 is a schematic cross-sectional view of a liquid crystal display panel 11 according to the fourth embodiment of the present invention. The layout diagram for one pixel is the same as FIG. 4 (semi-transmissive type) shown in the first embodiment. FIG. 19 is a cross-sectional view of the liquid crystal display panel 11 taken along line AA ′ shown in FIG. FIG. 20 is a cross-sectional view of the liquid crystal display panel 11 taken along the line BB ′ shown in FIG. 19 and 20, the circularly polarizing plates 30 and 33 and the alignment films 26 and 29 shown in FIG. 18 are not shown.

TFT基板21に形成された絶縁膜47上には、Y方向に延びる画素電極24と、画素電極24を囲む共通電極25(共通電極25−1〜25−4)とが設けられる。なお、前述したように、共通電極25は、画素電極24をX方向から挟むように構成してもよい。共通電極25−1、25−2は、平面投影(平面視)において、信号線SLを覆うように形成される。これにより、信号線SLに起因する不要な電界が液晶層23に印加されるのを防ぐことができる。   On the insulating film 47 formed on the TFT substrate 21, a pixel electrode 24 extending in the Y direction and a common electrode 25 (common electrodes 25-1 to 25-4) surrounding the pixel electrode 24 are provided. As described above, the common electrode 25 may be configured to sandwich the pixel electrode 24 from the X direction. The common electrodes 25-1 and 25-2 are formed so as to cover the signal line SL in planar projection (plan view). Thereby, it is possible to prevent an unnecessary electric field due to the signal line SL from being applied to the liquid crystal layer 23.

CF基板22に形成されたカラーフィルター27及びブラックマトリクスBM上には、共通電極28(共通電極28−1〜28−4)が設けられる。図19に示されるように、共通電極28−1、28−2は、平面投影において、共通電極25−1、25−2に重なるように配置される。また、共通電極28−1、28−1の幅は、共通電極25−1、25−2の幅より大きく設定される。同様に、図20に示されるように、共通電極28−3、28−4は、平面投影において、共通電極25−3、25−4に重なるように配置される。また、共通電極28−3、28−4の幅は、共通電極25−3、25−4の幅より大きく設定される。   On the color filter 27 and the black matrix BM formed on the CF substrate 22, common electrodes 28 (common electrodes 28-1 to 28-4) are provided. As shown in FIG. 19, the common electrodes 28-1 and 28-2 are arranged so as to overlap the common electrodes 25-1 and 25-2 in the planar projection. The widths of the common electrodes 28-1 and 28-1 are set larger than the widths of the common electrodes 25-1 and 25-2. Similarly, as shown in FIG. 20, the common electrodes 28-3 and 28-4 are arranged so as to overlap the common electrodes 25-3 and 25-4 in the planar projection. The widths of the common electrodes 28-3 and 28-4 are set larger than the widths of the common electrodes 25-3 and 25-4.

図21は、共通電極25、28及び画素電極24の距離に関するパラメータを説明する図である。“a”は、画素電極24と共通電極25−2との距離である。“b”は、共通電極25−2と共通電極28−2との距離であり、すなわち、セルギャップに対応する。“c”は、画素電極24と共通電極28−2との距離であり、具体的には、画素電極24の共通電極28−2側の端と、共通電極28−2の画素電極24側の端との間の斜め方向の距離である。“d”は、共通電極28−2の画素電極24側の端と、共通電極25−2の画素電極24側の端の間の水平距離である。   FIG. 21 is a diagram illustrating parameters regarding the distance between the common electrodes 25 and 28 and the pixel electrode 24. “A” is the distance between the pixel electrode 24 and the common electrode 25-2. “B” is the distance between the common electrode 25-2 and the common electrode 28-2, that is, corresponds to the cell gap. “C” is the distance between the pixel electrode 24 and the common electrode 28-2, specifically, the end of the pixel electrode 24 on the common electrode 28-2 side and the common electrode 28-2 on the pixel electrode 24 side. The diagonal distance between the edges. “D” is a horizontal distance between the end of the common electrode 28-2 on the pixel electrode 24 side and the end of the common electrode 25-2 on the pixel electrode 24 side.

距離cは、以下の式(1)で表される。
The distance c is represented by the following formula (1).

ここで、距離cは、距離aより小さく設定される。c<aであるため、距離dは、以下の式(2)で表される。
Here, the distance c is set smaller than the distance a. Since c <a, the distance d is expressed by the following formula (2).

なお、0<d<aである。   Note that 0 <d <a.

また、共通電極25−1、25−3、25−4、28−1、28−3、28−4の条件についても、図21で示した共通電極25−2、28−2と同じ条件を満たすように設定される。   Also, the conditions for the common electrodes 25-1, 25-3, 25-4, 28-1, 28-3, 28-4 are the same as those for the common electrodes 25-2, 28-2 shown in FIG. Set to meet.

[2.動作]
まず、比較例に係る液晶表示パネルの動作について説明する。図22は、比較例に係る液晶分子の配向状態を説明する図である。図22は、液晶層に電界を印加した状態(オン状態)を表している。オン状態では、共通電極25、28には、共通電圧Vcom(例えば0V)が印加され、画素電極24には、共通電圧Vcomより高い駆動電圧(例えば5V)が印加される。液晶層に電界が印加されていない状態(オフ状態)は、図9(a)と同じである。
[2. Operation]
First, the operation of the liquid crystal display panel according to the comparative example will be described. FIG. 22 is a diagram for explaining the alignment state of the liquid crystal molecules according to the comparative example. FIG. 22 shows a state where an electric field is applied to the liquid crystal layer (ON state). In the ON state, a common voltage Vcom (for example, 0V) is applied to the common electrodes 25 and 28, and a drive voltage (for example, 5V) higher than the common voltage Vcom is applied to the pixel electrode 24. The state in which an electric field is not applied to the liquid crystal layer (off state) is the same as FIG.

比較例では、CF基板22側の共通電極28の幅がTFT基板21側の共通電極25の幅より小さくなっている。また、上下基板の合わせズレ等でCF基板22側の共通電極28がTFT基板21側の共通電極25より内側(画素電極24から離れる方向)に配置された場合、少なくとも図22のうち共通電極28−1、28−2の一方と同じ位置関係が生じる。この場合、共通電極28と画素電極24との距離は、共通電極25と画素電極24との距離より大きくなるので、共通電極28と画素電極24との間に印加される斜め電界は、共通電極25と画素電極24との間に印加される横電界より小さくなる。   In the comparative example, the width of the common electrode 28 on the CF substrate 22 side is smaller than the width of the common electrode 25 on the TFT substrate 21 side. Further, when the common electrode 28 on the CF substrate 22 side is disposed inside the common electrode 25 on the TFT substrate 21 side (in the direction away from the pixel electrode 24) due to misalignment of the upper and lower substrates, at least the common electrode 28 in FIG. -1 and 28-2, the same positional relationship is generated. In this case, since the distance between the common electrode 28 and the pixel electrode 24 is larger than the distance between the common electrode 25 and the pixel electrode 24, the oblique electric field applied between the common electrode 28 and the pixel electrode 24 is The horizontal electric field applied between the pixel electrode 24 and the pixel electrode 24 becomes smaller.

斜め電界が横電界より小さくなると、図22に示した液晶層23内のドメインにおいて、液晶の配向不良が発生してしまう。例えば、ドメインの両側の液晶分子がドメイン側に傾くため、ドメイン内の液晶分子は、共通電極28側に傾くことができず、立ち上がった状態となり、さらに、ドメイン内の液晶分子が表示中に動いてしまう可能性がある。このドメインでは、液晶の配向不良が発生し、所望の配向(ハーフベンド配向)を実現することができない。結果として、このドメインは、表示ムラや残像などを発生させる。   If the oblique electric field is smaller than the lateral electric field, liquid crystal alignment defects occur in the domains in the liquid crystal layer 23 shown in FIG. For example, since the liquid crystal molecules on both sides of the domain are tilted toward the domain side, the liquid crystal molecules in the domain cannot be tilted toward the common electrode 28 and are in a standing state, and further, the liquid crystal molecules in the domain move during display. There is a possibility that. In this domain, alignment failure of the liquid crystal occurs, and a desired alignment (half-bend alignment) cannot be realized. As a result, this domain causes display unevenness and afterimage.

図23は、本実施形態に係る液晶分子の配向状態を説明する図である。図23は、液晶層に電界を印加した状態(オン状態)を表している。オン状態において、共通電圧供給回路14は、共通電極25、28に共通電圧Vcom(例えば0V)を印加し、信号ドライバ13は、画素電極24に共通電圧Vcomより高い駆動電圧(例えば5V)を印加する。   FIG. 23 is a diagram for explaining the alignment state of the liquid crystal molecules according to the present embodiment. FIG. 23 shows a state in which an electric field is applied to the liquid crystal layer (ON state). In the ON state, the common voltage supply circuit 14 applies a common voltage Vcom (for example, 0 V) to the common electrodes 25 and 28, and the signal driver 13 applies a drive voltage (for example, 5 V) higher than the common voltage Vcom to the pixel electrode 24. To do.

本実施形態では、共通電極28と画素電極24との距離は、共通電極25と画素電極24との距離より小さくなる。一例として、共通電極28と画素電極24との距離aが4μm程度、共通電極25と共通電極28との距離(セルギャップ)bが3μm程度とすると、共通電極28の端と共通電極25の端との片側の距離dを1.35μm以上大きくする。この場合、共通電極28と画素電極24との間に印加される斜め電界は、共通電極25と画素電極24との間に印加される横電界より相対的に大きくなる。   In the present embodiment, the distance between the common electrode 28 and the pixel electrode 24 is smaller than the distance between the common electrode 25 and the pixel electrode 24. As an example, when the distance a between the common electrode 28 and the pixel electrode 24 is about 4 μm and the distance (cell gap) b between the common electrode 25 and the common electrode 28 is about 3 μm, the end of the common electrode 28 and the end of the common electrode 25 And the distance d on one side is increased by 1.35 μm or more. In this case, the oblique electric field applied between the common electrode 28 and the pixel electrode 24 is relatively larger than the lateral electric field applied between the common electrode 25 and the pixel electrode 24.

これにより、液晶の配向をより安定させることができる。具体的には、共通電極25−1と画素電極24との間の液晶は、同じ方向に傾くようにしてハーフベンド配向をとる。同様に、共通電極25−2と画素電極24との間の液晶は、同じ方向に傾くようにしてハーフベンド配向をとる。本実施形態では、比較例で生じていた液晶配向不良のドメインが生成されるのを抑制することができる。   Thereby, the orientation of the liquid crystal can be further stabilized. Specifically, the liquid crystal between the common electrode 25-1 and the pixel electrode 24 has a half bend alignment so as to be inclined in the same direction. Similarly, the liquid crystal between the common electrode 25-2 and the pixel electrode 24 has a half bend alignment so as to be inclined in the same direction. In the present embodiment, it is possible to suppress the generation of a liquid crystal alignment defect domain that has occurred in the comparative example.

[3.効果]
以上詳述したように第4実施形態では、液晶層23は、p型(ポジ型)液晶材料からなり、また、電界が印加されていない状態で液晶分子をほぼ垂直に配向させる。また、TFT基板21に、直線状の画素電極24と、この画素電極24を所定の間隔を空けて囲む又は挟むように形成された共通電極25を設ける。また、CF基板22に、共通電極25とほぼ同じ平面形状を有し、共通電極25と少なくとも一部が重なるように形成された共通電極28を設ける。そして、共通電極28と画素電極24との距離は、共通電極25と画素電極24との距離より小さく設定される。
[3. effect]
As described above in detail, in the fourth embodiment, the liquid crystal layer 23 is made of a p-type (positive) liquid crystal material, and aligns liquid crystal molecules substantially vertically in the state where an electric field is not applied. Further, the TFT substrate 21 is provided with a linear pixel electrode 24 and a common electrode 25 formed so as to surround or sandwich the pixel electrode 24 with a predetermined interval. In addition, the CF substrate 22 is provided with a common electrode 28 having substantially the same planar shape as the common electrode 25 and formed so as to at least partially overlap the common electrode 25. The distance between the common electrode 28 and the pixel electrode 24 is set smaller than the distance between the common electrode 25 and the pixel electrode 24.

従って第4実施形態によれば、液晶層23に電界を印加した場合、液晶分子がハーフベンド配向をとるようになるため、VAモード、及びIPS/FFSモードなどに比べて、液晶表示パネル11の応答速度をより高速化することができる。   Therefore, according to the fourth embodiment, when an electric field is applied to the liquid crystal layer 23, the liquid crystal molecules take a half-bend alignment. Therefore, compared with the VA mode, the IPS / FFS mode, and the like, The response speed can be further increased.

また、ハーフベンド配向時に、共通電極28によって液晶層に印加される斜め電界を、共通電極25によって液晶層に印加される横電界より大きくすることができる。これにより、液晶の配向をより安定させることができるため、液晶配向不良のドメインが生成されるのを抑制することができる。この結果、表示特性をより向上させることができる。   In addition, the oblique electric field applied to the liquid crystal layer by the common electrode 28 during the half bend alignment can be made larger than the lateral electric field applied to the liquid crystal layer by the common electrode 25. Thereby, since the orientation of the liquid crystal can be further stabilized, it is possible to suppress the generation of domains with poor liquid crystal orientation. As a result, the display characteristics can be further improved.

なお、第4実施形態に第2及び第3実施形態を適用することも可能である。   Note that the second and third embodiments may be applied to the fourth embodiment.

[第5実施形態]
第5実施形態は、共通電極25を画素電極24より下層に配置することで、共通電極28と画素電極24との距離を、共通電極25と画素電極24との距離より小さくするようにしている。
[Fifth Embodiment]
In the fifth embodiment, the common electrode 25 is disposed below the pixel electrode 24 so that the distance between the common electrode 28 and the pixel electrode 24 is smaller than the distance between the common electrode 25 and the pixel electrode 24. .

1画素分のレイアウト図は、第1実施形態で示した図5(反射膜なし)と同じである。図24は、図5に示したA−A´線に沿った液晶表示パネル11の断面図である。図25は、図5に示したB−B´線に沿った液晶表示パネル11の断面図である。なお、図24及び図25の断面図では、円偏光板30、33と、配向膜26、29との図示を省略している。また、反射膜46を設ける場合(すなわち、半透過型の場合)には、共通電極25と別のレベル層に反射膜46を配置する。   The layout diagram for one pixel is the same as FIG. 5 (without the reflection film) shown in the first embodiment. 24 is a cross-sectional view of the liquid crystal display panel 11 taken along line AA ′ shown in FIG. FIG. 25 is a cross-sectional view of the liquid crystal display panel 11 taken along line BB ′ shown in FIG. 24 and 25, illustration of the circularly polarizing plates 30 and 33 and the alignment films 26 and 29 is omitted. When the reflective film 46 is provided (that is, in the case of a semi-transmissive type), the reflective film 46 is disposed in a level layer different from the common electrode 25.

共通電極25(共通電極25−1〜25−4)は、画素電極24より下層に配置される。図24及び図25の構成例では、共通電極25は、絶縁膜45上に配置される。共通電極25−1、25−2は、平面投影において、信号線SLを覆うように形成される。   The common electrode 25 (common electrodes 25-1 to 25-4) is disposed below the pixel electrode 24. In the configuration example of FIGS. 24 and 25, the common electrode 25 is disposed on the insulating film 45. The common electrodes 25-1 and 25-2 are formed so as to cover the signal line SL in the planar projection.

画素電極24と共通電極28−2との距離cは、画素電極24と共通電極25−2との距離aより小さく設定される。同様に、共通電極25−1、25−3、25−4、28−1、28−3、28−4の条件についても、共通電極25−2、28−2と同じ条件を満たすように設定される。   The distance c between the pixel electrode 24 and the common electrode 28-2 is set to be smaller than the distance a between the pixel electrode 24 and the common electrode 25-2. Similarly, the conditions of the common electrodes 25-1, 25-3, 25-4, 28-1, 28-3, 28-4 are also set so as to satisfy the same conditions as the common electrodes 25-2, 28-2. Is done.

c<aの条件の設定方法は、(1)共通電極28の幅を共通電極25の幅より大きくすること、及び(2)共通電極25の深さ、すなわち画素電極24の底面から共通電極25の上面までの垂直距離を大きくすることで実現できる。或いは、共通電極25及び共通電極28の幅を所定値とした上で、共通電極25の深さを主として調整することで、c<aの条件を満たすようにしてもよい。   The conditions for setting c <a are as follows: (1) the width of the common electrode 28 is made larger than the width of the common electrode 25; and (2) the depth of the common electrode 25, that is, the bottom surface of the pixel electrode 24. This can be achieved by increasing the vertical distance to the top surface of the plate. Alternatively, the condition of c <a may be satisfied by mainly adjusting the depth of the common electrode 25 after setting the widths of the common electrode 25 and the common electrode 28 to predetermined values.

以上詳述したように第5実施形態によれば、ハーフベンド配向時に、共通電極28によって液晶層に印加される斜め電界を、共通電極25によって液晶層に印加される横電界より大きくすることができる。これにより、第4実施形態と同じ効果を得ることができる。また、c<aの条件の設定するための手法に、共通電極25のレベルを加えることで、斜め電界を横電界より大きくするための設計が容易となる。   As described above in detail, according to the fifth embodiment, the oblique electric field applied to the liquid crystal layer by the common electrode 28 can be made larger than the lateral electric field applied to the liquid crystal layer by the common electrode 25 during half-bend alignment. it can. Thereby, the same effect as the fourth embodiment can be obtained. Further, by adding the level of the common electrode 25 to the method for setting the condition of c <a, the design for making the oblique electric field larger than the lateral electric field becomes easy.

なお、上記各実施形態は、反射領域と透過領域とを含む半透過型液晶表示パネルとして実現してもよいし、反射領域(反射膜46)を含まない透過型液晶表示パネルとして実現してもよい。   Each of the above embodiments may be realized as a transflective liquid crystal display panel including a reflective region and a transmissive region, or may be realized as a transmissive liquid crystal display panel including no reflective region (reflective film 46). Good.

また、上記各実施形態では、円偏光板30、33を備えた液晶表示パネル11の構成例について示している。しかし、これに限定されず、位相差板31、34を省いて偏光子を構成してもよい。   Moreover, in each said embodiment, the structural example of the liquid crystal display panel 11 provided with the circularly-polarizing plates 30 and 33 is shown. However, the present invention is not limited to this, and the polarizer may be configured by omitting the phase difference plates 31 and 34.

本発明は、上記実施形態に限定されるものではなく、その要旨を逸脱しない範囲内で、構成要素を変形して具体化することが可能である。さらに、上記実施形態には種々の段階の発明が含まれており、1つの実施形態に開示される複数の構成要素の適宜な組み合わせ、若しくは異なる実施形態に開示される構成要素の適宜な組み合わせにより種々の発明を構成することができる。例えば、実施形態に開示される全構成要素から幾つかの構成要素が削除されても、発明が解決しようとする課題が解決でき、発明の効果が得られる場合には、これらの構成要素が削除された実施形態が発明として抽出されうる。   The present invention is not limited to the above embodiment, and can be embodied by modifying the constituent elements without departing from the scope of the invention. Further, the above embodiments include inventions at various stages, and are obtained by appropriately combining a plurality of constituent elements disclosed in one embodiment or by appropriately combining constituent elements disclosed in different embodiments. Various inventions can be configured. For example, even if some constituent elements are deleted from all the constituent elements disclosed in the embodiments, the problems to be solved by the invention can be solved and the effects of the invention can be obtained. Embodiments made can be extracted as inventions.

10…液晶表示装置、11…液晶表示パネル、12…走査ドライバ、13…信号ドライバ、14…共通電圧供給回路、15…電圧発生回路、16…制御回路、17…画素、18…TFT、18…スイッチング素子、20…バックライト、21…TFT基板、22…CF基板、23…液晶層、24…画素電極、25…共通電極、26,29…配向膜、27…カラーフィルター、28…共通電極、30,33…円偏光板、31,34…位相差板、32,35…偏光板、40…蓄積容量線、41,45,47…絶縁膜、42…半導体層、43…ソース電極、44…ドレイン電極、46…反射膜、48…コンタクトプラグ。   DESCRIPTION OF SYMBOLS 10 ... Liquid crystal display device, 11 ... Liquid crystal display panel, 12 ... Scan driver, 13 ... Signal driver, 14 ... Common voltage supply circuit, 15 ... Voltage generation circuit, 16 ... Control circuit, 17 ... Pixel, 18 ... TFT, 18 ... Switching element, 20 ... Back light, 21 ... TFT substrate, 22 ... CF substrate, 23 ... Liquid crystal layer, 24 ... Pixel electrode, 25 ... Common electrode, 26, 29 ... Alignment film, 27 ... Color filter, 28 ... Common electrode, 30, 33 ... Circularly polarizing plate, 31, 34 ... Retardation plate, 32, 35 ... Polarizing plate, 40 ... Storage capacitor line, 41, 45, 47 ... Insulating film, 42 ... Semiconductor layer, 43 ... Source electrode, 44 ... Drain electrode, 46 ... reflective film, 48 ... contact plug.

Claims (10)

対向配置された第1及び第2基板と、
前記第1及び第2基板間に挟持され、p型の液晶材料からなり、電界を印加しない状態で垂直配向をとる液晶層と、
前記第1基板に設けられ、第1方向に延びる画素電極と、
前記第1基板に設けられ、それぞれが前記第1方向に延びる第1及び第2電極部分を含み、前記第1及び第2電極部分は、前記第1方向に直交する第2方向における前記画素電極の両側に間隔を空けて配置される、第1共通電極と、
前記第2基板に設けられ、それぞれが前記第1方向に延びる第3乃至第5電極部分を含む第2共通電極と、
を具備し、
前記第3及び第4電極部分はそれぞれ、平面投影において前記第1及び第2電極部分と少なくとも一部が重なり、
前記第5電極部分は、平面投影において前記画素電極と少なくとも一部が重なることを特徴とする液晶表示装置。
First and second substrates disposed opposite to each other;
A liquid crystal layer sandwiched between the first and second substrates, made of a p-type liquid crystal material, and having a vertical alignment without applying an electric field;
A pixel electrode provided on the first substrate and extending in a first direction ;
The pixel electrode is provided on the first substrate and includes first and second electrode portions each extending in the first direction, wherein the first and second electrode portions are in the second direction orthogonal to the first direction. A first common electrode , spaced apart on both sides of the
A second common electrode provided on the second substrate and including third to fifth electrode portions each extending in the first direction ;
Equipped with,
Each of the third and fourth electrode portions at least partially overlaps the first and second electrode portions in a planar projection;
The liquid crystal display device according to claim 5, wherein the fifth electrode portion at least partially overlaps the pixel electrode in planar projection .
前記第3電極部分と前記画素電極との距離は、前記第1電極部分と前記画素電極との距離より小さく、  The distance between the third electrode portion and the pixel electrode is smaller than the distance between the first electrode portion and the pixel electrode,
前記第4電極部分と前記画素電極との距離は、前記第2電極部分と前記画素電極との距離より小さいことを特徴とする請求項1に記載の液晶表示装置。  The liquid crystal display device according to claim 1, wherein a distance between the fourth electrode portion and the pixel electrode is smaller than a distance between the second electrode portion and the pixel electrode.
対向配置された第1及び第2基板と、  First and second substrates disposed opposite to each other;
前記第1及び第2基板間に挟持され、p型の液晶材料からなり、電界を印加しない状態で垂直配向をとる液晶層と、  A liquid crystal layer sandwiched between the first and second substrates, made of a p-type liquid crystal material, and having a vertical alignment without applying an electric field;
前記第1基板に設けられ、第1方向に延びる画素電極と、  A pixel electrode provided on the first substrate and extending in a first direction;
前記第1基板に設けられ、それぞれが前記第1方向に延びる第1及び第2電極部分を含み、前記第1及び第2電極部分は、前記第1方向に直交する第2方向における前記画素電極の両側に間隔を空けて配置される、第1共通電極と、  The pixel electrode is provided on the first substrate and includes first and second electrode portions each extending in the first direction, wherein the first and second electrode portions are in the second direction orthogonal to the first direction. A first common electrode, spaced apart on both sides of the
前記第2基板に設けられ、それぞれが前記第1方向に延びる第3及び第4電極部分を含み、前記第3及び第4電極部分はそれぞれ、平面投影において前記第1及び第2電極部分と少なくとも一部が重なる、第2共通電極と、  The third and fourth electrode portions are provided on the second substrate and each extend in the first direction, and each of the third and fourth electrode portions is at least one of the first and second electrode portions in a planar projection. A second common electrode partially overlapping,
を具備し、  Comprising
前記第3電極部分と前記画素電極との距離は、前記第1電極部分と前記画素電極との距離より小さく、  The distance between the third electrode portion and the pixel electrode is smaller than the distance between the first electrode portion and the pixel electrode,
前記第4電極部分と前記画素電極との距離は、前記第2電極部分と前記画素電極との距離より小さいことを特徴とする液晶表示装置。  A distance between the fourth electrode portion and the pixel electrode is smaller than a distance between the second electrode portion and the pixel electrode.
前記第1共通電極と前記第2共通電極とに同じ電圧を印加する駆動回路をさらに具備することを特徴とする請求項1乃至3のいずれかに記載の液晶表示装置。 4. The liquid crystal display device according to claim 1 , further comprising a driving circuit that applies the same voltage to the first common electrode and the second common electrode. 5. 前記第3電極部分の幅は、前記第1電極部分の幅より大きく、
前記第4電極部分の幅は、前記第2電極部分の幅より大きいことを特徴とする請求項1乃至4のいずれかに記載の液晶表示装置。
The width of the third electrode portion is larger than the width of the first electrode portion,
5. The liquid crystal display device according to claim 1 , wherein a width of the fourth electrode portion is larger than a width of the second electrode portion .
前記第3電極部分の端は、平面投影において、前記第1電極部分の端より前記画素電極側に配置され、
前記第4電極部分の端は、平面投影において、前記第2電極部分の端より前記画素電極側に配置されることを特徴とする請求項1乃至5のいずれかに記載の液晶表示装置。
The end of the third electrode portion is disposed on the pixel electrode side from the end of the first electrode portion in planar projection,
6. The liquid crystal display device according to claim 1 , wherein an end of the fourth electrode portion is disposed closer to the pixel electrode than an end of the second electrode portion in a planar projection .
前記第1共通電極は、前記画素電極より下のレベル層に配置されることを特徴とする請求項1乃至6のいずれかに記載の液晶表示装置。 The liquid crystal display device according to claim 1, wherein the first common electrode is disposed in a level layer below the pixel electrode. 前記画素電極に駆動電圧を供給する信号線をさらに具備し、
前記第1共通電極は、前記信号線を覆うように配置されることを特徴とする請求項1乃至7のいずれかに記載の液晶表示装置。
A signal line for supplying a driving voltage to the pixel electrode;
The liquid crystal display device according to claim 1, wherein the first common electrode is disposed so as to cover the signal line.
前記第1及び第2基板を挟むように配置された第1及び第2円偏光板をさらに具備することを特徴とする請求項1乃至8のいずれかに記載の液晶表示装置。   9. The liquid crystal display device according to claim 1, further comprising first and second circularly polarizing plates arranged so as to sandwich the first and second substrates. 前記第1基板に設けられ、入射光を反射する反射膜をさらに具備することを特徴とする請求項1乃至9のいずれかに記載の液晶表示装置。   The liquid crystal display device according to claim 1, further comprising a reflective film that is provided on the first substrate and reflects incident light.
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