JP6341551B2 - Vacuum channel transistor and manufacturing method thereof - Google Patents

Description

  The present invention relates to a vacuum channel transistor, which is a semiconductor device using a gallium nitride-aluminum nitride mixed crystal semiconductor, and a method for manufacturing the same, and more particularly, using a nitride-based semiconductor having a low electron affinity to reduce power consumption and voltage. The present invention relates to a vacuum channel transistor that can be driven and can operate in a frequency range of 1 THz to 10 THz, and a manufacturing method thereof.

  Currently, the frequency of electromagnetic waves is increasing, and terahertz waves close to the optical frequency range are expected to have many applications such as next-generation high-speed wireless communications, monitoring imaging, and medical applications such as gene / protein functional analysis. Yes. In general, an electromagnetic wave having a frequency of 100 GHz to 10 THz may be referred to as a terahertz wave. Here, the terahertz wave is an electromagnetic wave having a frequency of 1 THz to 10 THz.

  Toward the practical application of devices in the frequency range of 1 THz to 10 THz, electronic research and development has been promoted on the low frequency side, and photon engineering (photonics) research and development has been promoted on the high frequency side. It is being pushed forward. In other words, the electronic approach has been developed with the aim of speeding up electronic devices so that their operating frequency exceeds 1 THz. On the other hand, in the photonics approach, attempts have been made to lengthen the wavelength of light generated in a semiconductor laser or quantum cascade laser and reduce the frequency of the generated electromagnetic wave to 10 THz or less.

  However, there is a limit to speeding up electronic devices in an electronic approach, and electronic devices that can practically generate electromagnetic waves exceeding 1 THz have not been realized. Even in the photonics approach, there is a limit to lowering the frequency of an optical device, and an optical device that can practically generate an electromagnetic wave of 10 THz or less has not been realized. Regarding optical devices, the optical transition energy level difference corresponding to photons of 1 THz to 10 THz is a region close to room temperature thermal energy and is disturbed by room temperature thermal energy, so that the optical device operates at room temperature. There is a problem that it becomes difficult.

  In this way, although it is in the terahertz wave region where many applications are expected, there has not yet been realized a device that practically generates electromagnetic waves in this region in both the electronic approach and the photonics approach. . The electromagnetic wave in the frequency range of 1 THz to 10 THz is left as a blank area where generation of electromagnetic waves and signal processing cannot be performed substantially.

  In order to overcome the problems in the terahertz wave region as described above, a gate insulating type vacuum channel transistor as shown in the following Non-Patent Document 1 has been proposed. Non-Patent Document 1 describes a field effect transistor having a structure in which electrons as carriers travel in a channel in a vacuum space. In a normal field effect transistor in which a channel is provided in a semiconductor, the upper limit of the operating speed depends on the electron saturation speed determined by the semiconductor material. However, there is no saturation speed in the speed of electrons traveling in vacuum, and it is theoretically possible to accelerate the electrons to near the speed of light.

  Therefore, it can be expected that electromagnetic waves in the terahertz wave region can be generated by the vacuum channel transistor. However, in the vacuum channel transistor according to Non-Patent Document 1, the actual cutoff frequency is only 0.46 THz, and the wall of 1 THz cannot be exceeded. This may be due to the low efficiency of emitting electrons from the source. In the vacuum channel transistor of Non-Patent Document 1, although the tip of the source electrode has a sharp shape and the distance between the source and the drain is very small, the efficiency of electron emission is improved to some extent, but still sufficient efficiency can be obtained. I can't say that.

  When the minimum voltage at which a current starts to flow when a voltage is applied between the source and drain is called a threshold voltage, the vacuum channel transistor of Non-Patent Document 1 requires a threshold voltage of about 10 V. The value of is relatively large. This indicates that the efficiency of electron emission at the source is not yet sufficient. Non-Patent Document 1 is a device based on silicon (silicon), and both source and drain electrodes are also made of silicon.

  Since silicon has a high electron affinity, energy corresponding to a large electron affinity must be given to the electrons in order to field-emit electrons at the silicon electrode. As a result, the threshold voltage increases, the electron emission efficiency decreases, and the power consumption increases. It is also necessary to generate a high electric field concentration by making the electrode shape sharp by fine processing.

  On the other hand, there has been proposed an electronic device that attempts to improve electron emission efficiency by using an electrode of a gallium nitride-aluminum nitride mixed crystal semiconductor. Let x be the ratio of aluminum nitride in the gallium nitride-aluminum nitride mixed crystal semiconductor. Here, the ratio x is the ratio of the number of aluminum nitride molecules to the whole, and 0 ≦ x ≦ 1. Note that the mixed crystal semiconductor in the case of x = 0, 1 is actually a pure compound, but in this specification, for convenience, the mixed crystal semiconductor is also described as a mixed crystal semiconductor.

That is, this mixed crystal semiconductor can be expressed as Al _x Ga _1-x N. When the ratio x is 0, the mixed crystal semiconductor is gallium nitride and has an electron affinity of about 3.3 eV, which is a positive electron affinity. As the aluminum nitride ratio x increases, the electron affinity decreases. When the ratio x is about 0.65, the electron affinity of the mixed crystal semiconductor is almost zero. In addition, in aluminum nitride where the ratio x is 1, the electron affinity is negative.

  An electronic device using such a gallium nitride-aluminum nitride mixed crystal semiconductor is disclosed in Patent Document 1 below. In Patent Document 1, a gallium nitride-aluminum nitride mixed crystal semiconductor is used as a surface layer of an electrode, and a substance having an electron affinity of 0 or negative is used as an electrode material to improve the efficiency of electron emission. An electronic device is described.

JP 2002-57322 A

Jin-Woo Han, Jae Sub Oh, and M. Meyyappan, “Vacuum nanoelectronics: Back to the future?-Gate insulated nanoscale vacuum channel transistor”, Applied Physics Letters, vol. 100, pp. 2012

  As described above, the realization of an electronic device capable of generating electromagnetic waves in the terahertz wave region and performing signal processing, which is expected to be applied in many ways, is desired. Although it was expected that a terahertz wave electromagnetic wave could be generated by a vacuum channel transistor as shown in Non-Patent Document 1, the vacuum channel transistor according to Non-Patent Document 1 still exceeds the 1 THz wall. Not done.

  In an electronic device using a silicon electrode as in Non-Patent Document 1, since the electron affinity of silicon is large, the threshold voltage for electron emission must be increased. As a result, the threshold voltage of the electronic device increases and the efficiency of electron emission also decreases. This is a major technical obstacle for realizing a vacuum channel transistor operable in the terahertz wave region.

  On the other hand, there has been proposed an electronic device that attempts to improve electron emission efficiency by using an electrode of a gallium nitride-aluminum nitride mixed crystal semiconductor. However, in order to realize an electronic device that can operate in the terahertz wave region, it is desirable to further improve the efficiency of electron emission. It is desired to further reduce the threshold voltage for electron emission.

  Accordingly, the present invention relates to a semiconductor device and a vacuum channel transistor that use a gallium nitride-aluminum nitride mixed crystal semiconductor and improve the electron emission efficiency and reduce the threshold voltage for electron emission. An object is to provide a transistor. Another object of the present invention is to provide a method for manufacturing such a vacuum channel transistor.

In order to achieve the above object, a semiconductor device of the present invention is provided with an electrode made of a wurtzite structure crystal of a gallium nitride-aluminum nitride mixed crystal semiconductor in which aluminum nitride has a total number ratio of 0.65 or more. And the electrode is arranged so that an angle formed between the main electron emission direction and the c-axis direction of the crystal structure is 30 degrees or less.

  In the above semiconductor device, it is preferable that the electrodes are arranged so that the main electron emission direction is the c-axis direction of the crystal structure.

The vacuum channel transistor of the present invention includes a conductor substrate that forms a gate electrode, an insulating layer made of an insulator formed on the conductor substrate, a source electrode formed on the insulating layer, and the insulating And a drain electrode provided on the layer so as to face the source electrode. The source electrode is made of a wurtzite structure crystal of a gallium nitride-aluminum nitride mixed crystal semiconductor in which aluminum nitride has a total number ratio of 0.65 or more, and the main emission direction of electrons. And the c-axis direction of the crystal structure are arranged to be 30 degrees or less.

  In the above semiconductor element, the source electrode is preferably arranged so that the main electron emission direction is the c-axis direction of the crystal structure.

  In the vacuum channel transistor, the conductor substrate is preferably made of n-type silicon, and the insulating layer is preferably a silicon dioxide layer formed on the surface of the n-type silicon substrate.

  In the above vacuum channel transistor, the source electrode is preferably connected to a metal electrode for energizing the source electrode.

  In the above vacuum channel transistor, a gallium nitride-aluminum nitride mixed crystal semiconductor is formed between the source electrode and the metal electrode, and the proportion of aluminum nitride increases from the metal electrode side toward the source electrode side. A bonding layer can be formed.

  In the above vacuum channel transistor, a contact layer made of gallium nitride can be formed between the metal electrode and the coupling layer.

Also, the method for manufacturing a vacuum channel transistor of the present invention comprises growing a semiconductor layer made of a gallium nitride-aluminum nitride mixed crystal semiconductor on a substrate having a surface of m-plane and comprising a gallium nitride wurtzite structure crystal. A step of oxidizing the surface of the conductive substrate made of n-type silicon to form an insulating layer made of silicon dioxide, and superimposing the surface of the insulating layer and the surface of the semiconductor layer, the insulating layer and the semiconductor layer It possesses a step of coupling and a step of peeling the substrate from the semiconductor layer, and forming the semiconductor layer as a source electrode and a drain electrode, the semiconductor layer, the entire aluminum nitride with a ratio of the number of molecules Of a wurtzite structure crystal of a gallium nitride-aluminum nitride mixed crystal semiconductor of 0.65 or more, and the source electrode and the drain The emission electrode, in which the angle between the main emission direction of the electron and c-axis direction of the crystal structure are formed to be equal to or less than 30 degrees.

  In the method for manufacturing a vacuum channel transistor, the source electrode and the drain electrode are formed such that a main electron emission direction is a c-axis direction of the crystal structure of the semiconductor layer. Is preferred.

  Since this invention is comprised as mentioned above, there exist the following effects.

  The vacuum channel transistor as the semiconductor device of the present invention uses a gallium nitride-aluminum nitride mixed crystal semiconductor, and the main emission direction of electrons at the source electrode is the c-axis direction of the crystal structure, so that the electron emission efficiency is maximized. The threshold voltage for electron emission can be remarkably reduced. As a result, the operating speed of the vacuum channel transistor can be greatly improved, and operation within a frequency range of 1 THz to 10 THz is also possible. In addition, the vacuum channel transistor of the present invention can achieve a significant reduction in power consumption.

FIG. 1 is a schematic diagram showing a crystal structure of gallium nitride (GaN). FIG. 2 is a diagram showing each axial direction in the crystal structure. FIG. 3 is a diagram schematically showing a cross-sectional structure of a vacuum channel transistor 1 which is a semiconductor element of the present invention. FIG. 4 is a plan view of the vacuum channel transistor 1 as viewed from above. FIG. 5 is a graph comparing the characteristics of the vacuum channel transistor 1 of the present invention and a conventional device. FIG. 6 is a graph showing a comparison of device characteristics when the electron emission direction is the c-axis direction and the m-axis direction. FIG. 7 is a diagram showing each step of the manufacturing method of the vacuum channel transistor 1 of the present invention. FIG. 8 is a diagram showing each step of the manufacturing method of the vacuum channel transistor 1. FIG. 9 is a diagram showing each step of the manufacturing method of the vacuum channel transistor 1. FIG. 10 is a diagram showing each step of the manufacturing method of the vacuum channel transistor 1. FIG. 11 is a diagram showing each step of the manufacturing method of the vacuum channel transistor 1. FIG. 12 is a cross-sectional view showing the configuration of another form of vacuum channel transistor 1a. FIG. 13 is a cross-sectional view showing the configuration of another form of vacuum channel transistor 1b.

  Embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a schematic view showing a crystal structure of gallium nitride (GaN) which is a basic material of a semiconductor element of the present invention. Gallium nitride or aluminum nitride (AlN) can take two types of crystal structures, a hexagonal wurtzite crystal structure and a cubic zinc blende crystal structure, but the wurtzite crystal structure is more stable It is. FIG. 1 shows a unit cell of gallium nitride in a wurtzite crystal. White spheres represent nitrogen atoms (N), and hatched spheres represent gallium atoms (Ga).

  If gallium atoms are replaced with aluminum atoms (Al), FIG. 1 represents the crystal structure of aluminum nitride (AlN). If some of the gallium atoms having the crystal structure shown in FIG. 1 are replaced with aluminum atoms (Al), the crystal body becomes a gallium nitride-aluminum nitride mixed crystal body. The semiconductor element of the present invention is based on a gallium nitride-aluminum nitride mixed crystal semiconductor having a wurtzite crystal structure.

This gallium nitride-aluminum nitride mixed crystal semiconductor can be expressed as Al _x Ga _1-x N, where x is the ratio of the number of aluminum nitride molecules to the entire mixed crystal. However, the numerical value x in the ratio x is in the range of 0 ≦ x ≦ 1. The ratio x can also be said to be the ratio of the number of aluminum atoms to the total number of atoms of gallium and aluminum.

This mixed crystal semiconductor Al _x Ga _1-x N becomes gallium nitride when the ratio x is 0, and has a positive electron affinity of about 3.3 eV. The electron affinity decreases as the proportion x of aluminum nitride in the mixed crystal semiconductor increases. When the ratio x is about 0.65, the electron affinity of the mixed crystal semiconductor is almost zero. In addition, in aluminum nitride where the ratio x is 1, the electron affinity is negative.

FIG. 2 is a diagram illustrating basic vectors in a unit cell of a crystal structure. The unit cell of the wurtzite crystal structure shown in FIG. 1 has a regular hexagonal column shape, and FIG. 2 shows the regular hexagonal column of the unit cell. A basic vector in the direction of the central axis of a regular hexagonal prism that is a unit cell is defined as a vector c. The direction of vector c is the c-axis direction. Vectors from the central axis of the regular hexagonal column to the three vertices of the regular hexagon are designated as vector a ₁ , vector a ₂ , and vector a ₃ , respectively. Note that every other three vertices of the regular hexagon are selected as shown.

The direction and plane in the crystal structure can be represented by these four basic vectors a ₁ , a ₂ , a ₃ and c. A vector direction obtained by adding a vector obtained by multiplying each basic vector a ₁ , a ₂ , a ₃ , and c by coefficients i, j, k, and l is represented as [ijkl]. However, the coefficients i, j, k, and l are integer values, for example, values such as −1, 0, 1 and the like. According to this notation, the c-axis direction is represented by [0001], and the direction of the basic vector a ₁ is represented by [1000]. The direction opposite to the c-axis direction is represented by [000-1].

  A plane whose normal direction is [ijkl] is expressed as (ijkl) plane. That is, a plane perpendicular to the c-axis direction is represented as a (0001) plane. This (0001) plane is simply called a c-plane. In FIG. 2, the plane indicated by the symbol Sc is also the c-plane. A plane corresponding to the side surface of the regular hexagonal column of the unit cell is collectively referred to as an m-plane. An example of the m-plane is the (10-10) plane. The (10-10) plane is a plane indicated by a symbol Sm in FIG. In addition, the (−1010) plane, the (1-100) plane, the (−1100) plane, the (01-10) plane, and the (0-110) plane are called m-planes. The normal direction with respect to the m plane is referred to as the m-axis direction.

  When epitaxial growth is performed based on the c-plane of a crystal having a wurtzite crystal structure, such crystal growth is referred to as c-plane growth. At this time, the c-plane is referred to as a growth plane, and a semiconductor layer formed by the c-plane growth is referred to as a c-plane semiconductor layer. Similarly, crystal growth based on the m-plane is referred to as m-plane growth. In this case, the m-plane is a growth plane, and a semiconductor layer formed by m-plane growth is called an m-plane semiconductor layer. The same applies to the a-plane.

  FIG. 3 is a diagram schematically showing a cross-sectional structure of a vacuum channel transistor 1 which is a semiconductor element of the present invention. The vacuum channel transistor 1 is a field effect transistor having a structure in which electrons as carriers travel in a channel in a vacuum space. For this reason, it is theoretically possible to accelerate the electrons to near the speed of light, and the upper limit of the operation speed does not depend on the saturation speed of the electrons in the semiconductor material. As a result, the operating speed can be greatly improved.

  The vacuum channel transistor 1 is manufactured from a laminate in which an insulating layer 12 is formed on an upper surface of a conductor substrate 11 as a substrate, and a semiconductor layer 13 is provided on the upper surface of the insulating layer 12. See FIG. 10 for this laminate. A source 131 and a drain 132 are formed from the stacked semiconductor layer 13 by dry etching or the like. That is, the source 131 and the drain 132 are semiconductors having the same composition as the semiconductor layer 13.

  The space where the source 131 and the drain 132 face each other is a vacuum space, and this portion becomes a channel through which electrons travel. Note that when the gap between the source 131 and the drain 132 is sufficiently small, the space between the source 131 and the drain 132 is not necessarily evacuated, and a gas such as the atmosphere may exist in this space. The conductor substrate 11 itself corresponds to the gate as a field effect transistor. With these source 131, drain 132, and gate, the vacuum channel transistor 1 operates as a field effect transistor.

The semiconductor layer 13 is a gallium nitride-aluminum nitride mixed crystal semiconductor Al _x Ga _1-x N, and the aluminum nitride ratio x is 0.65 or more. The mixed crystal semiconductor has a wurtzite crystal structure. As shown in FIG. 3, the facing direction of the source 131 and the drain 132 is the c-axis direction of the wurtzite crystal structure. This direction is the main electron emission direction when electrons are emitted from the source 131 toward the drain 132. That is, the main emission direction of electrons emitted from the source 131 is configured to coincide with the c-axis direction.

  FIG. 4 is a plan view of the vacuum channel transistor 1 as viewed from above. The source 131 and the drain 132 formed on the insulating layer 12 on the upper surface of the conductor substrate 11 are configured so that the tips are close to each other. The facing direction of the source 131 and the drain 132 is made to coincide with the c-axis direction of the wurtzite crystal structure of these semiconductor layers. That is, the main emission direction of electrons emitted from the source 131 toward the drain 132 is the c-axis direction.

  A metal electrode 21 for energizing the source 131 is provided on the upper surface of the source 131, and a metal electrode 22 for energizing the drain 132 is provided on the upper surface of the drain 132. In addition, a metal electrode 23 for energizing the gate is provided on the lower surface of the conductor substrate 11. Here, an n-type silicon substrate is used as the conductor substrate 11. When a silicon substrate is used, the insulating layer 12 made of silicon dioxide can be easily formed by heating and oxidation treatment. However, the conductor substrate 11 is not limited to a silicon substrate, and any conductor can be used.

  In the vacuum channel transistor 1 of the present invention, the electron emission direction is the c-axis direction for the following reason. In order to investigate the conditions for improving the efficiency of electron emission, the present inventor investigated the dependence of the electron affinity on the plane orientation by measuring the Schottky characteristics for each plane orientation of gallium nitride having a wurtzite crystal structure. As a result, it was found that the electron affinity is the largest in the m-axis direction and the electron affinity is the smallest in the c-axis direction. Such plane orientation dependence of electron affinity is considered to occur similarly in aluminum nitride and gallium nitride-aluminum nitride mixed crystal semiconductors.

  Since the electron emission efficiency is strongly related to the electron affinity as described above, it is expected that the electron emission efficiency can be minimized and the electron emission efficiency can be maximized by setting the electron emission direction to the c-axis direction. . From this result, it was found that the optimum structure of the vacuum channel transistor using the gallium nitride-aluminum nitride mixed crystal semiconductor is such that the electron emission direction coincides with the c-axis direction.

  Although it is optimal that the electron emission direction coincides with the c-axis, even if the electron emission direction and the c-axis direction form a certain angle, an improvement in electron emission efficiency can be expected to some extent. According to a simulation calculation for examining the influence of piezo polarization and spontaneous polarization on electron emission, the efficiency of electron emission is halved when the angle between the electron emission direction and the c-axis direction exceeds 30 degrees. Therefore, it is desirable that the angle formed between the main electron emission direction and the c-axis direction of the crystal structure is 30 degrees or less.

  FIG. 5 is a graph comparing the characteristics of the vacuum channel transistor 1 of the present invention and a conventional device. FIG. 5 shows the relationship between the source-drain distance and the threshold voltage. The horizontal axis represents the source-drain distance [μm], and the vertical axis represents the threshold voltage. The threshold voltage is the minimum voltage at which current starts to flow when a voltage is applied between the source and drain. The solid line graph corresponds to the device of the present invention, and the dotted line graph corresponds to a conventional silicon-based device.

  The device of the present invention has a structure in which electrons are emitted in the c-axis direction using aluminum nitride as a source electrode. Conventional devices use silicon as the source electrode. The results in FIG. 5 are based on device simulation calculations. For example, when the distance between the source and the drain is 10 μm, the threshold voltage reaches 350 V in the conventional device, whereas the threshold voltage is about 2.5 V in the device of the present invention.

  The calculation points at the left end of both the solid line and the dotted line graph are when the distance between the source and the drain is 150 nm. At this distance between the source and the drain, the threshold voltage of the conventional device is about 10 V, whereas The threshold voltage of the device is 1 mV or less. Thus, according to the present invention, the threshold voltage of the device can be significantly reduced as compared with the prior art, and the efficiency of electron emission can be greatly improved. Thereby, in the device of the present invention, it is possible to realize a significant reduction in power consumption in addition to a significant improvement in operating speed.

  FIG. 6 is a graph showing a comparison of device characteristics when the electron emission direction is the c-axis direction and the m-axis direction with respect to the aluminum nitride source electrode. FIG. 6 shows the characteristics of the drain current with respect to the gate voltage of the device. The horizontal axis represents the gate voltage [V], and the vertical axis represents the drain current [μA]. The results in FIG. 6 are based on device simulation calculations.

  Here, the distance between the source and the drain is set to 1 mm so that the difference in device characteristics depending on the electron emission direction becomes clear. The solid line graph shows a case where the electron emission direction is the c-axis direction, and the dotted line graph shows a case where the electron emission direction is the m-axis direction. When the electron emission direction is set to the c-axis direction, the drain current is remarkably increased as compared with the case where the emission direction is set to the m-axis direction, and it can be seen that the electron emission efficiency is greatly improved.

  When the electron emission direction is the m-axis direction, the drain current hardly flows even when the gate voltage is increased. On the other hand, when the electron emission direction is the c-axis direction, the drain current increases rapidly with an increase in the gate voltage from around 3.5 V. The transconductance in this case is about 1.3 μS when the gate voltage is 10V. For this reason, it can be estimated that the cut-off frequency corresponding to this becomes 1 THz or more.

  Next, a method for manufacturing the vacuum channel transistor 1 of the present invention will be described. 7 to 11 are views showing each step of the manufacturing method of the vacuum channel transistor 1 of the present invention. First, as shown in FIG. 7, the insulating layer 12 is formed on the upper surface of the conductor substrate 11. Here, an n-type silicon substrate is used as the conductor substrate 11. The upper surface of the silicon substrate is heated and oxidized to form the insulating layer 12 made of silicon dioxide.

Also, as shown in FIG. 8, a semiconductor layer 13 is formed on the upper surface of a gallium nitride substrate 14. The substrate 14 is a crystal of gallium nitride having a wurtzite crystal structure, and the upper surface is an m-plane. Crystal growth is performed on the basis of the m-plane of the substrate 14 to form the semiconductor layer 13 made of a gallium nitride-aluminum nitride mixed crystal. The mixed crystal semiconductor Al _x Ga _1-x N of the semiconductor layer 13 has an aluminum nitride ratio x of 0.65 or more, and has the same wurtzite crystal structure as the substrate 14. The c-axis direction of the semiconductor layer 13 is parallel to the m-plane.

Specifically, the semiconductor layer 13 is formed by growing a mixed crystal semiconductor on the m-plane of the substrate 14 by metal organic chemical vapor deposition (MOCVD). For example, a mixed crystal semiconductor Al _x Ga _1-x N is introduced by introducing a mixed gas of trimethylgallium (TMG), trimethylaluminum (TMA), and ammonia (NH ₃ ) onto the m-plane of the substrate 14 held at 1000 ° C. Form. If the mixing ratio of the mixed gas is adjusted, mixed crystal semiconductor Al _x Ga _1-x N having an arbitrary ratio x can be formed. The mixed crystal semiconductor is epitaxially grown in the m-axis direction with respect to the m-plane of the substrate 14. The mixed crystal semiconductor layer 13 is an m-plane semiconductor layer.

  Next, as shown in FIG. 9, the substrate 14 inverted so that the semiconductor layer 13 becomes the lower surface is brought close to the upper surface of the conductor substrate 11 on which the insulating layer 12 is formed, and the semiconductor layer is placed on the upper surface of the insulating layer 12. Paste 13 together. The conductive substrate 11 and the substrate 14 are heat-treated at 1000 ° C. for 20 minutes in a nitrogen gas atmosphere. By this step, the insulating layer 12 of the conductor substrate 11 and the semiconductor layer 13 of the substrate 14 are combined.

  Next, as shown in FIG. 10, the semiconductor layer 13 and the substrate 14 are peeled off by a laser lift-off method. Since misfit dislocations due to lattice mismatch occur at the interface between the substrate 14 and the semiconductor layer 13, the laser beam is easily absorbed. When the laser beam is irradiated, the laser beam is selectively absorbed at the boundary surface, the boundary surface is melted, and the substrate 14 can be easily peeled off.

  Next, as shown in FIG. 11, the semiconductor layer 13 is processed into the shape of a source 131 and a drain 132 made of a mixed crystal semiconductor by chlorine-based dry etching. The distance between the tips of the source 131 and the drain 132 is, for example, 5 μm. The distance between the source and the drain is a size that does not require the use of an ultra-fine processing technique used in a silicon LSI or the like. Therefore, the vacuum channel transistor 1 of the present invention does not require an expensive stepper (reduction projection type exposure apparatus) or an advanced etching technique, and can reduce the manufacturing cost of the device.

  Finally, the metal electrode 23 is formed on the lower surface side of the conductor substrate 11, the metal electrode 21 is formed on the upper surface of the source 131, and the metal electrode 22 is formed on the upper surface of the drain 132. Thereby, the vacuum channel transistor 1 as shown in FIG. 3 is completed. Aluminum can be used as the metal electrodes 21 and 22, and a laminated structure electrode of titanium silicon and aluminum can be used as the metal electrode 23.

  The metal electrode 21 is not formed in a range of 10 μm from the tip (electron emission end) of the source 131. This is because electrons injected from the metal electrode 21 are sufficiently accelerated by the mixed crystal semiconductor in the range of 10 μm on the tip side. However, if the size of this part is increased too much, the distance traveled by the electrons increases and the resistance increases. Therefore, there is a best value for the dimension of this part. In this embodiment, the thickness is 10 μm.

  As an example of actual dimensions of each layer of the vacuum channel transistor 1, for example, the thickness of the insulating layer 12 can be 100 nm, and the thickness of the semiconductor layer 13 can be 100 nm. Further, the distance between the tips of the source 131 and the drain 132 can be set to 5 μm, for example.

  Next, a modification of the vacuum channel transistor of the present invention will be described. FIG. 12 is a diagram schematically showing a cross-sectional configuration of a vacuum channel transistor 1a as a modification of the vacuum channel transistor of the present invention. In this vacuum channel transistor 1a, in addition to the configuration of the vacuum channel transistor 1 shown in FIG. 3, coupling layers 151 and 152 are formed on the upper surfaces of the source 131 and the drain 132, respectively. The metal electrodes 21 and 22 are provided on the upper surfaces of the coupling layers 151 and 152. The other configuration of the vacuum channel transistor 1a is the same as that of the vacuum channel transistor 1 of FIG.

The bonding layers 151 and 152 are mixed crystals whose compositions are adjusted so that the ratio x of the mixed crystal semiconductor Al _x Ga _1-x N monotonously decreases from the source 131 and drain 132 side toward the metal electrodes 21 and 22 side. It is a semiconductor layer. In other words, in the coupling layers 151 and 152, the ratio x in the mixed crystal semiconductor monotonously increases from the metal electrodes 21 and 22 side toward the source and drain sides. In the lower end surfaces of the coupling layers 151 and 152, x = 0.65, and in the upper end surface, x = 0.2. The ratio x of the mixed crystal semiconductor monotonously decreases upward. The thickness of the coupling layers 151 and 152 is 500 nm.

The larger the ratio x of the mixed crystal semiconductor Al _x Ga ₁ -xN, the higher the contact resistivity between the mixed crystal semiconductor and the metal electrode. For this reason, it is desirable that the ratio x is smaller at the contact interface between the mixed crystal semiconductor and the metal electrode because the electric resistance becomes smaller. However, _if the ratio x of the mixed crystal semiconductor Al _x Ga _1-x N of the source 131 is reduced, the electron emission efficiency is lowered. Therefore, in the vacuum channel transistor 1a, the coupling layers 151 and 152 are formed on the upper surfaces of the source 131 and the drain 132 so that the conflicting demands of improving the efficiency of electron emission and reducing the contact resistivity with the metal electrode can be achieved. It is a thing.

  FIG. 13 is a diagram schematically showing a cross-sectional configuration of a vacuum channel transistor 1b as another modification. In the vacuum channel transistor 1b, contact layers 161 and 162 on the upper surfaces of the coupling layers 151 and 152 are added to the configuration of the vacuum channel transistor 1a shown in FIG. The metal electrodes 21 and 22 are provided on the upper surfaces of the contact layers 161 and 162. The other configuration of the vacuum channel transistor 1b is the same as that of the vacuum channel transistor 1a of FIG.

  In the vacuum channel transistor 1 b, contact layers 161 and 162 are added between the coupling layers 151 and 152 and the metal electrodes 21 and 22. The contact layers 161 and 162 are layers made of gallium nitride and have a low contact resistivity with the metal electrode. Therefore, in the vacuum channel transistor 1b, the contact resistivity with the metal electrode can be further reduced as compared with the vacuum channel transistor 1a of FIG. Thereby, high-concentration electrons can be supplied to the source 131, and the threshold voltage can be further reduced. In this example, the thickness of the coupling layers 151 and 152 is 500 nm, and the thickness of the contact layers 161 and 162 is also 500 nm.

  In the above embodiment, the surface orientation of the upper surface of the substrate 14 is the m-plane, but the surface orientation of the upper surface of the substrate 14 is the a-plane, and an equivalent device can be manufactured. As the best mode, it is desirable that the semiconductor layer made of a mixed crystal semiconductor is an m-plane semiconductor layer or an a-plane semiconductor layer and is not affected by piezoelectric polarization or spontaneous polarization. When electrons are accelerated in the m-plane or a-plane and emitted in the c-axis direction, the efficiency of electron emission is maximized and the threshold voltage can be reduced.

  However, the actual plane orientation of the upper surface of the semiconductor layer 13 does not have to be completely coincident with the m-plane or the a-plane, and may be inclined within a certain angle. Further, the direction in which electrons are emitted does not have to coincide completely with the c-axis, and may be inclined within a certain angle with respect to the c-axis. According to a simulation calculation for examining the influence of piezo polarization and spontaneous polarization on electron emission, the efficiency of electron emission is halved when the angle between the electron emission direction and the c-axis direction exceeds 30 degrees. Therefore, it is desirable that the angle formed between the main electron emission direction and the c-axis direction of the crystal structure is 30 degrees or less.

  When accelerating electrons in the semiconductor layer of the source, the electrons are accelerated in a plane close to the m-plane or a-plane that is not easily affected by piezo polarization or spontaneous polarization, thereby accelerating the carriers in the layer with a uniform electric field distribution. Therefore, the acceleration efficiency of electrons can be increased. Further, since the m-plane or a-plane is not easily affected by piezo-polarization or spontaneous polarization, there is no band barrier at the heterointerface, and carriers can be easily injected from the metal electrode. In the case of the vacuum channel transistor 1 a having the coupling layer 151, the coupling layer 151, and the vacuum channel transistor 1 b having the contact layer 161, electrons move from the metal electrode 21 to the source 131. Since the direction is the m-axis or a-axis direction, it is possible to move electrons efficiently with low resistance. With these effects, the threshold voltage of the vacuum channel transistor can be reduced and the efficiency can be improved.

  As described above, the vacuum channel transistor as the semiconductor element of the present invention uses a gallium nitride-aluminum nitride mixed crystal semiconductor, and the main emission direction of electrons at the source electrode is the c-axis direction of the crystal structure. The emission efficiency can be maximized and the threshold voltage for electron emission can be significantly reduced. As a result, the operating speed of the vacuum channel transistor can be greatly improved, and operation within a frequency range of 1 THz to 10 THz is also possible. In addition, the vacuum channel transistor of the present invention can achieve a significant reduction in power consumption.

  In the embodiment described above, the semiconductor element is described as a vacuum channel transistor, but the semiconductor element of the present invention is not limited to a vacuum channel transistor. The present invention can be applied to an electron supply element and other semiconductor elements with any electron emission.

  According to the present invention, the efficiency of electron emission in the vacuum channel transistor can be maximized and the threshold voltage for electron emission can be significantly reduced, thereby greatly improving the operating speed of the vacuum channel transistor and reducing the power consumption. It can be greatly reduced. As a result, a vacuum channel transistor that can operate within a frequency range of 1 THz to 10 THz can be provided.

1, 1a, 1b Vacuum channel transistor 11 Conductor substrate 12 Insulating layer 13 Semiconductor layer 14 Substrate 21, 22, 23 Metal electrode 131 Source 132 Drain 151, 152 Coupling layer 161, 162 Contact layer

Claims (10)

An electrode ( 131 ) made of a crystal of a wurtzite structure of a gallium nitride-aluminum nitride mixed crystal semiconductor in which aluminum nitride has a total molecular weight ratio of 0.65 or more ,
The electrode (131) is a semiconductor device in which the angle formed between the main electron emission direction and the c-axis direction of the crystal structure is 30 degrees or less. A semiconductor device according to claim 1,
The said electrode (131) is a semiconductor element arrange | positioned so that the main emission direction of an electron may turn into the c-axis direction of a crystal structure. A conductor substrate (11) forming a gate electrode;
An insulating layer (12) made of an insulator formed on the conductor substrate (11);
A source electrode (131) formed on the insulating layer (12);
A drain electrode (132) formed on the insulating layer (12) and provided to face the source electrode (131);
The source electrode 131 is composed of a wurtzite structure crystal of a gallium nitride-aluminum nitride mixed crystal semiconductor in which aluminum nitride has a total number ratio of 0.65 or more, and emits electrons mainly. The vacuum channel transistor is arranged so that the angle formed by the direction and the c-axis direction of the crystal structure is 30 degrees or less. A vacuum channel transistor according to claim 3 ,
The source electrode (131) is a vacuum channel transistor arranged such that the main electron emission direction is the c-axis direction of the crystal structure. A vacuum channel transistor according to claim 4 ,
The conductor substrate (11) is made of n-type silicon,
The insulating layer (12) is a vacuum channel transistor which is a layer of silicon dioxide formed on the surface of an n-type silicon substrate. A vacuum channel transistor according to claim 5 ,
The source electrode (131) is a vacuum channel transistor in which a metal electrode (21) for energizing the source electrode (131) is connected. A vacuum channel transistor according to claim 6 , comprising:
A gallium nitride-aluminum nitride mixed crystal semiconductor is formed between the source electrode (131) and the metal electrode (21), and the proportion of aluminum nitride is from the metal electrode (21) side to the source electrode (131) side. A vacuum channel transistor with a coupling layer (151) increasing towards it. A vacuum channel transistor according to claim 7 ,
A vacuum channel transistor having a contact layer (161) made of gallium nitride between the metal electrode (21) and the coupling layer (151). A step of crystal growth of a semiconductor layer (13) made of a gallium nitride-aluminum nitride mixed crystal semiconductor on a substrate (14) comprising a wurtzite structure crystal of gallium nitride and having a m-plane surface;
oxidizing the surface of the conductive substrate (11) made of n-type silicon to form an insulating layer (12) made of silicon dioxide;
Overlaying the surface of the insulating layer (12) and the surface of the semiconductor layer (13) to bond the insulating layer (12) and the semiconductor layer (13);
Peeling the substrate (14) from the semiconductor layer (13);
Possess and forming said semiconductor layer (13) as a drain electrode (132) and the source electrode (131),
The semiconductor layer (13) is made of a wurtzite structure crystal of a gallium nitride-aluminum nitride mixed crystal semiconductor in which aluminum nitride has a molecular number ratio of 0.65 or more as a whole,
The source electrode (131) and the drain electrode (132) are formed so that the angle formed between the main electron emission direction and the c-axis direction of the crystal structure is 30 degrees or less. Manufacturing method. A method of manufacturing a vacuum channel transistor according to claim 9 ,
The source electrode (131) and the drain electrode (132) are formed in such a way that the main electron emission direction is the c-axis direction of the crystal structure of the semiconductor layer (13). Production method.

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