JP6322263B2 - Power over data line detection and classification scheme using PD information stored in memory - Google Patents

Description

(Cross-reference to related applications)
The present application is Jeffrey Heath et al. Is based on and claims priority from US Provisional Application No. 61 / 909,232, filed Nov. 26, 2013, which is hereby incorporated by reference. .

(Field of the Invention)
The present invention relates to a power over data line (PoDL) system in which power from a power supply (PSE) conducts a differential data signal (typically an Ethernet signal). Is transmitted to the powered device (PD) through a single wire pair that is also used to perform a handshake routine before sufficient PoDL voltage is applied to the wire pair.

(background)
It is known to transmit a power over data line to power a remote device. Power over Ethernet (PoE) is an example of one such system. In PoE, limited power is transmitted from an Ethernet switch to an Ethernet-connected device (eg, VoIP phone, WLAN transmitter, security camera, etc.). DC power from the switch is transmitted through two twisted wire pairs in a standard CAT-5 cable. Since the DC common mode voltage does not affect the data, one or both of the wire pairs also carry a differential data signal. In this way, the need to provide any external power source to the powered device (PD) can be eliminated. A standard for PoE is presented in IEEE 802.3, which is hereby incorporated by reference. In PoE, the power supply (PSE) causes any type of PD to have the same normalized voltage sufficient to ensure that the PD receives at least 37V (despite the unknown voltage drop along the wire pair). Also supply.

  A newer technology is the power over data line (PoDL), in which power in addition to differential data is transmitted through a single twisted wire pair. As of the date of this disclosure, IEEE is in the process of being criticized to develop a standard for PoDL as IEEE P802.3bu. Since PoDL is more adaptable than PoE, and PoDL requires one fewer wire pair, PoDL can be a common technology, particularly in automobiles.

  It is envisioned that most future applications of PoDL require some handshake between the PSE and PD before sufficient power / voltage is applied to the data line by the PSE. This is because different types of PDs may require different voltage levels, different maximum power levels, or are not PoDL compliant. Other information may also be communicated during the handshake.

  Such a handshake may consist of a low power / voltage signal being generated on the wire pair by the PSE, and the PD identifies in a unique way to the PSE that the PD is PoDL compliant (typical As well as identifying the voltage and power requirements among other information (typically referred to as classification signatures).

  In automotive applications for PoDL, for example, PSE and PD types can be highly tuned by the automobile manufacturer. This allows various innovative and customized techniques to be used for detection and classification schemes.

  Therefore, what is needed is a variety of possible detection and classification schemes for PoDL that can be applied to different applications.

The present invention provides, for example:
(Item 1)
A power over data line (PoDL) system comprising:
A power supply (PSE) coupled to a power receiving device (PD) via a wire pair, wherein a differential data signal and DC power are transmitted over the same wire pair;
A variable voltage converter in the PSE coupled to receive an input voltage and output a regulated voltage, the magnitude of the regulated voltage being controlled by a control signal;
A classification circuit in the PD coupled to the wire pair;
A PSE controller circuit in the PSE configured to generate a classification signal through the wire pair, the classification signal received by the classification circuit in the PD, and the classification signal converted by the classification circuit. A PSE controller circuit that provides a classification signature through the wire pair by:
A PD load coupled to the wire pair for receiving power from the variable voltage converter;
The PSE controller circuit detects the classification signature, which identifies the specific voltage requirements of the PD;
The PSE controller is configured to control the variable voltage converter to output a voltage corresponding to the particular voltage requirement of the PD identified by the classification signature.
(Item 2)
The item further comprising an under voltage lockout (UVLO) circuit in the PD configured to detect a DC voltage on the wire pair and to determine whether the voltage is above a threshold voltage. A system as described,
The UVLO circuit includes a timer circuit having a short rest period;
The PSE controller is configured to perform a handshake routine with the PD during a classification phase in which the PoDL characteristics of the PD are transmitted to the PSE, and at least one of the classification signals generated by the PSE. Part exceeds the threshold voltage of the UVLO circuit,
The timer circuit is configured to be effective during the handshake routine to prevent the UVLO circuit from applying the DC voltage on the wire pair to the DC load during the brief pause period. The PD load is decoupled from the wire pair during the handshake routine despite the classification signal exceeding the threshold voltage.
(Item 3)
A power over data line (PoDL) system comprising:
A power supply (PSE) coupled to a power receiving device (PD) via a wire pair, wherein a differential data signal and DC power are transmitted over the same wire pair;
A detection circuit in the PD coupled to the wire pair, the detection circuit generating a detection signature in response to a detection test signal from the PSE;
A classification circuit in the PD coupled to the wire pair, the classification circuit comprising: a classification circuit that generates a classification signature in response to a classification test signal from the PSE;
The PSE generates the detected test signal having a first voltage polarity on the wire pair and generates the classification test signal having a second voltage polarity opposite to the first polarity on the wire pair. Is composed of
The detection circuit generates the detection signature in response to the detection test signal having the first voltage polarity, and the classification circuit is responsive to the classification test signal having the second voltage polarity. A system that generates classification signatures.
(Item 4)
A first diode network coupling the detection circuit to the wire pair, wherein the first diode network allows only a signal of the first voltage polarity to be received by the detection circuit; A diode network;
A second diode network coupling the classification circuit to the wire pair, wherein the second diode network allows only a polarity signal of the second voltage to be received by the classification circuit; A system according to any of the preceding items, further comprising two diode networks.
(Item 5)
A power over data line (PoDL) system comprising:
A power supply (PSE) coupled to a power receiving device (PD) via a wire pair, wherein a differential data signal and DC power are transmitted over the same wire pair;
A presence circuit in the PD coupled to the wire pair, wherein the presence circuit generates a presence signature in response to a detected test signal from the PSE, the presence circuit specifying a voltage across it A presence circuit with a voltage limiting circuit to limit the scale;
A current source in the PSE that is coupled to the wire pair to conduct current through the voltage limiting circuit, thereby causing the voltage limiting circuit to generate the presence signature of the PD;
A first detector at the PSE coupled to the wire pair and configured to detect the presence signature on the wire pair.
(Item 6)
The system of any of the preceding items, wherein the presence signature comprises the limited voltage of the scale, the system comprising:
Processing circuitry in the PSE configured to associate the classification signature with specific PoDL characteristics of the PD;
A power source at the PSE that is controlled by the PSE in response to the classification signature to provide power matching the classification signature to the PD via the wire pair.
(Item 7)
A system according to any of the preceding items, wherein the current source generates a constant current and the voltage limiting circuit is a zener diode coupled across the wire pair.
(Item 8)
The processing circuit in the PSE configured to apply a first current I1 to the wire pair by controlling the current source;
The first in the PSE is configured to detect the voltage V1 across the wire pair in response to the first current I1, while the voltage limiting circuit is configured to limit the voltage across the wire pair. A detector;
The processing circuitry in the PSE configured to also apply a second current I2 to the wire pair by controlling the current source;
The first current in the PSE is configured to detect the voltage V2 across the wire pair in response to the second current I2 while the voltage limiting circuit is configured to limit the voltage across the wire pair. A detector;
The processing circuitry configured to calculate the resistance R of the wire pair using V1, V2, I1 and I2, and
The processing circuit configured to calculate the voltage drop Vd along the wire pair by Vd = I * R at any current I;
A power source in the PSE that is controlled by the PSE to supply a voltage on the wire pair to power the PD when the power source supplies the voltage on the wire pair A system according to any of the preceding items, further comprising: a power source that is adjusted to account for the voltage drop along the wire pair.
(Item 9)
A power over data line (PoDL) system comprising:
A power supply (PSE) coupled to a power receiving device (PD) via a wire pair, wherein a differential data signal and DC power are transmitted over the same wire pair;
A classification circuit in the PD coupled to the wire pair, the classification circuit generating a classification signature in response to a classification test signal from the PSE, the classification circuit including a surge voltage protector circuit The surge voltage detector comprises at least one switch in series with a wire in the wire pair, the detector senses a voltage across the wire pair, and the detector detects the voltage across the wire pair. Controlling the switch to be high impedance when a threshold voltage is exceeded, wherein the classification signature includes the threshold voltage of the surge voltage protector;
A ramp voltage generator at the PSE configured to apply a ramp voltage to the wire pair at least until the threshold voltage is reached;
A detector in the PSE configured to detect the threshold voltage by detecting a change in impedance of the wire pair;
A processing circuit in the PSE configured to associate the classification signature with a particular PoDL characteristic of the PD;
A power source at the PSE that is controlled by the PSE in response to the classification signature to provide power matching the classification signature to the PD via the wire pair.
(Item 10)
A resistor connected across the at least one switch, the resistor having a value associated with a PoDL characteristic of the PD;
The PSE configured to detect an approximate resistance value when the at least one switch becomes high impedance after the threshold voltage is exceeded;
The system according to any of the preceding items, further comprising: the PSE configured to adjust its behavior associated with the PoDL characteristic in response to detecting the approximate resistance value.
(Item 11)
A power over data line (PoDL) system comprising:
A power supply (PSE) coupled to a power receiving device (PD) via a wire pair, wherein a differential data signal and DC power are transmitted over the same wire pair;
A classification circuit in the PD coupled to the wire pair, wherein the classification circuit generates a classification signature in response to a classification test signal from the PSE;
A surge voltage protection circuit, wherein the surge voltage detector comprises at least one switch in series with a wire in the wire pair, the detector senses a voltage across the wire pair, the detector comprising: A surge voltage protection circuit that controls the switch to be high impedance when the voltage across the wire pair exceeds a threshold voltage;
A resistor connected across the at least one switch, the resistor having a value associated with a PoDL characteristic of the PD, the PSE comprising:
The PSE configured to detect the approximate resistance value when the at least one switch becomes high impedance after the threshold voltage is exceeded, wherein the classification signature is the approximate resistance Including value,
A classification circuit;
A ramp voltage generator at the PSE configured to apply a ramp voltage to the wire pair at least until the threshold voltage is reached;
A processing circuit in the PSE configured to associate the classification signature with a particular PoDL characteristic of the PD;
A power source at the PSE that is controlled by the PSE in response to the classification signature to provide power matching the classification signature to the PD via the wire pair.
(Item 12)
A power over data line (PoDL) system comprising:
A power supply (PSE) coupled to a power receiving device (PD) via a wire pair, wherein a differential data signal and DC power are transmitted over the same wire pair;
A memory circuit in the PSE for storing information identifying PoDL power requirements for the PD for powering the PD through the wire pair;
The PSE includes a PSE controller;
When the PSE is activated, the PSE controller is configured to access the information stored in the memory, and to power the PD based on the information, A system configured to supply the power to the wire pair by controlling the PSE.
(Item 13)
The system according to any of the preceding items, wherein the PSE controller is configured not to perform a PoDL detection and classification routine that detects the power requirements of the PD each time the PSE is activated.
(Item 14)
The system according to any of the preceding items, wherein the PSE controller is configured to perform a shortened PoDL detection and classification routine that detects the power requirements of the PD each time the PSE is activated. .
(Item 15)
The information stored in the memory circuit includes information obtained by a detection and classification routine that detects the power requirements of the PD and prior to the activation of the PSE. The system according to any of the above items, performed.
(Item 16)
A system according to any of the preceding items, wherein the information is stored in the memory circuit prior to a first use of the PSE in the system.
(Item 17)
The system according to any of the preceding items, wherein the information in the memory circuit includes data transmitted to the PSE by the PD prior to activation of the PSE.
(Item 18)
A resistor in the PD coupled across the wire pair, wherein the resistance value of the resistor further corresponds to a maintenance power signature indicating that the PD is coupled to the wire pair. A system according to any of the above items, comprising:
The PSE controller is configured to supply a test current to the wire pair and configured to detect whether a sensed resistance is equal to or less than the resistance value of the resistor. Has been
The PSE controller is configured to determine that the PD is coupled to the wire pair when a sensed resistance is approximately equal to or less than the resistance value of the resistor;
The PSE controller is configured to determine that the PD is not coupled to the wire pair when a detected resistance is greater than the resistance value of the resistor.
(Item 19)
When the PSE controller detects that the PD is continuously coupled to the wire pair after the information is stored in the memory circuit, the PSE controller Configured to access the stored information and configured to supply the power to the wire pair by controlling the PSE to power the PD based on the information A system according to any of the preceding items, configured as follows.
(Item 20)
When the PSE controller detects that the PD is disconnected from the wire pair and then connected, the PSE controller performs a handshake routine with the PD to identify the PD's PoDL requirements. And configured to supply the power to the wire pair by controlling the PSE to power the PD based on the result of the handshake routine. The system according to any one of the above items.
(Item 21)
A system according to any of the preceding items, further comprising the PSE controller configured to store a result from the handshake routine in the memory circuit.
(Item 22)
A power over data line (PoDL) system comprising:
A power supply (PSE) coupled to a power receiving device (PD) via a wire pair, wherein a differential data signal and DC power are transmitted over the same wire pair;
An alternative power source coupled to the PD via other than the wire pair;
The power transmitted by the PSE through the wire pair powers at least the communication circuitry in the PD, so that the PD is sufficiently routed through the wire pair to convey information to the PSE via the wire pair. Powered system.

(Summary)
The PoDL system includes a PSE that is connected to the PD via a wire pair, where differential data and DC power are transmitted over the same wire pair. Typically, a low voltage / current detection and classification routine is required at each system startup, which allows the PD to communicate its PoDL requirements to the PSE. Various techniques have been described that simplify or eliminate such start-up routines, or that enable increased flexibility for PoDL systems. Such techniques include a method for identifying a particular PD operating voltage; a method for disabling the PD's UVLO circuit during such a routine; using an opposite polarity voltage for the two routines; Using voltage limiters or surge protectors to convey information; detecting loop resistance; using PSE memory to store previous results of routines; using wire pairs Powering the PD communication circuit while the PD load is powered by an alternative power source.

(Summary)
Various detection and classification techniques for the PoDL system are described herein. The best choice depends on the specific application.

Examples of the techniques described are
A technology for communicating that the PD is PoDL-compatible;
A technique for communicating a voltage signature from the PD to the PSE identifying the voltage level to be supplied to the PD;
A technology that allows a PSE to supply a wide range of voltages to different types of PDs;
A technique for transmitting the maximum power signature from the PD to the PSE;
A technique that prevents an undervoltage lockout (UVLO) circuit in the PD from coupling the input voltage on the data wire to the PD load when the detection / classification test voltage exceeds the UVLO threshold voltage;
A technique that allows the detected voltage polarity to be opposite the classification voltage polarity to separate the two schemes and to avoid interference from other circuits;
A technique for generating a detection or classification signature for a PD based on a clamp voltage (low impedance above a voltage threshold) provided by a clamp circuit in the PD, wherein the clamp can double as an ESD protection circuit;
A technique for generating a PD detection or classification signature based on a threshold voltage (high impedance above the voltage threshold) of a surge stopper in the PD, wherein the surge stopper can also serve as an ESD protection circuit;
A technique that automatically identifies the loop resistance between the PSE and the PD so that the PSE can adjust its output voltage to deliver a regulated voltage to the PD;
A technique to detect whether the PD is still coupled to the PSE even when the PD is not powered, or whether the PD has been disconnected and replaced;
A technique for storing detection and classification information in memory in the PSE so that handshaking does not have to be performed at each startup;
While allowing the primary PD load to be powered by an alternative power source on the PD side, the PSE can also route the data wires so that the PD can communicate while the alternative power source is disabled. Through which the power can be supplied to the front end (ie, “physical layer”) of the PD.

  Various other embodiments have been described.

  The terms PSE and PD are used throughout this disclosure to distinguish between devices that supply power and devices that receive power, and such devices / devices are Ethernet devices unless otherwise specified. / Not limited to devices.

FIG. 1 illustrates a PoDL system that enables Ethernet communication and power transfer through a single wire pair, where the PSE is applied to the PD depending on the detected voltage requirements of the PD. It is possible to supply a variable voltage. FIG. 2A illustrates disabling the UVLO circuitry in the PD for a time sufficient to perform handshaking when the handshake voltage exceeds the UVLO threshold. FIG. 2B is a flowchart illustrating the operation of FIG. 2A. FIG. 3A illustrates performing a detection and classification scheme using opposite voltage polarities in order to effectively isolate the detection and classification circuit. FIG. 3B is a flowchart illustrating the operation of FIG. 3A. FIG. 4A shows a circuit in which PoDL information about the PD is conveyed by the clamp voltage magnitude of a Zener diode or other clamp circuit in the PD. FIG. 4B shows the voltage drop caused by the clamp circuit of FIG. 4A. FIG. 4C is a flowchart illustrating the operation of FIG. 4A when detecting PoDL information using a clamp circuit. FIG. 4D is a flowchart illustrating the operation of FIG. 4A when using the clamp circuit in FIG. 4A to determine the loop resistance between the PSE and PD, such as to adjust the output voltage of the PSE. is there. FIG. 5A illustrates the use of a surge stopper in the PD to convey PoDL information about the PD and to protect the PD from voltage surges. FIG. 5A also shows a resistor for transmitting other PoDL information after the surge stopper is activated. FIG. 5B is a flowchart illustrating the operation of FIG. 5A. FIG. 5C shows how the surge stopper of FIG. 5A becomes high impedance when the input voltage reaches a threshold. FIG. 6A shows how detection / classification information for PDs is stored in memory on the PSE and at startup PSE to eliminate the need for a full handshake routine to reduce start-up time. It can be accessed by FIG. 6A also shows a “maintenance power signature” resistor in the PD that communicates whether the PSE is still connected to the PSE. FIG. 6B is a flowchart illustrating the operation of FIG. 6A in connection with a “maintenance power signature” resistor. FIG. 6C is a flowchart illustrating the operation of FIG. 6A related to storing detection / classification information in memory. FIG. 7A shows that the front end of the PD by the PSE because the use of the alternative power source on the PD side powers the main PD load while the PD can still communicate when the alternative power source is disabled. Indicates that power is supplied. FIG. 7B is a flowchart illustrating the operation of FIG. 7A.

  Identical or equivalent elements are labeled with the same numbers.

(Detailed explanation)
The various circuits shown present relevant aspects of the PoDL system, where, for example, a single twisted wire pair carries Ethernet data and detection / classification information and power. The portion of the PoDL system associated with the differential data path is independent of the present invention and may be conventional. Therefore, the data path is not described.

  In future PoDL systems, unlike standardized PoE systems, different PDs may have different input voltage requirements. For example, one type of PD may require a regulated 5V input across the wire pair, eliminating the need for a PD voltage regulator, while another PD requires at least 24V and another PD Includes a voltage regulator to power the load. Therefore, if the PSE needs to support various types of PDs that can be connected to the PSE via a wire pair, the PSE needs to know the “voltage classification” of the PD and the required voltage across the wire pair. It is necessary to be able to generate a variable voltage that supplies

  The PSE needs to be able to supply a voltage as low as 5V to some types of PDs and a fairly high voltage to other types of PDs, and the type of PD connected Assuming that is initially unknown to the PSE, the detection / classification test needs to use a low voltage to ensure that there is no damage to the PD.

  FIG. 1 illustrates the relevant functional units in a PoDL system, according to one embodiment of the present invention. PSE 10 and PD 12 are shown coupled through a single data wire pair 14 of arbitrary length. Wire pair 14 may conduct an Ethernet differential data signal filtered by capacitor 16, where wire pair 14 is further DC isolated from each differential data processing circuit 18 and 20 by transformers 22 and 24. Is done. The Ethernet data portion of the circuit can be conventional and is not relevant to the present invention. Any DC power supplied to the PD 12 by the PSE 10 is cut off from the differential data processing circuits 18 and 20 by operation of the capacitor 16 and transformers 22 and 24.

  The PSE controller 26 can receive both AC and DC signals on the wire pair 14 and transmit both AC and DC signals to the PD controller 28 via the wire pair 14. The PSE controller 26 may be an IC that performs various routines under the control of either a processor or firmware. The PSE controller 26 detects the PD 12 to be PoDL compliant and obtains further information (eg, a classification signature) from the PD 12 that conveys the PD 12 PoDL requirements. And do a handshake routine. PD controller 28 may be an IC that performs various routines under the control of either a processor or firmware.

  The PD controller 28 performs a handshake routine in response to the signal from the PSE controller 26 so that the PSE 10 supplies the appropriate voltage and up to the maximum power level (defined in the classification signature). In order to supply power to the PD 12, the requested PoDL information of the PD controller 28 is transmitted.

  To test for a signature response from the PD 12 that identifies the PD 12 as PoDL capable at system startup, the PSE controller 26 provides a limited current or voltage (eg, 5V) on the wire pair 14. . Various detection signature techniques can be used. In one embodiment, a value resistor (such as 25K ohms) is traversed across the wire pair 14 in the PD 12, and this signature resistance value is determined by detecting the resulting voltage or current. 26. In another embodiment, a capacitor, zener diode or other circuit element is connected to the wire pair 14 in the PD 12 and the resulting voltage gradient (if a capacitor is used) or limited voltage magnitude (the zener diode is Communicates whether the PD is PoDL-enabled. If no such signature signal is detected, the PSE controller 26 continues to handshake and does not provide power through the wire pair 14.

  If the detection signature is identified by the PSE controller 26, an additional low current or voltage signal is generated by the PSE controller 26 during the classification phase to identify details regarding the PoDL requirements of the PD 12. Various classification techniques are described below with reference to the drawings.

  Since the PSE 10 can be coupled to various PDs and different PDs may require different operating voltages than the PSE 10, the PD 12 needs to communicate its operating voltage requirements (eg 5V, 12V, 44V, etc.) is there.

Once the classification phase is complete, the PSE controller 26 controls the variable voltage converter 30, which can receive an unregulated input voltage of, for example, 12V in automotive applications and is detected by the classification signature from the PD 12. Output adjustment voltage V _{OUT —} DC. PSE controller 26 then controls a switch 32 (eg, a MOSFET) that couples the output of converter 30 to wire pair 14 via filtering inductors 34 and 36. The variable voltage converter 30 may be a plurality of different voltage sources that are capable of outputting different voltages when enabled, or the converter 30 may have a feedback voltage or a reference voltage selected as a regulated voltage. May be a single converter that changes to output. For example, a resistance division network connected between the output voltage terminal and the error amplification feedback terminal may be adjusted by a control signal that causes the switching voltage converter to output a different adjustment voltage. Such variable feedback techniques and switching regulators are well known.

  The PD controller 28 includes an under voltage lockout (UVLO) circuit (not shown in FIG. 1) that simply couples the voltage on the wire pair 14 to the PD load 38 when the voltage exceeds a threshold level (such as 5V). Including. Once this level is detected, PD controller 28 closes switch 40 (eg, a MOSFET) to couple incoming PoDL voltage Vin_DC to PD load 38 via filtering inductors 42 and 44. The DC voltage is cut off from the data path by the filtering capacitor 16. The PD load 38 may or may not include a voltage converter for converting the voltage on the wire pair 14 to the regulated voltage required by the main PD load.

  The front end of the PD 12 may include a diode bridge that ensures the correct polarity voltage provided to the PD 12.

  One problem with the system described above is that the PD load 38 can require an operating voltage of 5V from the PSE 10, but the detection and classification scheme can use voltages above 5V. The PSE 10 needs to generate a significantly higher detection and classification signal so that the voltage drop along the wire pair 14 does not mitigate the detection / classification signature signal below the threshold level for detection by the PSE 10. However, the inventors do not want to activate the UVLO circuit in the PD 12 during the detection or classification phase.

  FIG. 2A shows a timer circuit that can be used to disable UVLO of the PD during the detection and / or classification phase. FIG. 2B is a flowchart showing the steps performed by the circuit of FIG. 2A. In the following description, it is assumed that the detection signal provided by PSE 10 is always below any UVLO threshold voltage, but the classification can be above the UVLO threshold voltage. However, the same circuit can be used to disable the UVLO circuit during the detection phase. The UVLO circuit, PD classification circuit and timer may be present in the PD controller 28IC.

  The UVLO circuit uses the comparator 50 to compare the voltage PD_Vin across the wire pair 14 with the threshold voltage Vth, thereby determining when the switch 40 should be closed in order for the PoDL voltage to be applied to the PD load 38. To do. Suppose Vth is 5V.

  In step 52 of FIG. 2B, the detection phase is performed at a low voltage. If the detection signature (such as a resistance value) from the PD 12 indicates that the PD 12 is PoDL compliant (step 54), the process proceeds to the classification stage (step 56). If no detected signature is detected, the PoDL handshake process ends (step 58).

  The PD classification circuit 60 (FIG. 2A) in the PD controller 28 (FIG. 1) detects the classification signal from the PSE 10 and starts the timer 62. All processing can be under the control of firmware in the PD controller 28 or a programmed processor. The PD controller 28 estimates that any voltage within a certain period after the detection phase is the classification phase. Assuming that the detection or classification signal can exceed 5V (ie, Vth), timer 62 blocks the signal from UVLO comparator 50 during a brief pause (such as 1 ms) (step 64). PD classification circuit 60 then presents the appropriate classification signature on wire pair 14 for analysis by PSE 10. The classification phase is then terminated by PSE10. Shortly thereafter, timer 62 pauses and couples the output of UVLO comparator 50 to switch 40 (step 66). Then, when the PSE 10 supplies a PoDL operating voltage greater than Vth to the PD 12, the switch 40 is closed by the UVLO circuit and power is supplied to the PD load 38 via the wire pair 14 (step 66).

  FIGS. 3A and 3B are directed to a technique that allows the detection and classification circuits to be effectively separated from each other during the handshake phase, thereby avoiding circuit interference. Thus, the detection and classification circuits may be similar by using resistors, capacitors or Zener diodes, etc. to convey signature information. In addition, when the PD operating voltage is similar to the handshake voltage, the technique may eliminate the need for a timer in FIG. 2A. This is accomplished by the PSE 10 using one voltage polarity of the detection phase and the opposite polarity of the classification phase. If the polarity of the classification stage is opposite to the polarity of the operating voltage, the UVLO circuit in the PD will not detect a classification voltage that is above the threshold level that triggers the UVLO circuit.

  In step 74 of FIG. 3B, the system designer determines the normal operating voltage polarity of the PSE PoDL. In FIG. 3A, diode 76 is configured such that only signals having the appropriate voltage polarity are coupled to PD classification circuit 78 and PD detection circuit 80. Circuits 78 and 80 may present signature resistance values, Zener diode thresholds, capacitor values, or may perform other functions on the PSE signal that communicate the desired PoDL information to PSE 10. The inventors presume that the normal voltage polarity of PoDL is the same polarity used during the low voltage / current detection phase.

  In step 82, detection is performed with normal polarity, and diode 76 coupling detection circuit 80 to wire pair 14 is forward biased. If the detection signal is above the UVLO threshold voltage of the UVLO circuit 84, the timer 62 can be used to prevent the UVLO circuit 84 from closing the switch 40, as described above.

  In step 86, it is determined whether the PD is PoDL compliant. If the PD is not PoDL compliant, the PoDL handshake routine is terminated (step 88).

  If the PD is PoDL compliant, the classification phase is performed using the opposite polarity voltage (step 90), where the diode 76 coupling the PD classification circuit 78 to the wire pair 14 is forward biased. The UVLO circuit 84 is not triggered by the reverse polarity voltage and the detection circuit 80 is isolated from the wire pair 14.

  After the handshake phase, the PSE supplies the specified PoDL voltage on the wire pair 14 to the PD load 38 with normal voltage polarity (step 92). Therefore, the classification circuit 78 is decoupled from the wire pair 14. A detection circuit resistor or other signature generator can be decoupled from the wire pair 14 by a switch within the detection circuit, or the signature circuit can be trivial to the operation of the PD during normal operation.

  4A-4C are directed to using a voltage limiting device in the PD to convey detection and / or classification signatures. In one example, the detection and classification signal generated by PSE controller 26 may have a 10V limit. Separate detection and classification devices can be used, and the invention of FIGS. 4A-4C can be combined with the invention of the previous drawings. The voltage limiting device may provide a limited voltage of, for example, 7V to communicate both that the PD is PoDL compliant and the required operating voltage is 5V (step 94). Additional information can be conveyed by the magnitude of the limited voltage (such as maximum power level), which can be used by the PSE for budgeting purposes and to detect overload.

  In the example of FIG. 4A, the voltage limiting device is a Zener diode 96 having a threshold higher than the PD's normal PoDL operating voltage. The detector circuit 98 isolates the PD controller 28 from the zener diode 96 via the switch 100 during the detection phase, so that the detection signature is not affected by other electrical circuits in the PD (step 94).

  In step 102, the PSE 10 is activated or the PD 12 is connected to the PSE 10.

  In step 104, the PSE 10 turns on the low current source 106 and the low current source 106 applies a low current to the Zener diode 96. A diode bridge 108 can be used to ensure that the proper polarity is applied to the zener diode 96. FIG. 4B shows that the Zener diode 96 limits the resulting voltage.

  In step 110, the voltage detector 112 detects the resulting voltage limited by the zener diode 96, and the resulting voltage drop Vd is used to identify the PoDL characteristic corresponding to a particular Vd level. The voltage is applied to the controller 26 (step 112). For example, the Vd level can be digitized and a look-up table providing PoDL characteristics (such as operating voltage and maximum power level) to the PSE can be handled. Each set of PoDL characteristics can be associated with a narrow range of Vd levels, as unknown voltage drops due to resistance can exist besides wires. FIG. 4B shows that two ranges of Vd levels are associated with Type I and Type II PDs in relation to maximum power.

  After the handshake phase, when the current source 106 is disabled, the switch 100 is closed (step 114) and the PSE power supply 116 is controlled by the PSE controller 26, thereby applying the appropriate voltage to the wire pair 14 To provide.

  In step 118, after the UVLO circuit in the PD controller 28 detects an appropriate operating voltage, the UVLO circuit closes the switch 40 to power the PD load 38. At this time, the Zener diode 96 operates as an ESD protection device because its threshold is above the operating PoDL voltage.

  In some applications, the PD includes a voltage regulator because the voltage on the wire pair 14 is affected by a voltage drop in the wire loop. If the resistance of the loop is known, the voltage drop along the loop can be calculated for any current level, and the voltage supplied by the PSE supplies the PD with a precisely known voltage. Can be adjusted by the PSE to do so. This may eliminate the need for any voltage regulator in the PD or allow the use of a simple linear regulator in the PD rather than a switching regulator.

  FIG. 4D illustrates the steps that can be used in conjunction with Zener diode 96 (or other voltage limiting device) to calculate the loop resistance and expected voltage drop along the loop. All processing can be performed by the PSE controller 26 in FIG. 4A.

  In step 122 of FIG. 4D, the loop resistance test is initiated after the PSE detects the Zener diode 96 (or other voltage limiting device) during the detection phase.

  In step 124, current source 106 (FIG. 4A) applies a known low DC current I1 to wire pair 14, and the resulting measured voltage at PSE is due to voltage clamping by zener diode 96, and voltage The drop (I1xR) is due to loop resistance. The resulting voltage is V1 and is stored in memory in the PSE.

  In step 126, a known higher current I2 is provided by the current source 106 and the resulting voltage V2 across the wire pair 14 is again measured and stored in memory. Since I2 is greater than I1, there is a larger loop voltage drop, but the contribution from the Zener diode is the same. The current source 106 may comprise multiple current sources or a single current source, where the parameters are adjusted to generate multiple current levels.

  In step 128, the loop resistance R is calculated as R = (V1-V2) / (I2-I1).

  In step 130, during normal operation, the voltage drop Vd due to the loop resistance is calculated as Vd = I * R, where I is the operating current. Vd changes because the current can change during operation.

  In step 132, the PSE PoDL voltage is dynamically adjusted taking into account the voltage drop along the wire pair 14 based on the PD current so that the voltage at the PD can be adjusted to the correct voltage. This eliminates the need for a separate voltage regulator in the PD or allows the use of an effective linear regulator in the PD. The variable voltage source in the PSE can be the variable voltage converter 30 in FIG.

  5A-5C are directed to transmitting a PoDL characteristic by a PD using a surge stopper in the PD, where the magnitude of the threshold voltage of the surge stopper corresponds to the PoDL characteristic. During normal operation, the surge stopper can serve to block voltage surges to prevent damage to the PD electrical circuit. In various embodiments, the threshold voltage corresponding to a particular set of PoDL characteristics is within various ranges of threshold voltages, as there may be a small variable voltage drop along the wire pair 14 with low detection and classification currents. .

  FIG. 5A shows a simple surge stopper for each wire, with each surge stopper being formed by MOSFETs 140 and 142 in series with the associated wire. The surge voltage detector 144 (comparator and driver) detects when the voltage across the wire pair 14 exceeds a certain threshold voltage Vth (such as 10 V). The threshold is higher than the PD operating voltage. The threshold voltage level is simply set (eg, by selecting a resistor divider in series with the current source to provide the threshold voltage and then comparing the threshold voltage with the actual voltage across the wire pair 14). . When the threshold is exceeded, detector 144 applies a suitable voltage to the gates of MOSFETs 140 and 142 to provide a high impedance (step 148 in FIG. 5B).

  In step 150, first, the PSE supplies a lamp voltage to the PD during the classification phase until the surge stopper is triggered. FIG. 5C shows the high impedance that occurs at the threshold voltage Vt. Before the surge stopper starts, the PSE detects a much lower impedance than the open circuit. A high value resistor 152 across the wire pair in the PD ensures that the circuit formed by the PD is present even when the UVLO circuit keeps the switch 40 open. The timer circuit of FIG. 2A, or the voltage polarity reversal technique of FIG. 3A can be used to prevent the UVLO circuit from closing the switch 40 before receiving the normal PoDL operating voltage.

  In step 154, the PSE detects that the surge stopper has started by detecting a change in impedance. Furthermore, the level of the lamp voltage is detected and a specific level is used to cross-reference the PoDL characteristic of the PD from a lookup table in the PSE, or the level is determined by an algorithm to determine the PoDL characteristic. (Step 156). The PSE then supplies the required voltage specified by the surge stopper threshold level to the PD (step 156). Since the operating voltage for the PD is below the surge stopper threshold, the MOSFETs 140 and 142 are normally closed and the UVLO switch 40 is also closed. Since the exact threshold voltage of the surge stopper may not be known by the PSE due to the voltage drop along the wire pair 14, as shown in FIG. 5C, various possible ranges of detected threshold voltages are Used to classify PDs (such as Type I or Type II PDs), where different types are associated with maximum power levels.

  High-value resistors 158 and 160 are in series with the loop when MOSFETs 140 and 142 are opened during the classification test. In step 162, the values of these resistors 158/160 are detected, where the particular values correspond to the PDOL characteristics of the PD (such as operating voltage and maximum current / power for the PD). Therefore, by using resistors 158 and 160, the resistance value, rather than the surge stopper threshold voltage, can be used to convey the PoDL characteristic. The advantage of this technique is that the resistor 158/160 does not affect the circuit when the MOSFET 140/142 is closed during normal operation, and the surge stopper threshold is optimized for the particular application. obtain. The resistance value can be detected by measuring the resulting current at the threshold voltage, where R = Vth / I.

  6A-6C are directed to techniques that allow the PSE to know if the PD has been disconnected from the wire pair 14 following the handshake phase. This allows the PSE to know if it should stop supplying PoDL, and stores the startup routine from the PD rather than performing a full handshake routine each time the PSE starts up. It is possible to use the generated PoDL information. This saves considerable startup time.

  In FIG. 6A, a high value resistor 170 (greater than 100K ohms) traverses the wire pair 14 in the PD. This resistance value provides a “maintenance power signature” (step 174). This resistance is much higher than the 25K ohm conventional detection signature resistor used during the detection phase, and the resistor 170 remains across the wire pair 14 during normal operation of the PD. Typically, the detection signature resistor and other detection signature circuits that conduct significant current during normal operation are switched out of the circuit during normal operation.

  In step 174, a low test current is periodically provided by current source 176 even when the PD load is not conducting current after the PD is in normal operation (eg, when the PD load is in a power off state). Is done.

  In step 178, the PSE periodically tests that the PD load resistance is less than or equal to the “maintenance power signature” resistance value.

  In step 180, if the PD load resistance is less than or equal to the “maintenance power signature” resistance value, the PSE estimates that the PD was not disconnected following the last handshake routine.

In step 182, if the PD load resistance is greater than the “maintenance power signature” resistance value, the PSE assumes that the PD has been disconnected following the last handshake routine.
In response, the PSE finishes supplying power to the PD to save energy.

  In step 184, when the PSE is not supplying power to the PD during normal operation, the PSE detects a “maintenance power signature” (ie, is the PD just in a power off state but still connected)? In order to detect whether or not the PD has been removed), a low current is supplied to the wire pair 14 periodically or continuously.

  In step 186, if the PSE detects that the PD is disconnected and then connected, the PSE performs a handshake routine for PoDL. If the PSE does not detect any disconnection during the PD activation state, the PSE does not need to repeat the handshake routine, but can simply supply sufficient PoDL voltage according to the result of the previous handshake.

  FIG. 6C shows the steps that can be performed using the circuit of FIG. 6A, where the result of the previous handshake is non-volatile memory 190 for use when the PD is later restarted. Stored in.

  In step 190, the PSE performs a detection and classification routine on the PD at startup.

  In step 192, the PSE stores the resulting PoDL information in memory 190. For example, the stored data may be codes corresponding to operating voltage levels, PD maximum power, and other operating characteristics.

  In step 194, the PSE periodically performs a test (such as the maintenance power signature test described above) to determine whether the PD is still connected or activated.

  In step 196, if the PSE detects that the PD has been disconnected and then connected and activated, the PSE may assume that the PD is the same PD or a replacement PD of the same type, which is the car manufacturer. Is true in automotive applications that identify PD types. The PSE then accesses the memory 190 for classification information to provide the appropriate PoDL voltage. The data stored in memory 190 can be from an initial handshake routine or can be preloaded by the manufacturer. Alternatively, when the PSE detects that the PD has been disconnected and subsequently detects that the PD is connected, the PSE does not use the stored data in the memory 190, A full handshake routine can be performed.

  If, at step 198, the PSE detects that the sustain power signature has not been interrupted even when the PD is powered off, the PSE stores in memory 190 at startup rather than performing a handshake routine. PoDL data may be used.

  In another embodiment, the PSE may use the information in the memory 190 and still perform a shortened handshake routine to verify that the PD is PoDL compliant or other information.

  In step 200, if the application is one that limits the type of PD used (eg, in an automobile), PoDL information in memory 190 can be preloaded into memory 190 by the manufacturer, or It can be from the first launch of the system.

  FIGS. 7A and 7B are directed to a PoDL system where the primary PD load is powered from an alternative power source 210 located on the PD side, rather than powered by the PSE. This situation can occur when the PD load requires more power than can be supplied by the PSE. In such cases, there are several benefits to a PSE that is still supplying power to the front end of the PD to power the communication channel and certain functions within the PD (other than the main PD load). Using this technology, even if the alternative power source 210 is off or malfunctioning, the PD can still communicate its operating state to the PSE for maintenance and the like. In addition, the PD may even allow the PSE to power the PD load in the event of an alternative power source 210 failure.

  FIG. 7A is the same as FIG. 1 except for the addition of an alternative power source 210 coupled to the PD load 38 and the PD controller 28.

  In step 212 of FIG. 7B, an alternative power source 210 is provided. While the PSE may provide PoDL power to an Ethernet data physical (PHY) subsystem (such as an amplifier, control circuitry, etc.), the alternate power source 210 simultaneously supplies power to the main PD load.

  In step 214, if the alternative power source 210 fails or is off, the PD still communicates to the PSE because the PHY subsystem (and other required electrical circuitry) is powered by the PSE ( For example, it is possible to communicate faults). Alternatively, the PD may switch PoDL power to the PD load 38 for normal or limited operation.

  In step 216, upon PD activation, the PSE can initially power the PD via PoDL and may send configuration data to the PD before the alternative power source 210 is turned on. Is possible. The alternative power source 210 is then appropriately configured. This is particularly useful when the alternative power source is a general purpose power source and is not customized for a particular PD. For example, once the PSE detects that the PD is PoDL compliant and that the alternative power source 210 is configured to supply the required voltage, the PSE enables only the alternative power source 210. obtain.

  All the techniques described herein can be combined in various ways for a particular application.

  Some of the various technologies are particularly suited for automotive applications where the type of PSE and PD used is highly regulated, and the handshake at each startup of the PoDL system is shortened or It can be removed.

  While particular embodiments of the present invention have been shown and described, changes and modifications can be made in broader aspects of the invention without departing from the invention, and therefore the appended claims It will be apparent to those skilled in the art that all such variations and modifications within the true spirit and scope of the invention are encompassed within the scope of the invention.

Claims (9)

A power over data line (PoDL) system, the system comprising:
A power supply (PSE) coupled to a power receiving device (PD) via a wire pair, wherein a differential data signal and DC power are transmitted over the same wire pair;
A memory circuit in the PSE that stores information identifying PoDL power requirements for the PD to power the PD through the wire pair;
With
The PSE includes a PSE controller;
When the PSE is activated, the PSE controller is configured to access the information stored in the memory, and to power the PD based on the information, Configured to supply power to the wire pair by controlling the PSE;
The PSE controller, the every time PSE is started, and is configured so as not to PoDL detection and classification routines for detecting the power requirements of the PD, the system. A power over data line (PoDL) system, the system comprising:
A power supply (PSE) coupled to a power receiving device (PD) via a wire pair, wherein a differential data signal and DC power are transmitted over the same wire pair;
A memory circuit in the PSE that stores information identifying PoDL power requirements for the PD to power the PD through the wire pair;
With
The PSE includes a PSE controller;
When the PSE is activated, the PSE controller is configured to access the information stored in the memory, and to power the PD based on the information, Configured to supply power to the wire pair by controlling the PSE;
The PSE controller, the PSE is the time it is activated, is configured to perform a shortened PoDL detection and classification routines for detecting the power requirements of the PD, the system. The information stored in the memory circuit includes information obtained by a detection and classification routine that detects the power requirements of the PD and prior to the activation of the PSE. The system according to claim 1 , wherein the system is performed. The system of claim 1 or claim 2 , wherein the information is stored in the memory circuit prior to a first use of the PSE in the system. The system according to claim 1 or 2 , wherein the information in the memory circuit includes data transmitted to the PSE by the PD before activation of the PSE. A power over data line (PoDL) system, the system comprising:
A power supply (PSE) coupled to a power receiving device (PD) via a wire pair, wherein a differential data signal and DC power are transmitted over the same wire pair;
A memory circuit in the PSE that stores information identifying PoDL power requirements for the PD to power the PD through the wire pair;
A resistor in the PD coupled across the wire pair, the resistance value of the resistor corresponding to a maintenance power signature indicating that the PD is coupled to the wire pair; and
With
The PSE includes a PSE controller;
When the PSE is activated, the PSE controller is configured to access the information stored in the memory, and to power the PD based on the information, Configured to supply power to the wire pair by controlling the PSE;
The PSE controller is configured to supply a test current to the wire pair and configured to detect whether a detected resistance is less than or equal to the resistance value of the resistor. Has been
The PSE controller is configured to determine that the PD is coupled to the wire pair when a sensed resistance is approximately equal to or less than the resistance value of the resistor;
The PSE controller, is detected resistance the PD is configured to determine that it has not been coupled to the wire pair when greater than the resistance value of the resistor, the system. When the PSE controller detects that the PD is continuously coupled to the wire pair after the information is stored in the memory circuit, the PSE controller Configured to access the stored information and configured to supply power to the wire pair by controlling the PSE to power the PD based on the information. The system according to claim 6 , which is configured as follows. When the PSE controller detects that the PD is disconnected from the wire pair and then connected, the PSE controller performs a handshake routine with the PD to identify the PoDL requirement of the PD. And configured to supply power to the wire pair by controlling the PSE to power the PD based on a result of the handshake routine. The system of claim 7 . The system of claim 8 , further comprising the PSE controller configured to store a result from the handshake routine in the memory circuit.

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