JP6316585B2 - 貫通電極を有する半導体素子の製造方法 - Google Patents
貫通電極を有する半導体素子の製造方法 Download PDFInfo
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- JP6316585B2 JP6316585B2 JP2013264445A JP2013264445A JP6316585B2 JP 6316585 B2 JP6316585 B2 JP 6316585B2 JP 2013264445 A JP2013264445 A JP 2013264445A JP 2013264445 A JP2013264445 A JP 2013264445A JP 6316585 B2 JP6316585 B2 JP 6316585B2
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- insulating film
- conductive via
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- substrate
- film
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- 239000004065 semiconductor Substances 0.000 title claims description 118
- 238000004519 manufacturing process Methods 0.000 title claims description 50
- 239000000758 substrate Substances 0.000 claims description 91
- 238000000034 method Methods 0.000 claims description 29
- 238000005530 etching Methods 0.000 claims description 27
- 238000000059 patterning Methods 0.000 claims description 13
- 230000009471 action Effects 0.000 claims description 2
- 229910052751 metal Inorganic materials 0.000 description 32
- 239000002184 metal Substances 0.000 description 31
- 239000011229 interlayer Substances 0.000 description 21
- 239000000126 substance Substances 0.000 description 19
- 230000008569 process Effects 0.000 description 16
- 239000010410 layer Substances 0.000 description 14
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 12
- 238000005498 polishing Methods 0.000 description 11
- 230000015572 biosynthetic process Effects 0.000 description 9
- 239000010949 copper Substances 0.000 description 9
- 238000007517 polishing process Methods 0.000 description 9
- 239000010931 gold Substances 0.000 description 8
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 7
- 229910052802 copper Inorganic materials 0.000 description 7
- 230000010365 information processing Effects 0.000 description 7
- 229910000679 solder Inorganic materials 0.000 description 7
- 229910052581 Si3N4 Inorganic materials 0.000 description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 238000000151 deposition Methods 0.000 description 6
- 230000004048 modification Effects 0.000 description 6
- 238000012986 modification Methods 0.000 description 6
- 238000007747 plating Methods 0.000 description 6
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 6
- 229910052814 silicon oxide Inorganic materials 0.000 description 6
- 238000009413 insulation Methods 0.000 description 5
- 230000004888 barrier function Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 4
- 229910052737 gold Inorganic materials 0.000 description 4
- 229910052759 nickel Inorganic materials 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 238000009713 electroplating Methods 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 2
- 239000002313 adhesive film Substances 0.000 description 2
- 239000011651 chromium Substances 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 238000000465 moulding Methods 0.000 description 2
- 239000002245 particle Substances 0.000 description 2
- 230000000149 penetrating effect Effects 0.000 description 2
- 229910052697 platinum Inorganic materials 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 239000004332 silver Substances 0.000 description 2
- 239000002356 single layer Substances 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- 238000004380 ashing Methods 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000005553 drilling Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 239000002002 slurry Substances 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 230000009466 transformation Effects 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
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- H01L25/0657—Stacked arrangements of devices
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/08—Address circuits; Decoders; Word-line control circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
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- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
- H01L2225/06565—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices having the same size and there being no auxiliary carrier between the devices
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- H01L24/10—Bump connectors ; Manufacturing methods related thereto
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Description
前記下部絶縁膜のうち少なくとも一部を除去して前記下部絶縁膜内に前記リセスをさらに形成することをさらに含む。
前記基板の第1面上では第1厚さを有する前記マスク膜の第1部分を提供し、そして前記伝導性ビアの第1端部上では第2厚さを有する前記マスク膜の第2部分を提供することを含み、前記第1厚さは、前記第2厚さに比べて大きくなり得る。
本発明と従来技術と比較した長所は添付図面を参照した詳細な説明と特許請求の範囲を通じて明確になり得る。特に、本発明は特許請求の範囲で明確に請求される。しかし、本発明は添付された図面と関連して次の詳細な説明を参照することによって最も良く理解される。図面において、同一の参照符号は多様な図面を通じて同一の構成要素を示す。
図1は本発明の一実施形態による半導体素子を示した断面図である。
図1を参照すれば、半導体素子1は基板100を垂直方向に貫通して電気的な信号を伝達する電気的な連結部10を含む。電気的な連結部10は貫通電極120を含む。一例によれば、貫通電極120は基板100が伸張する水平方向に対して実質的に垂直方向に伸張される。貫通電極120と基板100との間にはビア絶縁膜110が提供される。ビア絶縁膜110によって貫通電極120と基板100とは電気的に絶縁される。貫通電極120とビア絶縁膜110との間に貫通電極120の構成成分(例:銅)が基板100に拡散することを阻止するバリアー膜124がさらに提供される。
図2Aは本発明の一実施形態による半導体素子において、電気的な連結部の一例を示した断面図である。図2B及び図2Cは本発明の一実施形態による半導体素子において、整列キーの変形例を示した断面図である。図2Dは本発明の一実施形態による半導体素子において、整列キーの多様なディメンションを示した断面図である。
図3A及び図3Bは本発明の他の実施形態による半導体素子において、電気的な連結部の他の例を示した断面図である。以下では図2Aと異なる点について詳細に説明し、同一の点に対しては省略する。
図4Aは本発明の一実施形態による半導体素子をパッケイジングした半導体パッケージを示した断面図である。図4Bは図4Aの変形形態を示した断面図である。
図5A乃至図5Pは本発明の一実施形態による半導体素子の製造方法を示した断面図である。
図6A乃至図6Cは本発明の他の実施形態による半導体素子の製造方法を示した断面図である。
図7A乃至図7Cは本発明のその他の実施形態による半導体素子の製造方法を示した断面図である。
図8Aは本発明の実施形態による半導体素子を具備するメモリカードを示したブロック図である。図8Bは本発明の実施形態による半導体素子を応用した情報処理システムを示したブロック図である。
10、11、12、13 電気的な連結部
100 基板
101 ビアホール
102 層間絶縁膜
103 集積回路
104 第1層間絶縁膜
106 第2層間絶縁膜
107 上部絶縁膜
108 第1下部絶縁膜
109 第2下部絶縁膜
109f キャッピング部
110 ビア絶縁膜
111 下部絶縁膜
118 下部端子
119 鍍金膜
120 貫通電極
124 バリアー膜
152 金属配線
154 ボンディングパッド
160 整列キー
170 アンダーバンプ金属膜
190 突出部
198 上部端子
Claims (14)
- 基板を貫通して垂直方向に延長され、前記基板の第1面を通過するように延長されて前記基板の第1面に対して前記垂直方向に突出された第1端部を有する導電性ビアを形成する工程と、
前記導電性ビアの第1端部及び前記基板の第1面上に絶縁膜を形成する工程と、
前記絶縁膜上にマスク膜を形成し、前記マスク膜をパターニングして前記導電性ビアから離隔された前記導電性ビアの側面に開口部を有するマスク膜パターンを形成する工程と、
前記マスク膜パターンの上部を除去して前記導電性ビアの第1端部上に形成された前記絶縁膜のキャッピング部を露出させる工程と、
前記マスク膜パターンをエッチングマスクとして利用して、前記導電性ビアと離隔されて前記導電性ビアの側面に形成された前記絶縁膜の一部を前記導電性ビアの第1端部上に形成された前記絶縁膜のキャッピング部と同時に除去して、前記絶縁膜内にリセスを形成する工程と、を有することを特徴とする半導体素子の製造方法。 - 前記マスク膜パターンをエッチングマスクとして利用して、前記導電性ビアと離隔されて前記導電性ビアの側面に形成された前記絶縁膜の一部を前記導電性ビアの第1端部上に形成された前記絶縁膜のキャッピング部と同時に除去した後に、前記導電性ビアを平坦化する工程を更に含むことを特徴とする請求項1に記載の半導体素子の製造方法。
- 前記導電性ビアを平坦化する工程において、前記絶縁膜の一部が除去されて形成される整列キーの開口部の角部がラウンド形状の断面プロフィールに形成されることを特徴とする請求項2に記載の半導体素子の製造方法。
- 前記マスク膜パターンをエッチングマスクとして利用して、前記導電性ビアと離隔されて前記導電性ビアの側面に形成された前記絶縁膜の一部を前記導電性ビアの第1端部上に形成された前記絶縁膜のキャッピング部と同時に除去する前に、前記マスク膜パターンのうちの少なくとも上部を除去する工程を更に含むことを特徴とする請求項1に記載の半導体素子の製造方法。
- 前記マスク膜パターンをエッチングマスクとして利用して、前記導電性ビアと離隔されて前記導電性ビアの側面に形成された前記絶縁膜の一部を前記導電性ビアの第1端部上に形成された前記絶縁膜のキャッピング部と同時に除去した後に、前記マスク膜パターンを除去する工程を更に含むことを特徴とする請求項1に記載の半導体素子の製造方法。
- 前記絶縁膜を形成する工程は、
前記導電性ビアの第1端部及び前記基板の第1面上に下部絶縁膜を形成する工程と、
前記下部絶縁膜上に前記下部絶縁膜に対してエッチング作用選択性を有する上部絶縁膜を形成する工程と、を含み、
前記絶縁膜の一部を除去する工程は、前記上部絶縁膜のうちの少なくとも一部を除去して前記上部絶縁膜内に前記リセスを形成する工程を含むことを特徴とする請求項1に記載の半導体素子の製造方法。 - 前記絶縁膜の一部を除去する工程は、前記下部絶縁膜のうちの少なくとも一部を除去して前記下部絶縁膜内に前記リセスを形成する工程を含むことを特徴とする請求項6に記載の半導体素子の製造方法。
- 前記絶縁膜上にマスク膜を形成する工程は、前記基板の第1面上で第1厚さを有する前記マスク膜の第1部分を形成し、前記導電性ビアの第1端部上で第2厚さを有する前記マスク膜の第2部分を形成する工程を含み、
前記第1厚さは、前記第2厚さに比べて大きいことを特徴とする請求項1に記載の半導体素子の製造方法。 - 前記絶縁膜上にマスク膜を形成する工程は、平坦な上面を有する前記マスク膜を形成する工程を含むことを特徴とする請求項8に記載の半導体素子の製造方法。
- 前記マスク膜の第1部分は、前記基板の前記第1面に対して第1高さを有する上面を含み、
前記導電性ビアの第1端部上に形成された前記絶縁膜は、前記基板の前記第1面に対して第2高さを有する上面を含み、
前記第1高さは、前記第2高さに比べて小さいことを特徴とする請求項8に記載の半導体素子の製造方法。 - 前記マスク膜の第1部分は、前記基板の上面に対して第1高さを有する上面を含み、
前記絶縁膜のキャッピング部は、前記基板の上面に対して第2高さを有する上面を含み、
前記第1高さは、前記第2高さに比べて大きいことを特徴とする請求項8に記載の半導体素子の製造方法。 - 前記マスク膜パターンの上部を更に除去してリセスされたマスク膜パターンを形成する工程と、
前記リセスされたマスク膜パターンをエッチングマスクとして利用して、前記導電性ビアと離隔されて前記導電性ビアの側面に形成された前記絶縁膜の一部を除去する工程と、を更に含むことを特徴とする請求項1に記載の半導体素子の製造方法。 - 前記マスク膜をパターニングしてマスク膜パターンを形成する工程は、
光エネルギーによって完全露光された第1露光領域と光エネルギーによって部分露光された第2露光領域とを形成する工程と、
前記第1露光領域を除去して前記リセスに対応する前記絶縁膜の一部を露出させる開口部を形成する工程と、
前記第2露光領域を除去して前記キャッピング部に対応する前記絶縁膜の一部を露出させる開口部を形成する工程と、を含むことを特徴とする請求項1に記載の半導体素子の製造方法。 - 基板を貫通して垂直方向に延長され、前記基板の第1面を通過するように延長されて前記基板の第1面に対して前記垂直方向に突出された第1端部を有する導電性ビアを形成する工程と、
前記導電性ビアの第1端部及び前記基板の第1面上に絶縁膜を形成する工程と、
前記絶縁膜上にマスク膜を形成し、前記マスク膜をパターニングして前記導電性ビアから離隔された前記導電性ビアの側面に開口部を有するマスク膜パターンを形成する工程と、
前記マスク膜パターンの上部を除去して前記導電性ビアの第1端部上に形成された前記絶縁膜のキャッピング部を露出させる工程と、
前記マスク膜パターンをエッチングマスクとして利用して、前記導電性ビアと離隔されて前記導電性ビアの側面に形成された前記絶縁膜の一部を除去して前記絶縁膜内に整列キー開口部を形成し、前記整列キーを形成した後に前記導電性ビアの第1端部を平坦化する工程と、を有し、
前記マスク膜パターンをエッチングマスクとして利用して、前記導電性ビアと離隔されて前記導電性ビアの側面に形成された前記絶縁膜の一部を除去して前記絶縁膜内に整列キー開口部を形成する工程は、前記導電性ビアの第1端部上に形成された前記絶縁膜のキャッピング部を除去する工程と共に進行されることを特徴とする半導体素子の製造方法。
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-
2012
- 2012-12-20 KR KR1020120149598A patent/KR102018885B1/ko active IP Right Grant
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2013
- 2013-12-17 US US14/108,771 patent/US9070748B2/en active Active
- 2013-12-20 JP JP2013264445A patent/JP6316585B2/ja active Active
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- 2015-05-12 US US14/709,840 patent/US20150243637A1/en not_active Abandoned
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JP2014123740A (ja) | 2014-07-03 |
US20140179103A1 (en) | 2014-06-26 |
KR102018885B1 (ko) | 2019-09-05 |
US9070748B2 (en) | 2015-06-30 |
KR20140080132A (ko) | 2014-06-30 |
US20150243637A1 (en) | 2015-08-27 |
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