JP6302960B2 - Multilayer capacitor and manufacturing method thereof - Google Patents

Description

  The present invention relates to a multilayer capacitor capable of adjusting an equivalent series resistance (ESR).

  A multilayer ceramic capacitor typically includes a multilayer body and a pair of external electrodes. The multilayer body is composed of a rectangular parallelepiped ceramic chip having a structure in which a plurality of internal electrode layers are stacked via a dielectric layer, and ends of each internal electrode layer are alternately exposed on both end faces in the length direction. The The pair of external electrodes are formed on the both end surfaces of the laminate so as to be electrically connected to the exposed end portions of the internal electrode layer (see, for example, Patent Document 1 below).

  On the other hand, a multilayer capacitor capable of realizing a predetermined equivalent series resistance (ESR) is known for the purpose of improving characteristics of an electric circuit. For example, in Patent Document 2 below, a laminate in which a dielectric layer and a different polarity internal conductor layer are laminated in a predetermined order, and a different polarity external electrode connected to the internal conductor layer and provided on the surface of the laminate, A multilayer capacitor is described that includes a connecting electrode of a different polarity that is connected to the inner conductor layer and provided on the surface of the multilayer body. In this multilayer capacitor, the equivalent series resistance can be set based on the resistivity of the connection electrode having the different polarity.

Japanese Unexamined Patent Publication No. 2011-3848 JP 2007-335754 A

  However, since the multilayer capacitor described in Patent Document 2 sets the ESR based on the resistivity of the electrode material, it is difficult to select an electrode material having both good electrical characteristics and a desired resistivity. In some cases, ESR cannot be set with a high degree of freedom.

  In view of the circumstances as described above, an object of the present invention is to provide a multilayer capacitor having a high degree of freedom in setting ESR.

In order to achieve the above object, a multilayer capacitor according to an embodiment of the present invention includes a multilayer body, a first external electrode, a second external electrode, and a resistance adjusting unit.
The laminate is formed in a rectangular parallelepiped shape having a first terminal surface and a second terminal surface facing each other in the first axial direction. The stacked body includes a first internal electrode, a second internal electrode, and a dielectric layer. The first internal electrode has a first extraction end exposed from the first terminal surface. The second internal electrode has a second lead end that is opposed to the first internal electrode in a second axial direction perpendicular to the first axial direction and is exposed from the second terminal surface. . The dielectric layer is disposed between the first internal electrode and the second internal electrode.
The first external electrode has a first conductor portion that is disposed on the first terminal surface and is electrically connected to the first lead-out end portion.
The second external electrode includes a second conductor portion that is disposed on the second terminal surface and is electrically connected to the second lead-out end portion.
The resistance adjusting unit includes a first insulating layer and a second insulating layer. The first insulating layer is disposed on the first terminal surface and limits a connection width of the first conductor portion with respect to the first lead-out end portion. The second insulating layer is disposed on the second terminal surface and limits a connection width of the second conductor portion with respect to the second lead-out end portion.

The first insulating layer is a pair of first terminal coating layers facing each other via a first gap in a third axial direction orthogonal to the first axial direction and the second axial direction, respectively. Have
The second insulating layer has a pair of second terminal coating layers facing each other with a second gap in the third axial direction.
The first extraction end and the second extraction end are connected to the first conductor portion and the second conductor portion via the first gap and the second gap, respectively.
The stacked body further includes a first side surface and a second side surface facing each other in the third axial direction.
The resistance adjusting unit further includes a pair of insulating coating layers formed on the first side surface and the second side surface, respectively, for connecting the first insulating layer and the second insulating layer to each other.
The width dimension along the third axial direction of each of the pair of first terminal coating layers, the width dimension along the third axial direction of each of the pair of second terminal coating layers, and the first At least one of the width dimensions along the third axial direction of each of the one gap and the second gap is different from each other.

1 is an overall perspective view schematically showing a multilayer capacitor according to a first embodiment of the present invention. It is a whole perspective view which shows schematically the laminated body which comprises the said multilayer capacitor. It is the longitudinal cross-sectional view seen from the width direction of the said multilayer capacitor. It is the longitudinal cross-sectional view seen from the length direction of the said multilayer capacitor. It is a disassembled perspective view of the said laminated body. It is a perspective view which shows the relationship between the said laminated body and a resistance adjustment part. It is the cross-sectional view seen from the height direction of the said multilayer capacitor. It is process drawing explaining the manufacturing process of the said resistance adjustment part. It is a top view of the principal part explaining the structural example of the said resistance adjustment part. It is a whole perspective view showing roughly the multilayer capacitor concerning a 2nd embodiment of the present invention. It is a whole perspective view showing roughly the multilayer capacitor concerning the 3rd embodiment of the present invention. It is a whole perspective view showing roughly the multilayer capacitor concerning a 4th embodiment of the present invention. It is a disassembled perspective view which shows the modification of a structure of the said laminated body. It is a front view which shows the form of the said resistance adjustment part, (A) shows the form of the terminal coating layer which has an opening part in the center part of a terminal surface, (B) is one side surface with respect to the center part of a terminal surface. The form of the terminal coating layer which has an opening part in the position biased to the side is shown.

A multilayer capacitor according to an embodiment of the present invention includes a multilayer body, a first external electrode, a second external electrode, and a resistance adjusting unit.
The laminate is formed in a rectangular parallelepiped shape having a first terminal surface and a second terminal surface facing each other in the first axial direction. The stacked body includes a first internal electrode, a second internal electrode, and a dielectric layer. The first internal electrode has a first extraction end exposed from the first terminal surface. The second internal electrode has a second lead end that is opposed to the first internal electrode in a second axial direction perpendicular to the first axial direction and is exposed from the second terminal surface. . The dielectric layer is disposed between the first internal electrode and the second internal electrode.
The first external electrode has a first conductor portion that is disposed on the first terminal surface and is electrically connected to the first lead-out end portion.
The second external electrode includes a second conductor portion that is disposed on the second terminal surface and is electrically connected to the second lead-out end portion.
The resistance adjusting unit includes a first insulating layer and a second insulating layer. The first insulating layer is disposed on the first terminal surface and limits a connection width of the first conductor portion with respect to the first lead-out end portion. The second insulating layer is disposed on the second terminal surface and limits a connection width of the second conductor portion with respect to the second lead-out end portion.

  The multilayer capacitor includes a resistance adjustment unit that limits a connection width between the first internal electrode and the first external electrode and a connection width between the second internal electrode and the second external electrode, respectively. Therefore, the equivalent series resistance (hereinafter also referred to as ESR) can be arbitrarily adjusted depending on the size of each connection width. That is, according to the multilayer capacitor, ESR can be adjusted with a high degree of freedom, and desired ESR can be realized with high accuracy.

  The connection width is typically the connection length along the width direction of the lead-out end portion of the internal electrode exposed from the terminal surface of the laminate, and is the connection length along the thickness direction of the lead-out end portion. Also good. In any case, since the cross-sectional area of the connection portion between the internal electrode and the external electrode can be limited, the ESR can be adjusted.

  The first internal electrode and the second internal electrode are each typically composed of a plurality of electrode layers. In this case, between each of the plurality of first internal electrode layers, each of the plurality of second internal electrode layers is disposed to face each other via a dielectric layer. Thereby, a large-capacity multilayer capacitor can be easily configured.

The first and second insulating layers each have an opening having a length direction in the second axial direction and a width direction in a third axial direction orthogonal to the first and second axial directions. May be. In this case, the first and second lead end portions are connected to the first and second conductor portions through the opening, respectively.
Thus, by adjusting the width of the opening, it is possible to connect the first and second conductor portions and the first and second lead end portions with a desired connection width.

The stacked body may further include first and second side surfaces facing each other in the third axial direction. The resistance adjusting unit may further include a pair of insulating coating layers that are formed on the first and second side surfaces, respectively, and connect the first insulating layer and the second insulating layer to each other. .
The insulating coating layer constitutes a side margin layer of the stacked body, thereby improving the withstand voltage of the stacked body.

The resistance adjusting unit may be made of a ceramic material.
Thereby, a resistance adjustment part can be formed appropriately, suppressing generation | occurrence | production of the delamination and crack of a laminated body.

The pair of external electrodes may further include a conductive coating layer that covers the first and second terminal surfaces from above the first and second insulating layers, respectively.
As a result, the adhesion of the external electrode is increased and the mounting reliability of the multilayer capacitor can be ensured.

A method of manufacturing a multilayer capacitor according to an embodiment of the present invention includes producing a rectangular parallelepiped multilayer body.
The laminated body includes a first internal electrode having one end exposed from the first terminal surface, and a second terminal exposed from the second terminal surface facing the first terminal surface in the first axial direction. The internal electrodes are produced by alternately laminating them in a second axial direction orthogonal to the first axial direction via a dielectric layer.
A first insulating layer having a first opening for limiting the width of the first internal electrode exposed from the first terminal surface is formed on the first terminal surface. A second insulating layer having a second opening for limiting the width of the second internal electrode exposed from the second terminal surface is formed on the second terminal surface.
A first external electrode electrically connected to the first internal electrode through the first opening is formed on the first terminal surface, and the second external electrode through the second opening. A second external electrode electrically connected to the internal electrode is formed on the second terminal surface.

  In the multilayer capacitor manufacturing method, the first and second insulating layers that limit the widths of the first and second internal electrodes exposed from the first and second terminal surfaces, respectively, Each is formed on the terminal surface. Thereby, the multilayer capacitor which can adjust an equivalent series resistance (ESR) to arbitrary values can be manufactured.

The step of forming the first and second insulating layers includes the step of forming the laminated body into a bath of an insulating paste material along a third axial direction orthogonal to the first and second axial directions, respectively. It is also possible to include a dipping process on both sides.
Thereby, the first and second insulating layers having a desired opening width can be easily formed on the first and second terminal surfaces.

The immersion depth of the laminate in the bath can be less than ½ of the width dimension along the third axial direction of the laminate.
Thereby, the 1st and 2nd insulating layer which has a desired opening width in the center part of the 1st and 2nd terminal surface can be formed in the 1st and 2nd terminal surface, respectively.

Or the immersion depth of the said laminated body in the said bath may mutually differ in the both sides | surfaces of the said laminated body.
In this case, the first and second openings for limiting the widths of the first and second internal electrodes are located at positions deviated to one side of the center of the first and second terminal surfaces. Each is formed.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

<First Embodiment>
[Overall structure of multilayer capacitor]
FIG. 1 is an overall perspective view schematically showing a multilayer capacitor according to an embodiment of the present invention. In the figure, the X, Y and Z axes indicate the three axial directions orthogonal to each other. In this embodiment, the X axis direction is the length direction of the multilayer capacitor, the Y axis direction is the width direction, and the Z axis direction Corresponds to the height direction.

  The multilayer capacitor 10 of this embodiment includes a multilayer body 11, a pair of external electrodes 12 a and 12 b, and a resistance adjustment unit 13.

  As will be described later, the multilayer body 11 is constituted by a substantially rectangular parallelepiped ceramic component in which internal electrodes and dielectric layers are alternately laminated in the Z-axis direction. The pair of external electrodes 12 a and 12 b are respectively formed on two terminal surfaces facing each other in the X-axis direction of the multilayer body 11, and are electrically connected to the internal electrodes of the multilayer body 11. The resistance adjusting unit 13 has a function of limiting the connection width between the internal electrode and the external electrodes 12a and 12b.

  Details of each part of the multilayer capacitor 10 will be described below.

(Laminate)
2 is an overall perspective view schematically showing the multilayer body 11, FIG. 3 is a longitudinal sectional view of the multilayer capacitor 10 showing the cross-sectional structure of the multilayer body 11 as seen from the Y-axis direction, and FIG. 4 is a multilayer view as seen from the X-axis direction. FIG. 5 is an exploded perspective view schematically showing the structure of the multilayer body 11.

  The stacked body 11 includes first and second main surfaces M1 and M2 that face each other in the Z-axis direction (height direction) and first and second faces that face each other in the X-axis direction (length direction). It is constituted by a rectangular parallelepiped (hexahedron) having terminal surfaces T1, T2 and first and second side surfaces S1, S2 facing each other in the Y-axis direction (width direction). The laminated body 11 has an internal structure in which a first internal electrode layer 111 and a second internal electrode layer 112 are arranged so as to face each other with a dielectric layer 110 therebetween as shown in FIGS. Have.

  As shown in FIG. 5, the stacked body 11 is produced by alternately stacking a plurality of first sheet materials 11 a and a plurality of second sheet materials 11 b in the Z-axis direction. The first sheet material 11a is composed of a rectangular ceramic sheet in which a first internal electrode layer 111 is formed on a dielectric sheet 110s. The second sheet material 11b is composed of a rectangular ceramic sheet in which the second internal electrode layer 112 is formed on the dielectric sheet 110s, and has the same shape and size as the first sheet material 11a. ing.

The dielectric sheet 110s is formed mainly of a ferroelectric powder such as barium titanate (BaTiO ₃ ), calcium titanate (CaTiO ₃ ), strontium titanate (SrTiO ₃ ), calcium zirconate (CaZrO ₃ ), for example. It is composed of a sintered body of a rectangular green sheet. The first and second internal electrode layers 111 and 112 are formed of a rectangular metal thin film having a width W1 obtained by sintering a conductive paste containing a base metal powder such as Ni or Cu.

  Both main surfaces M1 and M2 of the laminated body 11 are composed of a plurality of dielectric sheets 110s laminated respectively on the uppermost second sheet material 11b and the lowermost first sheet material 11a. One end 111a (first lead end) of the first internal electrode layer 111 is drawn to one end of the dielectric sheet 110s, and one end 112a (second lead end) of the second internal electrode layer 112 is drawn. ) Is pulled out to the other end side of the dielectric sheet 110s. As a result, the lead end 111a of the first internal electrode layer 111 is exposed from the first terminal surface T1 of the multilayer body 11, and the lead end 112a of the second internal electrode layer 111 is exposed from the second terminal surface T2. Is exposed.

  The thickness of the dielectric sheet 110s, the thicknesses of the first and second internal electrode layers 111 and 112, and the like are appropriately set according to the specifications of the multilayer capacitor 10. In the present embodiment, each of the first and second internal electrodes includes a plurality of internal electrode layers 111 and 112, and the dielectric layer 110 is interposed between each of the plurality of first internal electrode layers 111. Thus, each of the plurality of second internal electrode layers 112 is disposed to face each other. Thereby, the large capacity multilayer capacitor 10 can be easily configured. The number of layers of the first and second internal electrode layers 111 and 112 is not limited to the example shown in the figure, and may be composed of several tens of layers or more.

(Resistance adjustment unit)
FIG. 6 is a perspective view showing the resistance adjusting unit 13 formed in the stacked body 11. The resistance adjustment unit 13 includes a first adjustment layer 13a formed on the first side surface S1 of the multilayer body 11 and a second adjustment layer 13b formed on the second side surface S2 of the multilayer body 11.

  Each adjustment layer 13a, 13b is made of an insulating ceramic material. Each adjustment layer 13a, 13b is made of the same kind of material as that of the dielectric layer 110 constituting the multilayer body 11 (for example, barium titanate ceramic material), so that the delamination of the multilayer body 11 due to mismatching of thermal expansion coefficients. Lamination and cracking can be suppressed. In addition, the adjustment layers 13a and 13b can be appropriately formed.

  In the present embodiment, the first and second adjustment layers 13a and 13b include the first and second side margin layers 130a and 130b (insulating coating layers) and the first terminal coating layers 131a and 131b (first coating layers). Insulating layer) and second terminal covering layers 132a and 132b (second insulating layer).

  As shown in FIG. 6, the first terminal covering layers 131a and 131b are respectively arranged on the first terminal surface T1 of the multilayer body 11, and a gap G1 having a width W2 at the center in the width direction of the first terminal surface T1. Are opposed to each other in the Y-axis direction. The region on the first terminal surface T1 excluding the formation region of the gap G1 is covered with the first terminal coating layers 131a and 131b.

  Similarly, the second terminal covering layers 132a and 132b are arranged on the second terminal surface T2 of the multilayer body 11, respectively, and the second terminal coating layers 132a and 132b are Y through the gap G2 having the width W2 at the center in the width direction of the second terminal surface T2. They are opposed to each other in the axial direction. The region on the second terminal surface T2 excluding the formation region of the gap G2 is covered with the second terminal coating layers 132a and 132b.

  The first and second side margin layers 130a and 130b are formed by replacing the first terminal coating layers 131a and 131b and the second terminal coating layers 132a and 132b with the first and second side surfaces S1 and S2, and the first and first side coating layers 131a and 131b. It arrange | positions at 1st and 2nd side surface S1, S2, and 1st and 2nd main surface M1, M2 of the laminated body 11, respectively so that it may mutually connect via 2 main surface M1, M2. The entire area of the first and second side surfaces S1, S2 is covered with the first and second side margin layers 130a, 130b, respectively, and the side margin layers 130a, 130b are in the Y-axis direction on the main surfaces M1, M2. Are opposed to each other through a gap having a width W2.

  Each gap G1, G2 corresponds to an “opening” that exposes the first and second terminal surfaces T1, T2 through the first and second terminal coating layers 131a, 131b, 132a, 132b, respectively. The end portions Ga of the first and second terminal coating layers 131a, 131b, 132a, and 132b that form the edge of the opening are each formed in a curved shape. Thereby, each gap | interval G1, G2 is formed so that opening width may spread outward from terminal surface T1, T2.

  The first and second terminal coating layers 131a, 131b, 132a, 132b mainly have a function of limiting the connection width between the multilayer body 11 and the external electrodes 12a, 12b, and the first and second side margin layers. 130 a and 130 b mainly have a function of improving the withstand voltage of the multilayer capacitor 10. The terminal covering layers 131a, 131b, 132a, 132b and the side margin layers 130a, 130b are respectively formed with a sufficient thickness to ensure the desired withstand voltage.

(External electrode)
The external electrodes 12a and 12b are respectively disposed on the first and second terminal surfaces T1 and T2 of the multilayer body 11 via the first and second terminal coating layers 131a, 131b, 132a, and 132b. The external electrodes 12a and 12b are formed of the same material as the first and second internal electrode layers 111 and 112, and are formed of a base metal material such as Ni, for example. The surface of the external electrodes 12a and 12b may be subjected to solder plating in order to improve solder wettability when mounted on the circuit board.

  FIG. 7 is a cross-sectional view of the multilayer capacitor 10 showing a connection state between the external electrodes 12a and 12b and the internal electrode layers 111 and 112. FIG. Hereinafter, the details of the external electrodes 12a and 12b will be described with reference to FIGS.

  The first external electrode 12a includes a first conductive portion 121a that is electrically connected to the leading end portions 111a of the plurality of first internal electrode layers 111, and a first conductive layer that covers the first terminal surface T1. And a covering layer 122a.

  As shown in FIG. 7, the first conductor portion 121a includes a first internal electrode layer 111 in which the exposed width from the first terminal surface T1 is limited to W1 to W2 by the first terminal coating layers 131a and 131b. Connected to the leading end 111a. The connection width between the first conductor portion 121a and the lead end portion 111a determines the electrical resistance of the connection point between the external electrode 12a and the first internal electrode layer 111, and the cross-sectional area of the connection point decreases as the connection width decreases. The electrical resistance increases because of the decrease. Therefore, the connection resistance between the first external electrode 12a and the first internal electrode layer 111 can be adjusted depending on the size of the gap W2.

  As shown in FIGS. 3 and 7, the first conductive coating layer 122a is formed on the first terminal surface T1 so as to cover the first terminal surface T1 from above the first terminal coating layers 131a and 131b. It is formed around. The first conductive coating layer 122a is integrally connected to the first conductor portion 121a, and the main surfaces M1, M2 and each of the multilayer body 11 from above the first and second side margin layers 130a, 130b. It is formed so as to cover part of the side surfaces S1, S2.

  Similarly, in the second external electrode 12b, the second conductor portion 121b electrically connected to the lead-out end portions 112a of the plurality of second internal electrode layers 112 and the second terminal surface T2 are covered. Conductive coating layer 122b. The 2nd conductor part 121b and the 2nd conductive coating layer 122b are constituted similarly to the above-mentioned 1st conductor part 121a and the 1st conductive coating layer 122a.

  The second conductor portion 121b is also formed on the lead-out end portion 112a of the second internal electrode layer 112 whose exposure width from the second terminal surface T2 is limited to W2 from W2 by the second terminal coating layers 132a and 132b. Connected. Therefore, the connection resistance between the second external electrode 12b and the second internal electrode layer 112 is adjusted according to the size of the gap W2.

  In this embodiment, the gap (opening) between the first terminal coating layers 131a and 131b and the gap (opening) between the second terminal coating layers 132a and 132b are formed with the same width (W2). Thereby, the equivalent series resistance (ESR) when viewed from the input side and the output side of the multilayer capacitor 10 can be made the same. However, the present invention is not limited to this, and the gap between the first terminal coating layers 131a and 131b and the gap between the second terminal coating layers 132a and 132b may be formed with different widths according to the specifications of the circuit design.

[Operation of multilayer capacitor]
The multilayer capacitor 10 of the present embodiment configured as described above constitutes a capacitance element having a predetermined capacity by soldering the first and second external electrodes 12a and 12b to the connection lands on the circuit board. To do.

  In the present embodiment, since the external electrodes 12a and 12b also cover a part of each of the main surfaces M1 and M2 and the side surfaces S1 and S2, the multilayer capacitor 10 can be mounted regardless of the mounting direction. Mounting efficiency increases. Further, since the external electrodes 12a and 12b protrude outward from the main surfaces M1 and M2 of the multilayer body 11, the multilayer body 11 does not come into contact with the circuit board at the time of mounting, so that the mounting reliability can be improved. .

  According to the multilayer capacitor 10 of the present embodiment, the connection width between the first internal electrode layer 111 and the first external electrode 12a, and the connection between the second internal electrode layer 112 and the second external electrode 12b. Since the resistance adjustment unit 13 that restricts the connection width between them is provided, the equivalent series resistance (hereinafter also referred to as ESR) can be arbitrarily adjusted according to the size of each connection width.

  That is, according to the multilayer capacitor 10 of the present embodiment, ESR can be adjusted with a high degree of freedom, and an ESR value corresponding to the size of the connection width between the electrodes can be obtained. Can be adjusted.

  Furthermore, according to the present embodiment, the resistance adjusting unit 13 includes the side margin layers 130a and 130b that cover the side surfaces S1 and S2 of the multilayer body 11, so that the withstand voltage of the multilayer body 11 is improved, and thus the multilayer capacitor 10 reliability can be improved.

[Manufacturing method of multilayer capacitor]
The present embodiment includes a manufacturing process of the stacked body 11, a forming process of the resistance adjusting unit 13, and a forming process of the external electrodes 12a and 12b. In addition, the following description is an example and description of a manufacturing method is not restricted to the following description.

(Laminate manufacturing process)
As shown in FIG. 5, after a predetermined number of sheet materials 11a and 11b on which the printing patterns of the internal electrode layers 111 and 112 are printed are alternately stacked on the surface of the green sheet constituting the dielectric sheet 110s, They are laminated and integrated by the press method. After lamination, the laminate 11 shown in FIG. 2 is produced by cutting into a predetermined size.

(Formation process of resistance adjustment part)
Subsequently, the first and second adjustment layers 13a and 13b are formed on the stacked body 11, respectively. Although the formation method of each adjustment layer 13a, 13b is not specifically limited, In this embodiment, the method of forming adjustment layer 13a, 13b by the immersion method is demonstrated.

  FIG. 8 is a process diagram showing a process of forming the adjustment layers 13a and 13b.

  First, as shown in FIGS. 8A and 8B, one side surface S1 of the laminate 11 is directed downward, and the laminate 11 is immersed in a bath of a paste material P of insulating ceramic along the width direction thereof. . Next, as shown in FIGS. 8C, 8 </ b> D, and 8 </ b> E, the other side surface S <b> 2 of the laminate is directed downward, and the laminate 11 is immersed in the paste material P bath along its width direction. . Thereafter, the adjustment layers 13a and 13b are formed through drying of the paste material P adhered to the laminate 11, binder removal processing, and the like. The binder removal process for the paste material P may also serve as the binder removal process for the stacked body 11.

  As described above, the adjustment layers 13a and 13b having the side margin layers 130a and 130b and the terminal covering layers 131a, 132a, 131b, and 132b are formed. According to this embodiment, since each adjustment layer 13a, 13b can be formed by a single dipping process, there is an advantage of excellent work efficiency.

  Further, the amount of paste material P immersed in the bath corresponds to the formation width of each terminal coating layer 131a, 132a, 131b, 132b. For this reason, the gap width Wa between the adjustment layers 13a and 13b on the terminal surfaces T1 and T2 is determined by the amount of immersion (depth) Wb of the paste material P in the bath (FIG. 8E). Therefore, since the electrode width of the internal electrode layers 111 and 112 exposed from the terminal surfaces T1 and T2 can be adjusted by the amount of immersion (depth) Wb of the paste material P in the bath, a multilayer capacitor having a desired ESR characteristic can be obtained. It can be manufactured stably and accurately. The immersion amount Wb is the same on the one adjustment layer 13a side and the other adjustment layer 13b side, but may be different from each other.

  9A to 9C show a configuration of a plurality of terminal coating layers 131a and 131b having different opening widths Wa. When the equivalent series resistance when the opening width of the gap is Wa1 is ESR1, the equivalent series resistance when the opening width is Wa2 is ESR2, and the equivalent series resistance when the opening width is Wa3 is ESR3, the case of Wa1 <Wa2 <Wa3 , ESR3 <ESR2 <ESR1.

  Furthermore, according to this embodiment, the amount of immersion (depth) of the laminated body 11 in the bath of the paste material P is set to be less than ½ of the width dimension of the laminated body 11, thereby A terminal coating layer having a desired opening width at the center can be formed on each of the terminal surfaces T1 and T2.

(Formation of external electrodes)
After the formation of the resistance adjuster 13 (adjustment layers 13a and 13b), external electrodes 12a and 12b are formed, respectively. Typically, the external electrodes 12a and 12b are made of a paste material of a base metal material such as Ni, for example, the same type as the internal electrode layers 111 and 112, at each end including both terminal surfaces T1 and T2 of the laminate 11. It is produced by baking after coating. Thereafter, if necessary, solder plating is applied to the surfaces of the external electrodes 12a and 12b.

  In the present embodiment, the firing process of the external electrodes 12 a and 12 b is performed in the same process as the firing process of the stacked body 11 and the resistance adjusting unit 13. Thereby, the number of processes can be reduced and productivity can be improved.

  Furthermore, by forming the adjustment layers 13a and 13b by the above-described dipping method, the end portions Ga of the terminal coating layers 131a, 131b, 132a, and 132b are shown in FIG. 6 using the surface tension of the paste material. It can be formed in a simple streamline shape. Thereby, the adhesiveness between the terminal coating layers 131a and 131b and the external electrode 12a and the adhesiveness between the terminal coating layers 132a and 132b and the external electrode 12b can be ensured. Further, the connection reliability between the internal electrode layers 111a and 111b and the external electrodes 12a and 12b can be ensured.

<Second Embodiment>
FIG. 10 is an overall perspective view schematically showing the multilayer capacitor in accordance with the second embodiment of the present invention. Hereinafter, configurations different from those of the first embodiment will be mainly described, and configurations similar to those of the above-described embodiment will be denoted by the same reference numerals, and description thereof will be omitted or simplified.

  The multilayer capacitor 20 of this embodiment includes a multilayer body 11, first and second adjustment layers 13a and 13b, and first and second external electrodes 22a and 22b. The stacked body 11 and the first and second adjustment layers 13a and 13b have the same configuration as that of the first embodiment described above.

  Differences from the first embodiment described above are as follows. In other words, in the first embodiment, the outer surfaces of the external electrodes 12a and 12b have a concavo-convex shape corresponding to the surface step of the base (laminated body 11, first and second adjustment layers 13a and 13b) ( (See FIG. 1). On the other hand, in the multilayer capacitor 20 of this embodiment, the outer surfaces of the first and second external electrodes 22a and 22b are formed as flat surfaces. Thereby, the external electrodes 22a and 22b having a flat mounting surface can be formed.

  There is no particular limitation on the method of filling the underlying steps of the external electrodes 22a and 22b. For example, the step on the main surfaces M1 and M2 of the multilayer body 11 can be flattened by filling the step with an insulating material such as a ceramic dielectric. Further, the step on the terminal surfaces T1 and T2 may be formed relatively thick so that the conductive paste constituting the external electrodes 22a and 22b is not affected by the step of the base.

<Third Embodiment>
FIG. 11 is an overall perspective view schematically showing the multilayer capacitor in accordance with the third embodiment of the present invention. Hereinafter, configurations different from those of the first embodiment will be mainly described, and configurations similar to those of the above-described embodiment will be denoted by the same reference numerals, and description thereof will be omitted or simplified.

  The multilayer capacitor 30 of the present embodiment includes the multilayer body 11, a resistance adjustment unit 33 having first and second adjustment layers 33a and 33b, and first and second external electrodes 22a and 22b. The stacked body 11 has the same configuration as that of the above-described first embodiment, and the first and second external electrodes 22a and 22b have the same configuration as that of the above-described second embodiment, although the forms are different.

  In the multilayer capacitor 30 of this embodiment, the first and second adjustment layers 33a and 33b constituting the resistance adjustment unit 33 are formed only on both terminal surfaces T1 and T2 and both side surfaces S1 and S2 of the multilayer body 11. This is different from the first and second embodiments described above. That is, the resistance adjustment unit 33 includes a first side margin layer 330a formed on the first side surface S1, a second side margin layer 330b formed on the second side surface S2, and a first terminal surface. It has 1st terminal coating layer 331a, 331b formed on T1, and 2nd terminal coating layer 332a, 332b formed on 2nd terminal surface T2.

  The first terminal coating layers 331a and 331b correspond to the first terminal coating layers 131a and 131b described in the first embodiment, and the leading end portion 111a of the first internal electrode layer 111 and the first external electrode. The connection width with 22a is defined. The second terminal coating layers 332a and 332b correspond to the second terminal coating layers 132a and 132b described in the first embodiment, and the leading end portion 112a and the second external electrode of the second internal electrode layer 112. The connection width with 22b is defined.

  The adjustment layers 33a and 33b are formed by removing the paste material P adhering to both the main surfaces M1 and M2 of the multilayer body 11 by a polishing process or the like after the step shown in FIG. As a result, the flatness of the main surfaces M1, M2 can be maintained, so that the mounting surfaces of the external electrodes 22a, 22b can be formed flat.

<Fourth Embodiment>
FIG. 12 is an overall perspective view schematically showing the multilayer capacitor in accordance with the fourth embodiment of the present invention. Hereinafter, configurations different from those of the first embodiment will be mainly described, and configurations similar to those of the above-described embodiment will be denoted by the same reference numerals, and description thereof will be omitted or simplified.

  The multilayer capacitor 40 of the present embodiment includes a multilayer body 11, a resistance adjustment unit having first and second adjustment layers 43a and 43b, and first and second external electrodes 22a and 22b. The stacked body 11 has the same configuration as that of the above-described first embodiment, and the first and second external electrodes 22a and 22b have the same configuration as that of the above-described second embodiment, although the forms are different.

  In the multilayer capacitor 40 of the present embodiment, the first and second adjustment layers 43a and 43b constituting the resistance adjustment unit are formed only on the both terminal surfaces T1 and T2 of the multilayer body 11, and thus the above-described first. Different from the first to third embodiments. That is, the first and second adjustment layers 43a and 43b constitute a resistance adjustment unit that limits the connection width between the lead ends 111a and 112a of the internal electrodes and the external electrodes 22a and 22b. In the present embodiment, the first adjustment layer 43a is composed of a pair of terminal coating layers 431a and 431b formed on the first terminal surface T1 of the multilayer body 11, and the second adjustment layer 43b is formed of the multilayer body 11. It comprises a pair of terminal coating layers 432a and 432b formed on the second terminal surface T2.

  As described above, the adjustment layers 43a and 43b of the present embodiment do not have a configuration corresponding to the side margin layers 130a and 130b described in the first embodiment, and are insulating layers formed on the terminal surfaces T1 and T2. Each is composed only of. Even with such a configuration, the equivalent series resistance (ESR) of the multilayer capacitor 40 can be easily adjusted.

  The embodiment of the present invention has been described above, but the present invention is not limited to the above-described embodiment, and it is needless to say that various modifications can be made without departing from the gist of the present invention.

  For example, in the first embodiment described above, the example in which the terminal coating layers 131a, 131b, 132a, and 132b that form the resistance adjustment unit 13 are formed by the dipping method has been described. Other methods such as lamination may be employed.

  Further, the openings (gap G1, G2) for limiting the exposed width of the leading end portions 111a, 112a of the internal electrode layer may be formed by machining or the like after forming the insulating layer covering the terminal surfaces T1, T2. Good.

  Furthermore, as the multilayer body 11 constituting the multilayer capacitor 30 according to the first to third embodiments described above, the first and second sheet materials 11a and 11b having the configuration shown in FIG. 5 are employed. Here, since the adjustment layers 13a and 13b include the side margin layers 130a and 130b, the internal electrode layers 111 and 112 formed on the dielectric sheet 110s are formed with substantially the same width as the width of the dielectric sheet 110s. It is also possible to do. FIG. 13 shows the configuration of the first and second sheet materials 21a and 21b having the internal electrode layers 211 and 212 formed with the same width as that of the dielectric sheet 110s. A laminated body 21 is produced by alternately laminating a plurality of first and second sheet materials 21a and 21b configured as described above. In the laminate 21, both edges of the internal electrode layers 211 and 212 are exposed on the side surfaces, but the adjustment layers 13a and 13b (side margin layers 130a and 130b) manufactured through the steps shown in FIG. A predetermined side margin can be secured. Further, the end portions 211a and 212a (first and second lead end portions) of the internal electrode layer exposed from both terminal surfaces of the multilayer body 21 have the same width as the dielectric sheet 110s, and thus the adjustment layers 13a and 13b. The degree of freedom of adjustment of the connection width with the external electrode by the (terminal covering layers 131a, 131b, 132a, 132b) is increased. As a result, the ESR adjustment range can be expanded. Furthermore, it is possible to prevent variation in capacitance due to a positional shift in the width direction of the internal electrode layers 211 and 212 with respect to the dielectric sheet 110s.

  Furthermore, in the above embodiment, the amount of immersion (depth) of the laminate 11 in the bath of the paste material P is set to be less than ½ of the width dimension of the laminate 11 as shown in FIG. In addition, terminal coating layers 131a and 131b having a predetermined width Wb whose central portion opens with an opening width Wa are formed on the terminal surface T1. Instead, the terminal coating layers 131a and 131b may be formed so that the opening is biased toward the side surface S1 or S2. In this case, the amount of immersion (depth) of the laminate 11 in the bath of the paste material P is made different between the side surfaces S1 and S2 of the laminate 11 as shown in FIG. 14B, for example. Terminal covering layers 131a and 131b having mutually different widths Wb1 and Wb2 can be formed on the side surface S1 side and the side surface S2 side. Moreover, the terminal coating layer which is biased toward the other side surface and opens with the opening width Wax is obtained by setting the amount of immersion of one side surface in the bath of the paste material to ½ or more of the width dimension of the laminate 11. Can be formed. The size of the width Wax of the opening is not particularly limited, and can be appropriately set according to the target ESR value.

DESCRIPTION OF SYMBOLS 10, 20, 30, 40 ... Multilayer capacitor 11, 21 ... Laminated body 12a, 12b, 22a, 22b ... External electrode 13, 33, 43 ... Resistance adjustment part 13a, 13b, 33a, 33b, 43a, 43b ... Adjustment layer 110 ... Dielectric layers 111, 112, 211, 212 ... Internal electrode layers 111a, 112a, 211a, 212a ... Lead ends 121a, 121b ... Conductors 122a, 122b ... Conductive coating layers 130a, 130b, 330a, 330b ... Side margins Layers 131a, 131b, 132a, 132b, 331a, 331b, 332a, 332b, 431a, 431b, 432a, 432b ... Terminal coating layer M1, M2 ... main surface S1, S2 ... side surface T1, T2 ... terminal surface

Claims (7)

A first interior having a first drawing end portion that is formed in a rectangular parallelepiped shape having a first terminal surface and a second terminal surface that face each other in the first axial direction, and is exposed from the first terminal surface. An electrode, and a second internal electrode having a second lead-out end exposed from the second terminal surface facing the first internal electrode in a second axial direction orthogonal to the first axial direction A laminate having a dielectric layer disposed between the first internal electrode and the second internal electrode;
A first external electrode having a first conductor portion disposed on the first terminal surface and electrically connected to the first lead-out end portion;
A second external electrode having a second conductor portion disposed on the second terminal surface and electrically connected to the second lead-out end portion;
A first insulating layer disposed on the first terminal surface for limiting a connection width of the first conductor portion to the first lead-out end portion; and the second lead-out disposed on the second terminal surface. A resistance adjusting unit having a second insulating layer that limits a connection width of the second conductor part to the end part,
The first insulating layer and the second insulating layer are each in a length direction in the second axial direction and in a third axial direction orthogonal to the first axial direction and the second axial direction, respectively. Each having a first opening and a second opening having a width direction;
The first lead-out end portion and the second lead-out end portion are respectively connected to the first conductor portion and the second conductor portion through the first and second openings.
The laminate further includes a first side surface and a second side surface that face each other in the third axial direction, and from which the first internal electrode and the second internal electrode are exposed,
The resistance adjusting unit further includes a pair of insulating coating layers formed on the first side surface and the second side surface, respectively, for interconnecting the first insulating layer and the second insulating layer. Capacitor. The multilayer capacitor according to claim 1,
The first insulating layer has a pair of first terminal coating layers facing each other through the first opening in the third axial direction,
The second insulating layer has a pair of second terminal covering layers facing each other through the second opening in the third axial direction,
The width dimension along the third axial direction of each of the pair of first terminal coating layers, the width dimension along the third axial direction of each of the pair of second terminal coating layers, and the first A multilayer capacitor in which at least one of the width dimensions along the third axial direction of each of the one opening and the second opening is different from each other. The multilayer capacitor according to claim 1 or 2,
The resistance adjusting unit is a multilayer capacitor made of a ceramic material. The multilayer capacitor according to any one of claims 1 to 3,
The pair of external electrodes further includes a conductive coating layer that covers the first terminal surface and the second terminal surface from above the first insulating layer and the second insulating layer, respectively. A first internal electrode having one end exposed from the first terminal surface; and a second internal electrode having one end exposed from the second terminal surface facing the first terminal surface in the first axial direction; By alternately laminating in a second axial direction orthogonal to the first axial direction through a dielectric layer, a rectangular parallelepiped laminated body is produced,
Forming a first insulating layer on the first terminal surface having a first opening for limiting a width of the first internal electrode exposed from the first terminal surface;
Forming a second insulating layer having a second opening for limiting a width of the second internal electrode exposed from the second terminal surface on the second terminal surface;
A first external electrode electrically connected to the first internal electrode through the first opening is formed on the first terminal surface, and the second external electrode through the second opening. A method of manufacturing a multilayer capacitor in which a second external electrode electrically connected to the internal electrode is formed on the second terminal surface,
The step of producing the laminate includes producing the laminate so that the first internal electrode and the second internal electrode are exposed from both side surfaces of the laminate,
The step of forming the first insulating layer and the second insulating layer includes the step of forming an insulating paste material along a third axial direction orthogonal to the first axial direction and the second axial direction, respectively. A method for manufacturing a multilayer capacitor, comprising immersing the both side surfaces of the multilayer body in a bath. A manufacturing method of the multilayer capacitor according to claim 5,
A method for manufacturing a multilayer capacitor, wherein an immersion depth of the multilayer body in the bath is less than ½ of a width dimension along the third axial direction of the multilayer body. A manufacturing method of the multilayer capacitor according to claim 5,
A method of manufacturing a multilayer capacitor, wherein the immersion depth of the multilayer body in the bath is different from each other on the both side surfaces of the multilayer body.

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