JP6291261B2 - Communication apparatus, control method, and program - Google Patents

Description

  The present invention relates to a communication device, a control method, and a program.

  In recent years, not only general-purpose computers (PCs) but also computer embedded devices are required to execute network protocol processing at high speed. However, the sufficient processing speed of Gigabit Ethernet (registered trademark) by software processing far exceeds the capacity of the processor installed in the computer embedded device. Therefore, it is common to add a supplementary device specialized for protocol processing such as TOE (TCP / IP Offload Engine) to realize broadband network communication without depending on the processor.

  On the other hand, a protocol processing device such as the TOE has a large capacity for temporarily storing packets in order to simultaneously realize communication with a plurality of communication devices or a plurality of connections with one communication partner. Memory resources will be prepared. These resources supply power to all resources regardless of whether the protocol processor is performing the maximum number of communications that can be communicated simultaneously, or if there is no communication or only a small amount of communication. Therefore, it is not efficient in terms of power consumption.

  In contrast, Patent Document 1 controls the effective number of packet buffers that temporarily store received packets according to the amount of received packets, and supplies power to some packet buffers when traffic is low. A method to stop and reduce power consumption is proposed.

JP 2011-061443 A

  In the TOE, not only memory resources for temporarily storing packets, but also various hardware (HW) resources and on-chip memory resources are used for speeding up protocol processing. Many of these resources should be retained corresponding to the maximum number that can be communicated at the same time. Similarly to memory resources for accumulating packets, the entire HW can be powered even in a small amount of communication. A large amount of power is consumed by being supplied.

  The method shown in Patent Document 1 is intended only for control of memory resources, and in a configuration that requires various HW resources and on-chip memory such as TOE, there is a problem that not all power sources can be controlled. there were. In addition, the technique described in Patent Document 1 supplies power in a predictive manner according to the amount of received packets, and there is a problem that the power of resources required in actual communication cannot be finely controlled.

  The present invention has been made in view of the above problems, and an object thereof is to perform detailed power supply and stop control of resources for communication processing in accordance with actual communication conditions.

In order to achieve the above object, a communication apparatus according to the present invention is used for TCP protocol processing, and is used for TCP protocol processing, a plurality of timers corresponding to each of a plurality of TCP sockets, A plurality of memories corresponding to each of the TCP sockets, an identifier indicating each of the plurality of TCP sockets, and the timer and the memory used for TCP protocol processing in the TCP socket indicated by each identifier are managed in association with each other And when the TCP communication using the new TCP socket is started , the assigning means for assigning a first identifier indicating the new TCP socket to the new TCP socket, and the assigning means 1 is assigned to the first identifier managed by the management means. Start means for collectively starting power supply and clock supply to the corresponding timer and the memory, and the TCP managed by the management means when the TCP socket corresponding to the first identifier is released Stop means for collectively stopping power supply and clock supply to the timer and the memory corresponding to one identifier .

  According to the present invention, it is possible to perform detailed power supply and stop control of resources for communication processing according to actual communication conditions.

The figure which shows the structural example of a communication apparatus. The figure which shows TOE subsystem structure. The figure explaining the role of a sub processor. The flowchart which shows the flow of TCP socket creation processing. The flowchart which shows the flow of a TCP socket ID acquisition process. The flowchart which shows the flow of a TCP socket ID initialization process. The flowchart which shows the flow of a TCP socket release process. The flowchart which shows the flow of a TCP socket ID return process. The flowchart which shows the flow of a new IP reassembly start process. The flowchart which shows the flow of IP reassembly ID acquisition processing. The flowchart which shows the flow of IP reassembly ID initialization processing. The flowchart which shows the flow of an IP reassembly resource release process. The flowchart which shows the flow of IP reassembly ID return processing.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

(Configuration of communication device)
A configuration example of the communication apparatus according to the present embodiment will be described with reference to FIG. In the communication apparatus of FIG. 1, the main processor 101 is connected to each configuration described later via a system bus 102. The system bus 102 is an on-chip bus having a crossbar switch structure typified by AMBA 3.0 AXI (Advanced extensible Interface) specification proposed by the British company ARM. The system bus 102 can perform a parallel transfer operation of transmission / reception data required for the communication device. The main processor 101 is a computer that executes control of the entire communication apparatus.

  The interrupt control unit 106 transmits an interrupt event from each configuration or the TOE subsystem 105 to the main processor 101. The timer 107 is activated by software or the like, and generates a time measurement or a timeout event. An input key 115 connected to the general-purpose input / output (IO) interface 114 is a functional unit for accepting the setting of the operation mode of the communication device and the input of various communication parameters typified by an IP address. A display unit 109 connected to the display control unit 108 displays a communication device state, an application state, setting contents, and the like. The main DMA control unit 112 is a controller (DMAC) that controls direct memory access (DMA) in the communication device.

  The hard disk (HD) device 111 connected to the secondary storage control unit 110 stores software that implements the function of the communication device and its related data, firmware executed by the sub processor of each subsystem, its related data, and the like. The HD device 111 further stores history information such as an operation history and a communication history of the communication device. Note that the software that implements the functions of the communication device includes an operating system (OS), application software that implements each function of the communication device, an application protocol, a device driver for controlling related hardware, and the like.

  The flash memory 118 connected to the memory control unit 117 is a rewritable nonvolatile memory, and the SRAM 119 is a rewritable volatile memory. At least one of the flash memory 118 and the SRAM 119 stores a boot program that operates when the communication apparatus is activated, parameters used for setting the initial state of the communication apparatus, and the like. At least one of the flash memory 118 and the SRAM 119 further stores a device driver for controlling each configuration (hardware) when starting the communication apparatus, a setting parameter when starting each configuration, and the like. The main processor 101 executes a boot program stored in at least one of the flash memory 118 and the SRAM 119.

  The main memory 104 connected to the main memory control unit 103 functions as a work memory of the main processor 101, for example. For example, after initializing each hardware and subsystem of the communication device, the main processor 101 loads software stored in the HD device 111 into the main memory 104 and activates the OS. Further, the main processor 101 expands each firmware executed by the sub processors A to E (201 to 205) built in the TOE subsystem 105 on the main memory 104 when the subsystem is initialized, and Start the processor. Each sub-processor 201-205 loads each firmware developed on the main memory 104 into an instruction cache memory built in each sub-processor, and executes the firmware program. The main memory 104 is divided into a plurality of blocks, and the main memory control unit 103 can instruct power supply and stop for each block.

  The TOE subsystem 105 is a functional unit for the communication device to connect to the wired network 120. Details of the TOE subsystem 105 will be described later. The wireless LAN subsystem 113 is a functional unit for connecting a communication apparatus to a wireless LAN network that conforms to the IEEE802.11a / b / g / n standard. The general-purpose bus interface 116 connects the communication device to a serial bus such as USB or IEEE1394.

(Configuration of TOE subsystem)
Next, a configuration example of the TOE subsystem 105 according to the present embodiment will be described in detail with reference to FIG.

  The bus bridge 206 connects a subsystem bus 208 that is an internal bus of the TOE subsystem 105 and the system bus 102. The subsystem bus 208 is, for example, a crossbar switch connection. The TOE sub-system 105 includes five sub-processors 201 to 205, and offloads TCP / IP protocol processing from the main system by multi-processor processing by these sub-processors, and executes this protocol processing at high speed. The shared memory 215 is a memory for communication and information sharing between the sub processors 201 to 205. The communication timer 216 generates a time measurement and time-out event necessary for TCP / IP protocol processing.

  The role of the sub processors 201 to 205 of the TOE subsystem 105 according to the present embodiment will be described with reference to FIG. The TCP / IP protocol process has a hierarchical structure of an application layer 301, a socket API 302, a transport layer (TCP / UDP layer) 303, an Internet layer (IP layer) 304, a MAC driver 305, a MAC layer 306, and a PHY layer 307. Here, the TOE subsystem 105 has a function of processing a portion indicated by 310 in FIG. That is, the TOE subsystem 105 has a (processing) function of the TCP / UDP layer 303, the IP layer 304, and the MAC driver 305, and a partial function of the socket API 302. The TCP / UDP layer 303 processes the TCP protocol and the UDP protocol, and the IP layer 304 processes the IP protocol. The MAC driver 305 is a function for exchanging communication data and communication information with the MAC layer 306, and the socket API 302 is an application communication API. The TOE subsystem 105 performs processing by distributing these functions to the sub processors.

  For example, a part of the processing of the socket API 302 is assigned to the sub processor 201. Then, among the processes of the TCP protocol and the UDP protocol, the process related to the reception operation 315 is assigned to the sub processor 202, and the process related to the transmission operation 316 is assigned to the sub processor 203. Further, among the processes of the MAC driver 305 and the IP protocol, the process related to the reception operation 315 is assigned to the sub processor 204, and the process related to the transmission operation 316 is assigned to the sub processor 205. By distributing the processing in this way, a series of protocol processing can be divided into three pipeline stages 311 to 313 and a pipeline operation can be performed. In addition, by separating the transmission operation 316 and the reception operation 315, it is possible to operate the sub processors in charge of each function in parallel.

  In this embodiment, transmission of processing data and sharing of control information between the sub-processors is performed via the shared memory 215. For example, TCP transmits arrival confirmation information called a confirmation response between connections from the reception side to the transmission side from the viewpoint of guaranteeing the arrival of transfer data. In order to perform this confirmation response, a confirmation response is transmitted (314) between the sub processor 202 and the sub processor 203. In the TOE subsystem 105, transmission of such TCP control information is performed via the shared memory 215. Note that transmission of arrival confirmation information and sharing of control information between sub-processors may be performed using the main memory 104. In the TOE subsystem 105, control information necessary for TCP processing is shared using a TCB controller 218 described later.

  The TOE subsystem 105 includes a PHY 214 and a MAC (Media Access Controller) 213 as hardware for connecting to the wired network 120. The PHY 214 handles protocol processing and electrical signals of the physical layer (first layer) of the OSI reference model. The MAC 213 processes a MAC layer protocol corresponding to a lower sublayer of the data link layer (second layer) of the OSI reference model.

  Returning to FIG. 2, the data path control unit 212 has a function of performing DMA transfer between the received packet data and the transmitted packet data between, for example, the main memory 104 or the shared memory 215 and the MAC 213. The data path control unit 212 performs a checksum operation on the packet data during the transfer process. The search device 207 has an associative memory, and stores and searches various management information for protocol processing.

  The TOE subsystem 105 further includes a TCB controller 218 that controls a memory for storing control information for communication processing by TCP. The TOE subsystem 105 further includes a bitmap controller 219 that manages information on packets (fragments) received in the IP reassembly process, and an ID manager 217 that manages the number of simultaneous protocol processes. Note that the ID manager 217 manages at least one of the number of reassembled data and the number of TCP sockets that exist in parallel at the same time by using an identifier (ID) as a unit of processing. Further, the ID manager 217 includes a power control unit 220 and is used for processing a communication protocol. For the hardware resources each having a plurality of blocks that can individually control power supply and stoppage. Control of power supply and stop of each block is performed.

  The TOE subsystem 105 executes cryptographic communication protocol processing. The encryption communication protocol is, for example, IPsec (Security Architecture for Internet Protocol). The encryption communication protocol may be, for example, SSL (Secure Socket Layer) or TLS (Transport Layer Security). For these cryptographic communication protocol processes, the TOE subsystem 105 includes a key management unit 209, a random number generator 210, and an encryptor 211. The key management unit 209 keeps the encryption key, the random number, and the prime number generated for the encryption communication protocol processing secretly. The random number generator 210 generates a random value necessary for cryptographic processing. The encryption device 211 is, for example, an AES (Advanced Encryption Standard) encryption device. The encryptor 211 further includes hash function units such as SHA-1 (Secure Hash Algorithm 1) used for authentication and digital signature, and MD5 (Message Digest 5) standardized as RFC2121.

  The TOE subsystem 105 prepares resources such as a communication timer 216, a memory area managed by the TCB controller 218, a search entry of the search device 207, and a socket buffer of the main memory 104 for each TCP socket. Each resource has a plurality of blocks capable of power supply and stop control corresponding to the maximum number of TCP sockets that can establish connections at the same time. Each block is managed in association with an identifier (ID) of a TCP socket managed by the ID manager 217. That is, for each ID, the power supply to each block and the stop thereof can be controlled. The power supply control unit 220 collectively supplies power or supplies power to each block of one or more resources corresponding to the ID according to the start or end of communication by the TCP socket corresponding to the ID. Control is performed to stop the operation.

  Further, the TOE subsystem 105 allocates resources such as a communication timer 216, a bitmap controller 219, a search entry of the search device 207, and an IP reassembly buffer of the main memory 104 for each set of fragments reassembled into one data. prepare. Each resource has a plurality of blocks capable of power supply and stop control corresponding to the maximum number of fragments that can be simultaneously IP reassembled. Each block is managed in association with an identifier (ID) of data to be reassembled managed by the ID manager 217. That is, for each ID, the power supply to each block and the stop thereof can be controlled. The power supply control unit 220 supplies power to the blocks corresponding to the IDs of the resources collectively in response to the start or end of communication of one reassembled data fragment set corresponding to the ID. Alternatively, control is performed to stop the supply of power.

  Note that power control of the main memory 104 is performed by the main memory control unit 103 in accordance with an instruction from the power control unit 220 in the ID manager 217. Each hardware (HW) resource and the power supply control unit 220 are connected by a power supply control port 221, and according to an instruction from the ID manager 217, the power supply control unit 220 controls the power supply of each HW resource via the power supply control port. I do.

  In this embodiment, one of a plurality of blocks for each of one or more resources is associated with one ID, and corresponding to the corresponding block according to the start and end of communication corresponding to one ID. The power supply is controlled to be supplied and stopped. However, such a configuration is not necessary. That is, one block may be associated with a plurality of IDs. When a plurality of IDs are associated with one block, power supply to the block is performed when communication is started for at least one of the plurality of IDs corresponding to the one block. Control is performed as follows. In this case, control is performed so that power supply to this block is stopped in response to the end of communication for all of the plurality of IDs corresponding to that block.

  Further, instead of controlling the supply of power and its stop, control may be performed so that the supply and stop of the clock are executed. In this embodiment, the case where protocol processing in a TCP socket and IP fragment packet reassembly processing are used is described as the type of protocol processing. However, other types of protocol processing such as UDP processing may be used. Good.

(TCP socket creation processing)
Next, the flow of TCP socket creation processing according to the present embodiment, which is executed by the sub processor 202 or the sub processor 203, will be described with reference to FIGS. This process is, for example, a process when the communication protocol processing unit corresponding to the power control is related to communication using one TCP socket. Hereinafter, the sub processor 202 or the sub processor 203 is simply referred to as a “sub processor”.

  First, in S401 of FIG. 4, the sub processor requests the ID manager 217 to acquire a TCP socket identifier (TCP socket ID), and receives the TCP socket ID from the ID manager 217. The flow of TCP socket ID acquisition processing in the ID manager 217 at this time will be described in detail with reference to FIG.

  In step S501, the ID manager 217 checks whether the current TCP socket ID counter has reached the maximum value. That is, the ID manager 217 determines whether the number of currently used TCP sockets has already reached the maximum value that can be handled at the same time. The ID manager 217 outputs an error if the maximum value of the TPC socket has been reached (S513), ends the process, and proceeds to S502 if the maximum value has not been reached.

  In S502, the ID manager 217 selects one (arbitrary) ID value from the TCP socket ID values held by itself. That is, in S502, an ID assignment process for a newly created TCP socket is executed. The TCP socket ID value is held by a predetermined method that can hold the ID value, such as storing the ID value using a FIFO or holding it using a bitmap. The ID manager 217 may hold ID values as many as the maximum number of TCP sockets that can be handled simultaneously, or may hold more ID values.

  Subsequently, the ID manager 217 determines whether power is supplied to the TCP timer block corresponding to the TCP socket ID (S503). If power is not supplied to the block, the process proceeds to S504, where the power is supplied. If yes, the process proceeds to S505. Here, the “block” is a unit for managing the supply of power, and the power supply and the stop thereof can be individually controlled for one block. Note that a block may be associated with a single ID or may be associated with a plurality of IDs. In S504, the ID manager 217 instructs the communication timer 216 to supply power to the TCP timer block corresponding to the TCP socket ID, and the process proceeds to S505.

  In S505, the ID manager 217 checks whether power is supplied to the entry block of the TCP socket search table of the search device 207 corresponding to the TCP socket ID. Then, the process proceeds to S506 when power is not supplied to the block, and proceeds to S507 when power is supplied to the block. In S506, the ID manager 217 instructs the search device 207 to supply power to the block of the search entry in the TCP socket search table corresponding to the TCP socket ID, and the process proceeds to S507.

  In S507, the ID manager 217 checks whether power is supplied to the block in the memory area managed by the TCB controller 218 corresponding to the TCP socket ID. Then, the process proceeds to S508 when the block is not supplied with power, and proceeds to S509 when the block is supplied. In S508, the ID manager 217 instructs the TCB controller 218 to supply power to the memory block in the memory area managed by the TCB controller corresponding to the TCP socket ID, and the process proceeds to S509.

  In step S509, the ID manager 217 checks whether power is supplied to the main memory block in the TCP socket buffer area corresponding to the TCP socket ID. Then, the process proceeds to S511 when power is supplied to the main memory block, and proceeds to S510 when power is not supplied. In S510, the ID manager 217 instructs the main memory control unit 103 to supply power to the main memory block in the TCP socket buffer area of the main memory 104 corresponding to the TCP socket ID, and the process proceeds to S511.

  In S511, the ID manager 217 outputs the ID value selected in S502 (allocated by the allocation process), increments a counter that manages the number of TCP socket IDs used in S512, and ends the process.

  In the present embodiment, the power supply instruction is performed according to the above-described procedure. However, any procedure may be used as long as power can be supplied to each hardware resource. For example, the order of S503 to S504 and the order of S505 to S506 may be reversed, and the order of other processes may be changed. In addition, when power is constantly supplied to one or more of the above-described blocks, the determination of whether power is supplied to the block and the processing of the power supply instruction may be omitted.

  Returning to FIG. 4, as described above, when the TCP socket ID is transferred from the ID manager 217 to the sub processor (S401), the sub processor checks the result obtained in S401 in S402. If the ID value cannot be acquired and an error is output, the sub processor outputs a socket creation failure (S408), and ends the process. On the other hand, if the ID value can be acquired, the process proceeds to S403.

  In step S403, the sub processor instructs the TCB controller 218 to load a TCB controller management memory area corresponding to the acquired ID value. In step S <b> 404, the sub processor writes the TCP connection information in the TCB controller 218 and initializes the socket information. Subsequently, the sub processor sets and starts the TCP timer of the communication timer 216 corresponding to the acquired TCP socket ID (S405). Then, the sub processor registers the TCP socket search information in the search entry of the TCP socket search table of the search device 207 corresponding to the acquired TCP socket ID (S406), outputs the socket creation success (S407), and performs the processing. finish. Note that the order of these steps may be changed.

(TCP socket ID initialization process)
Next, the flow of TCP socket ID initialization processing by the main processor 101 will be described with reference to FIG. In this embodiment, the main processor performs the TCP socket ID initialization process, but the sub-processor in the TOE may execute this process. This process is executed, for example, when the power of the communication apparatus is turned on. After this process, the processes shown in FIGS. 4 and 5 are executed.

  In step S <b> 601, the main processor 101 sets the maximum value of the TCP socket ID in the ID manager 217. This setting value is the maximum number of simultaneous TCP socket connections determined for each system. Thereafter, the main processor 101 secures socket buffer areas for the maximum number of TCP socket ID values on the main memory 104 (S602). This area is secured in an area where power control is possible under the control of the main memory control unit 103. In the present embodiment, the case where the socket buffer is secured on the main memory has been described. However, the socket buffer may be secured on another memory as long as the power source can be controlled for each buffer. .

  Subsequently, the main processor 101 sets the position information of the socket buffer secured in S602 in the ID manager 217 (S603). Based on this setting information, the ID manager 217 issues a power control instruction at the start or end of communication using the TCP socket (that is, when the TCP socket ID is acquired and released). Thereafter, the main processor 101 sets a memory area for the TCB controller in the TCB controller 218 (S604). Based on this setting information, the TCB controller 218 loads or unloads the memory area corresponding to the TCP socket ID according to an instruction from the sub processor. Then, the main processor 101 sets a search table for TCP socket search for the search device 207 (S605). Thereafter, the main processor 101 instructs the ID manager 217 that power control of the hardware resource associated with the TCP socket ID should be started (S606), and ends the process. Note that the order of the steps described above may be changed, or some steps may be deleted.

(TCP socket release processing)
Subsequently, the flow of the TCP socket release process according to the present embodiment, which is executed in the sub processor 202 or the sub processor 203, will be described with reference to FIGS. Hereinafter, the sub processor 202 or the sub processor 203 is simply referred to as a “sub processor”.

  First, when communication using a certain TCP socket is completed, the sub processor deletes the entry in the area corresponding to the TCP socket ID value of the search device 207 in S701 of FIG. Then, the sub processor clears the TCP socket information corresponding to the TCP socket ID value of the TCB controller 218 (S702), and stops the TCP timer corresponding to the TCP socket ID value (S703). Further, in S704, the sub processor returns the TCP socket ID value to the ID manager 217, and ends the process.

  Here, the TCP socket ID return process executed by the ID manager 217 when the TCP socket ID value is returned in S704 will be described with reference to FIG. In step S801, the ID manager 217 adds the returned ID value to the stored TCP socket ID value. That is, the ID manager 217 adds and holds the returned ID value as a candidate to be assigned to communication by a TCP socket that is newly started thereafter.

  Then, the ID manager 217 instructs to stop power supply for each hardware resource block corresponding to the returned ID value. Specifically, in step S802, the communication timer 216 is instructed to stop the power supply of the TCP timer corresponding to the ID value. In step S803, the power supply stop of the entry in the TCP socket search table corresponding to the ID value is sent to the search device 207. Is instructed. In S804, the TCB controller is instructed to stop the power supply of the memory area for the TCB controller corresponding to the ID value. In S805, the power supply stop of the socket buffer area on the main memory 104 corresponding to the ID value is set to the main memory control unit. 103. In step S806, the ID manager 217 decrements the counter that manages the number of used TCP socket IDs, and ends the process. For each of the above-described steps, for example, the order of power stop instructions may be changed, or some steps may be deleted.

(IP reassembly start processing)
Next, a new IP reassembly start process according to the present embodiment, which is executed by the sub processor 204, will be described with reference to FIGS. This process is, for example, a process when the communication protocol processing unit corresponding to the power control is related to communication of a set of fragments reassembled into one data.

  First, in S901 of FIG. 9, the sub processor 204 requests the ID manager 217 to obtain an IP reassembly ID, and receives the IP reassembly ID from the ID manager 217. The flow of IP reassembly ID acquisition processing in the ID manager 217 at this time will be described in detail with reference to FIG.

  In step S1001, the ID manager 217 checks whether the current IP reassembly counter has reached the maximum value. That is, the ID manager 217 determines whether the number of IP reassembly currently being executed in parallel has already reached the maximum value that can be handled simultaneously. The ID manager 217 outputs an error if the number of simultaneous IP reassemblys has reached the maximum value (S1013), ends the process, and if not, reaches the process to S1002. Proceed.

  In S1002, the ID manager 217 selects one (arbitrary) ID value from the IP reassembly ID value held by itself. That is, in S1002, an ID assignment process is executed for a newly executed IP reassembly. Similar to the TCP socket ID value, the IP reassembly ID value is held by a predetermined method that can hold the ID value, such as storing the ID value using a FIFO or holding it using a bitmap.

  Subsequently, the ID manager 217 determines whether power is supplied to the block of the IP reassembly timer corresponding to the IP reassembly ID (S1003). As a result of the determination, the process proceeds to S1004 when power is not supplied to the block, and proceeds to S1005 when power is supplied to the block. The “block” here is also a unit for managing the supply of power as described above, and the power supply and the stop thereof can be individually controlled for one block. Also, the block may be associated with a single ID, or may be associated with a plurality of IDs, as described above. In S1004, the ID manager 217 instructs the communication timer 216 to supply power to the block of the IP reassembly timer corresponding to the IP reassembly ID, and the process proceeds to S1005.

  In step S1005, the ID manager 217 checks whether power is supplied to the entry block of the IP reassembly search table of the search device 207 corresponding to the IP reassembly ID. Then, the process proceeds to S1006 when the power is not supplied, and proceeds to S1007 when the power is supplied. In S1006, the ID manager 217 instructs the search device 207 to supply power to the search entry block of the IP reassembly search table corresponding to the IP reassembly ID, and the process proceeds to S1007.

  In step S1007, the ID manager 217 checks whether power is supplied to the bitmap table block of the bitmap controller 219 corresponding to the IP reassembly ID. The process proceeds to S1008 when the power is not supplied, and proceeds to S1009 when the power is supplied. In S1008, the ID manager 217 instructs the bitmap controller 219 to supply power to the bitmap table corresponding to the IP reassembly ID, and the process proceeds to S1009.

  In step S1009, the ID manager 217 checks whether power is supplied to the main memory block in the IP reassembly buffer area corresponding to the IP reassembly ID. The process proceeds to S1011 when power is supplied to the main memory block, and proceeds to S1010 when power is not supplied. In S1010, the ID manager 217 instructs the main memory control unit 103 to supply power to the IP reassembly buffer area of the main memory 104 corresponding to the IP reassembly ID, and the process proceeds to S1011.

  In S1011, the ID manager 217 outputs the ID value selected in S1002 (allocated by the allocation process), increments a counter that manages the number of IP reassembly ID used in S1012, and ends the process.

  In the present embodiment, the power supply instruction is performed according to the above-described procedure. However, any procedure may be used as long as power can be supplied to each hardware resource. For example, the order of S1003 to S1004 and the order of S1005 to S1006 may be reversed, and the order of other processes may be changed. In addition, when power is constantly supplied to one or more of the above-described blocks, the determination of whether power is supplied to the block and the processing of the power supply instruction may be omitted.

  Returning to FIG. 9, as described above, when the IP reassembly ID is transferred from the ID manager 217 to the sub-processor 204 (S901), the sub-processor 204 checks the result obtained in S901 in S902. If the ID value cannot be acquired and an error is output, the sub processor 204 outputs an IP reassembly resource acquisition failure (S908) and ends the process. On the other hand, if the ID value can be acquired, the process proceeds to S903.

  In step S903, the sub processor 204 records information indicating the reception position of the received fragment packet in the bitmap table of the bitmap controller corresponding to the acquired ID value. In step S904, the sub processor 204 transfers the fragment packet data to the IP reassembly buffer of the main memory 104 corresponding to the acquired IP reassembly ID value. Subsequently, in S905, the sub processor 204 sets and starts the IP reassembly timer of the communication timer 216 corresponding to the acquired IP reassembly ID value. In step S906, the sub processor 204 registers the IP reassembly search information in the search entry of the IP reassembly search table of the search device 207 corresponding to the acquired IP reassembly ID. After that, the sub processor 204 outputs IP reassembly resource acquisition success in S907 and ends the processing. Note that the order of these steps may be changed.

(IP reassembly ID initialization process)
Next, the flow of IP reassembly ID initialization processing by the main processor 101 will be described with reference to FIG. In this embodiment, the main processor 101 performs IP reassembly ID initialization processing, but a sub-processor in the TOE may execute this processing. This process is executed, for example, when the communication apparatus is turned on, and after this process, the processes shown in FIGS. 9 and 10 are executed.

  In S1101, the main processor 101 sets the maximum value of the IP reassembly ID in the ID manager 217. This set value is the maximum number of IP reassembling processes that can be executed simultaneously and determined for each system. Thereafter, the main processor 101 secures IP reassembly buffer areas for the maximum number of IP reassembly ID values on the main memory 104 (S1102). This area is secured in an area where power control is possible under the control of the main memory control unit 103. In this embodiment, the case where the IP reassembly buffer is secured on the main memory has been described. However, if the memory area is capable of power control for each buffer, the IP reassembly buffer is secured on another memory. May be.

  Subsequently, the main processor 101 sets the position information of the IP reassembly buffer secured in S1102 in the ID manager 217 (S1103). Based on this setting information, a power control instruction is given at the start or end of communication of a set of fragments to be reassembled into one data (that is, when an IP reassembly ID is acquired and released). Thereafter, the main processor 101 sets a search table for searching IP reassembly information in the search device 207 (S1104). Then, the main processor 101 instructs the ID manager 217 to start the power control of the hardware resource associated with the IP reassembly ID (S1105), and ends the process. Note that the order of the steps described above may be changed, or some steps may be deleted.

(IP reassembly resource release processing)
Next, the flow of IP reassembly resource release processing according to the present embodiment, which is executed in the sub processor 204, will be described with reference to FIGS.

  First, when communication about a set of fragments reassembled into one data is completed, the sub-processor 204 deletes an entry in an area corresponding to the IP reassembly ID value of the search device 207 in S1201 of FIG. . Then, the sub processor 204 clears the bitmap table corresponding to the IP reassembly ID value of the bitmap controller 219 (S1202), and stops the IP reassembly timer corresponding to the IP reassembly ID value (S1203). Further, in S1204, the sub processor 204 returns the IP reassembly ID value to the ID manager 217 and ends the process.

  Here, the IP reassembly ID return process executed by the ID manager 217 when the IP reassembly ID value is returned in S1204 will be described with reference to FIG. In step S1301, the ID manager 217 adds the returned ID value to the held IP reassembly ID value. That is, the ID manager 217 adds and holds the returned ID value as a candidate to be assigned to communication relating to IP reassembly that is newly started thereafter.

  Then, the ID manager 217 instructs to stop power supply for each hardware resource block corresponding to the returned IP reassembly ID value. Specifically, in step S1302, the communication timer 216 is instructed to stop the power supply of the IP reassembly timer corresponding to the ID value. In step S1303, the power supply stop of the entry in the IP reassembly search table corresponding to the ID value is detected by the search device 207. Instructed to. Further, the bitmap controller 219 is instructed to stop the power of the bitmap table corresponding to the ID value (S1304), and the power stop of the IP reassembly buffer area on the main memory 104 corresponding to the ID value is sent to the main memory control unit 103. Instructed (S1305). In step S1306, the ID manager 217 decrements the counter that manages the number of IP reassembly IDs used, and ends the process. For each of the above-described steps, for example, the order of power stop instructions may be changed, or some steps may be deleted.

  As described above, the communication apparatus according to the present embodiment includes an ID manager that manages the TCP socket and the IP reassembly process using IDs, and each of the communication protocol processes includes a plurality of IDs that are managed. Assign or release one ID. In the communication apparatus according to the present embodiment, each (hardware) resource is configured so that power can be controlled for each fine block, and the ID manager stores one or more IDs in association with each block. . And, according to the allocation and release of ID, the ID manager supplies power to or stops the block corresponding to the ID, or supplies or stops the clock for one or more resources. Take control. As a result, it becomes possible to perform detailed power supply control in units of hardware resources in accordance with the number of TCP sockets and the number of IP reassembles that are actually performing communication processing. Furthermore, such a configuration allows the storage device and hardware to be partially shut down according to the communication status while maintaining the maximum number of communication processes that can be executed simultaneously. Accordingly, power consumption can be reduced. In addition, since the ID manager controls the power supply in a lump, it is not necessary to individually control the power supply of the hardware resources, and it becomes possible to prevent an increase in processing load by performing the power supply control individually. .

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The present invention can also be realized by executing the following processing. That is, software (program) that realizes the functions of the above-described embodiments is supplied to a system or apparatus via a network or various storage media, and a computer (or CPU, MPU, or the like) of the system or apparatus reads the program. It is a process to be executed.

Claims (5)

A plurality of timers used for TCP protocol processing and corresponding to each of a plurality of TCP sockets;
A plurality of memories used for TCP protocol processing and corresponding to each of the plurality of TCP sockets;
Management means for managing the identifier indicating each of the plurality of TCP sockets, and the timer and the memory used for TCP protocol processing in the TCP socket indicated by each identifier,
When TCP communication using a new TCP socket is started , an assigning unit that assigns a first identifier indicating the new TCP socket to the new TCP socket ;
Start means for collectively starting power supply and clock supply to the timer and the memory corresponding to the first identifier managed by the management means when the assignment means assigns the first identifier. When,
When a TCP socket corresponding to the first identifier is released, power supply and clock supply to the timer and the memory corresponding to the first identifier managed by the management unit are collectively stopped. Stop means;
A communication apparatus comprising: It said management means, for one of the timer or the memory, and manages in association with the identifier of the multiple,
The stopping means supplies power and clocks to the timer and the memory corresponding to the plurality of identifiers managed by the management means when all the TCP sockets corresponding to the plurality of identifiers are released. the communication apparatus according to claim 1, wherein the benzalkonium stops collectively. The communication apparatus according to claim 1 or 2, wherein the timer and the memory is characterized by the early days including the hardware. Used for processing the TCP protocol, a plurality of timers corresponding to each of the plurality of TCP sockets are used for processing the TCP protocol, a plurality of memories corresponding to each of the plurality of TCP sockets, the A control method for a communication apparatus, comprising: an identifier indicating each of a plurality of TCP sockets; and a management unit that manages the timer and the memory used for TCP protocol processing in the TCP socket indicated by each identifier in association with each other. And
An allocation step of assigning a first identifier indicating the new TCP socket to the new TCP socket when TCP communication using the new TCP socket is started ;
A starting step of collectively starting power supply and clock supply to the timer and the memory corresponding to the first identifier managed by the management means when the first identifier is assigned in the assigning step; When,
When a TCP socket corresponding to the first identifier is released, power supply and clock supply to the timer and the memory corresponding to the first identifier managed by the management unit are collectively stopped. A stopping process;
A control method characterized by comprising:   The program for operating a computer as a communication apparatus of any one of Claim 1 to 3.

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